Abstract: A method and communication system for transmitting time-critical data, wherein selected datagrams are assigned to data streams and transmitted via paths for the data streams, where reservation requests are transmitted to a higher-level communication controller to reserve resources to be provided by the communication devices for transmitting data streams, in each case via a reservation function component, which is assigned to a first or second communication terminal or a communication device that is connected to the communication terminal and forwards datagrams, and where in the event of reservation requests, the higher-level communication controller ascertains a respective path and checks whether sufficient resources for transmitting the data streams while maintaining the specified service quality parameters are available in communication devices along the respective path, and the higher-level communication controller ascertains a proposed local cycle duration for selected communication devices.

Abstract: An optical transmission device includes a plurality of transmitting/receiving units provided on a substrate, each transmitting/receiving unit includes: an optical transmitter; an optical receiver; a polarization combiner/splitter; and a connection portion. In the connection portions which are arranged at the positions symmetrical to each other, a direction opposite, with respect to a virtual symmetry axis, to a direction of a main electric field on a plane perpendicular to an emission direction of an optical wave of the connection portion which is emitted from one of the connection portions to an outside is substantially orthogonal to a direction of a main electric field on a plane perpendicular to an emission direction of an optical wave of the connection portion which is emitted from the other of the connection portions to an outside.

Abstract: Example systems and related methods may relate to a synchronous first-in-first-out (FIFO) data buffer. The synchronous FIFO data buffer may include a counter. The counter may (i) receive a plurality of signals and (ii) output a count of total entries in the FIFO. The FIFO may further include a status generator that may (i) receive the plurality of signals and the count of total entries, and (ii) outputs a status signal. The FIFO may further include a selection generator that may (i) receive the count of total entries, the write signal, and the read signal, and (ii) output a data enable signal and a multiplexor selection signal. The FIFO may further include a scalable N×M flip-flop memory structure. N may be a number of entries in the memory structure and M may be a number of bits using flip-flops.

Abstract: Systems and methods for time slot allocation of time slots for bundled links in a shared mesh GMPLS for protect paths with different of COS may include time slot allocation divided into multiple phases with each phase having some qualification criterion to go to next phase or exit if the criterion is not met. For example, allocation of time slots for a circuit may include three phases—component selection phase, a connection admission phase, and an optimization phase.

Abstract: An optical circuit switching matrix includes a plurality of optical ports, each optical port being optically coupled to a respective one of a plurality of user nodes and an optical coupler having at least one input port optically coupled to the plurality of optical ports, and an output port. The optical circuit switching matrix also includes a wavelength demultiplexer having an input optically coupled to the output port of the optical coupler, and a plurality of output ports, each output port being optically coupled to a respective one of the plurality of optical ports.

Abstract: A data center network and a method for deploying the data center network. The data center network includes one core switch group, m cyclic arrayed waveguide grating (CAWG) groups, and m edge switch groups, where the core switch group includes k core switches; each CAWG group includes 2*Y N*N CAWGs, where the 2*Y CAWGs include Y uplink CAWGs and Y downlink CAWGs, the Y uplink CAWGs are connected to each core switch in the core switch group separately using an optical uplink, and the Y downlink CAWGs are connected to each core switch in the core switch group separately using an optical downlink; and each edge switch of an edge switch group is connected to an uplink CAWG and a downlink CAWG in a corresponding CAWG group separately. The present invention can reduce the number of optical fibers in a data center network.

Abstract: Technologies for generating a broadband optical output include a plurality of narrowband optical sources formed in a silicon substrate to generate a narrowband optical output, a plurality of input optical waveguides to route the narrowband optical output, an optical multiplexer formed in the silicon substrate to reflect the routed narrowband optical output, and an output optical waveguide to collect the reflected narrowband optical output to generate the broadband optical output. The output optical waveguide may route the broadband optical output to an output of the photonic integrated circuit.

Abstract: In one embodiment, photonic switching fabric includes an input photonic commutator switch configured to receive a photonic frame stream including a plurality of containerized photonic packets and a first high port count photonic switch coupled to the input photonic commutator switch. The photonic switching fabric also includes a second high port count photonic switch coupled to the input photonic commutator switch, where the input photonic commutator switch is configured to route the photonic frame to either the first high port count photonic switch or the second high port count photonic switch and an output photonic commutator switch coupled to the first high port count photonic switch and the second high port count photonic switch, where the output photonic commutator switch is configured to output a switched photonic frame.

Abstract: Time division multiplexed input signals (i.e., separated into time slots) are spread in each time slot with a destination code. This spreading is applied for destination identification as opposed to signal information modulation. Each spreading signal is associated with a particular destination for a particular time slot. These spread signals are then combined on a code division bus. Output signals for retransmission to the destinations are recovered from the bus by application of despreading codes. Each despread signal has a destination code which appears in its individual time slot. In a variant code division multiplexed signals are directed to a destination by use of time slot interchanger to achieve time division switching to route the CDMA multiplexed channels.

Abstract: A balanced, bufferless switch scalable to high capacities and requiring less processing effort with less internal fabric expansion in comparison with prior-art switches. The balanced, bufferless switch employs a pre-switching or post-switching balanced-connector.

Abstract: A packet-switched WDMA ring network has an architecture utilizing packet stacking and unstacking for enabling nodes to access the entire link capacity by transmitting and receiving packets on available wavelengths. Packets are added and dropped from the ring by optical switches. A flexible credit-based MAC protocol along with an admission algorithm enhance the network throughput capacity.

Abstract: The invention includes a method and apparatus for generating virtual clock signals for differing hierarchies in a communication system conveying data frames of differing hierarchies. Specifically, a method according to one embodiment of the invention includes receiving data frames of a first hierarchy, receiving at least one input clock signal, and generating a virtual clock signal using the at least one input clock signal and a clock enable signal. The clock enable signal is generated using at least one of a data rate ratio and a clock rate ratio. The virtual clock signal is adapted for converting at least a portion of the data frames of the first hierarchy to data frames of a second hierarchy. The frequency of the virtual clock signal is determined by applying the clock enable signal to a common clock signal.

Abstract: An apparatus is disclosed for permitting a mobile terminal having multiple, heterogeneous network connections (e.g., multiple wired or wireless transceivers of various types) to set up and maintain virtual connections over multiple networks to either the same or to multiple destinations. The mobile terminal can “load-share” traffic, i.e., it can distribute segments of traffic over a full set of heterogeneous networks, significantly improving the reliability and availability of communications. In a first embodiment, a mobile terminal is configured with multiple radio frequency (RF) transceivers. Operating system software is provided for dynamically establishing and maintaining traffic flow for user applications over multiple communications paths, and for automatically adapting to variations in the networking environment, application traffic flow requirements, end user preferences, or mobility.

Abstract: Systems and methods are described that provide network traffic engineering that obviate network over-provisioning by providing QoS to each traffic class. Embodiments dimension switching router LTE schedulers to ensure that each traffic class receives an appropriate QoS in terms of delay, jitter, Packet Loss Ratio and throughput. In addition to guaranteeing QoS, embodiments optimize transport cost, optimize switch-router port deployment, and work on top of IETF standards, IEEE standards, and MEF standards.

Abstract: A circulating switch comprises switch modules of moderate capacities interconnected by a passive rotator. Data is sent from a one switch module to another switch module either directly, traversing the rotator once, or indirectly through at least one intermediate switch module where the rotator is traversed twice. A higher capacity extended circulating switch is constructed from higher-capacity switch modules, implemented as common memory switches and having multiple ports, interconnected through a multiplicity of rotators preferably arranged in complementary groups of rotators of opposite rotation directions. A polyphase circulating switch having a low switching delay is derived from a multi-rotator circulating switch by providing programmable rotators having adjustable relative rotator-cycle phases. A low delay high-capacity switch may also be constructed from prior-art medium-capacity rotator space switches with mutually phase-shifted rotation cycles.

Abstract: A client (10) transmits a service request signal to a Web server (20). The Web server which has received the service request signal generates an ID for each session, and transmits the ID to the client together with window information. The client then transmits input voice information to a voice processing server (30) together with the ID. The voice processing server which has received the voice information and the ID processes the voice information, and transmits the processing result to the Web server together with the ID. The Web server prepares information reflecting the voice processing result obtained by the voice processing server in correspondence with the ID from the voice processing server, and transmits the information to the client.

Abstract: A transit memory assembly of a rotator-based switching node is logically partitioned into two sections, one operated as a common-memory switch fabric and the other as a time-shared space-switch fabric. The composition of data received at input ports of the switching node determines adaptive capacity division between the two sections. Based on an indication of traffic type, a controller of at least one input port selects one of the two sections. The space-switch section enables scalability to a high transport capacity while the common-memory section enables scalability to a high processing throughput. The switching node includes rotators and a bank of transit-memory devices that facilitate the incorporation of any mixture of periodic, aperiodic, contention-free exclusive-access, concurrent-access, and multicast switching.

Abstract: The invention relates to a method for transmitting compression parameters in a mobile communication system, comprising a mobile node, a first and a second packet switching node. In the method the second packet switching node is informed of the entry of the mobile node to an area controlled by the second packet switching node. At least one compression parameter is received from the first packet switching node to the second packet switching node. The second packet switching node informs at least one of the at least one compression parameter to the mobile node by way of layer-3 parameter renegotiation for a logical link connection. The benefits of the invention are related to improved reliability of packet data transmission to and from a mobile node.

Abstract: A high capacity switching node comprises a lattice structure of low-latency switch units and a plurality of balanced connectors interfacing electronic edge nodes to diagonal subsets of said switch units. The edge nodes may be collocated with the switch units or remotely located. The switch units may be bufferless, having optical switch-fabrics for example, thus requiring a compound vacancy-matching process. Using switch units each of dimension 64×64, a fast switching node having a dimension of the order of 10,000×10,000 can be constructed. With a typical wavelength-channel capacity of 10 Gb/s, the fast-switching node would scale to a capacity of 100 terabits per second, which is orders of magnitude higher than the capacity of known fast optical switches. A fast-switching optical switch of such scalability significantly reduces network complexity and cost.

Abstract: Systems and methods are described for high-speed memory assignment schemes for routing packets in a sharable parallel memory module based switch system. A method includes receiving a parameter, determining availability of memory location, determining if an available memory location is pre-assigned, and assigning a packet a parameter if the memory location is available. Systems of the present invention provides hardware and/or software based components for implementing the steps of receiving a parameter, determining available memory location, determining if available memory location is pre-assigned, and assigning a packet a parameter if the memory location is available.

Abstract: A method of time division multiplex switching reduces the implementation area by reducing the area required for both memory storage at each egress port and the multiplexing circuitry required. Ingress and egress processors are implemented to control the storage and selection of data grains to allow for the reduction in the memory and multiplexer areas.

Abstract: An Ethernet switch includes a plurality of ports, and the switch is configured to be operable within a temperature range of at least between approximately 0° C. and approximately 60° C. The switch is further configured to be operable within a non-condensing humidity range of at least between approximately 10% and approximately 95%. Also, the switch is configured to support at least one of a Virtual Local Area Network (VLAN), a Quality of Service (QoS), a Remote Monitoring (RMON), and a Spanning Tree.

Abstract: Disclosed is a method and circuit for synchronizing dual data buses. In one embodiment, the method includes a receiving circuit receiving first and second streams of multibit data portions transmitted via first and second parallel data buses, respectively, coupled thereto. The receiving circuit compares first-stream multibit data portions with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion. The receiving circuit stores into a first FIFO, all first-stream multibit data portions that follow the identified first-stream multibit data portion. The receiving circuit also compares second-stream multibit data portions with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion.

Abstract: Apparatus implements combined packetized time-division multiplexed (TDM) streams and TDM cross connect functions. The apparatus includes an input buffer, a reassembly state machine, a frame buffer, and a segmentation state machine. The frame buffer includes multiple bins for storing cell data. The segmentation state machine retrieves information from the bins as associated with each DS0 and assembles output cells for transmitting output DS0s. The cells may be in asynchronous transfer mode (ATM) format, allowing a single ATM backplane to be used for voice signals, data signals, and combined voice/data signals. Various types of ATM cell formats are supported.

Abstract: A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices is disclosed. The memory devices include a first memory bank configured for data being written to the first memory bank while data is read from the first memory bank at a timeslot and a second memory bank, which is smaller than the first memory bank and configured for writing the data read from the first memory bank to the second memory bank and reading data from the second memory bank. The system further includes an address comparer configured to compare a write address of the first memory bank with a read address of the first memory bank and select data for output from the first memory bank if the write address is smaller than the read address and select data from the second memory bank if the read address is equal to or smaller than the write address.

Abstract: A time division multiplex switching apparatus is provided for switching channels from any number of input data streams, each of which may have any of a plurality of data rates, to any of a plurality of output data streams, each of which may likewise have any one of a plurality of data rates. An input block 1 comprises a respective input channel for each input stream. Each channel has a variable delay circuit. The outputs of the channels are supplied to a buffer memory 3 which stores data from the input channels in a first order and reads out the data in a second order according to the channel connections required. A controller 2 controls the variable delay circuits 12–14 independently of each other so as to align the data streams from the input channels irrespective of the input stream data rates. For example, the streams may be aligned such that the zeroth channel of a predetermined frame in the input streams appear consecutively at the outputs of the input channels.

Abstract: Multicast call blocking is reduced in TST switch fabrics with the aid of an m-entry data structure. Each entry corresponds to one of m timeslots, and has 2n sub-entries corresponding to n input ports and n output ports. An N-cast call X:(y?z1, z2 . . . zN) is representable by associating a selected entry's yth input sub-entry with z1, z2, . . . zN of the selected entry's output sub-entries. Upon receipt of a call, the data structure entries are sequentially examined to detect the first entry for which a yth input sub-entry is unused and z1, z2, . . . zN output sub-entries are unused. If such an entry is detected, the call is scheduled for transmission in the corresponding timeslot. If there is no such entry and if N=1 the call cannot be scheduled; but, if N>1 the call is divided into two or more calls and an attempt is made to schedule them as above.

Abstract: An integrated services digital network private branch exchange, which is capable of automatically choosing a synchronization clock source. The integrated services digital network private branch exchange comprises a plurality of trunk chips, a plurality of subscribe chips, and a plurality of priority selection circuits. Wherein, the trunk chips connect to the network terminal via the trunk interface, and then connect to the central office via the network terminal to receive the frame synchronization clock output signal and the data clock output signal. Whereas, the subscribe chips connect to the terminal equipment via the subscribe interface. The priority selection circuits that are connected to each other in a daisy chain circuit manner are connected to the trunk chips to send out the frame synchronization clock output signal and the data clock output signal.

Abstract: A two-stage switching network that takes data from an input and first switches it through a space stage into a buffer. Data from the buffer is then switched in a time-space stage to an output. Each buffer, advantageously, holds one frame of data. Further, there are two buffers such that one may be filled from the input while the other is emptied to the output, and vice-versa. A maximum amount of data may be switched in space and time regardless of its origin and destination, effecting a switching network that is capable of the widest SONET-specified bandwidth.

Abstract: This invention relates to a switch structure and more particularly to a switch structure for circuit switching of telecommunications signals, such as, but not exclusively, data. A switch arrangement for a Group switch adapted to switch communication signals is provided, the switch arrangement including, a first switching module (SE-1 to SE-N) having at least a first switching element (SE-2) and a second switching element (SE-3); a first communication path (HWH) interconnecting the first and second switching elements (SE-2, SE-3) a second switching module (SE-N+1 to SE-2N) having at least a third switching element (SE-N+3), and a second communicating path (HWV) interconnecting the second module and first module. The second communication path is provided between modules allowing a distribution of the switching function with a minimum of connections and at the same time providing a switch structure that can be easily scaled up for increased capacity.

Abstract: Multiple streams of bits are received. One or more bits are selected from a stream of bits based, at least in part, on a space control register value and a time control register value. In one embodiment, a time control register stores a value indicating a selected bit from a sequence of bits, a counter counts bits in the sequence of bits from a predetermined bit, and a comparator is coupled to the time control register and to the counter to generate a load signal when a value stored in the time control register and a value provided by the counter are equal. The load signal causes the latch to load a value output by the multiplexer.

Abstract: Embodiments of an apparatus for forming a WDM signal having orthogonally polarized optical channels are disclosed. Utilizing the optical channels formed using non-polarization-maintaining components, the apparatus selectively controls a state of polarization (SOP) of each optical channel.

Abstract: A marching algorithm for the selection of middle stage switch elements in a network uses an arbitrary but settled sequence in which middle stage switch elements are sampled. The sequence is applied in the forward direction to find an appropriate middle stage switch element during connection and in a reverse direction during disconnection to find an appropriate middle stage switch element for rearrangement. All of the input switch elements use the same marching sequence. The marching algorithm is applicable to both single rate and multi-rate connections. In the case of multi-rate connections, multiple rearrangements may occur at disconnect to match the capacity of the terminated connection.

Abstract: This invention describes a method for transmitting and forwarding packets over a switching network using time information. The network switches maintain a common time reference, which is obtained either from an external source (such as GPS—Global Positioning System) or is generated and distributed internally. The time intervals are arranged in simple periodicity and complex periodicity (like seconds and minutes of a clock). A data packet that arrives to an input port is switched to an output port based on its order or time position in the time interval in which it arrives at the switch. The time interval duration can be longer than the time duration required for transmitting a data packet, in which case the exact position of a data packet in its forwarding time interval is predetermined. This invention provides congestion-free data packet switching for data packets for which capacity in their corresponding forwarding links and time intervals is reserved in advance.

Abstract: A time/space switching component is provided with multiple functionality that includes a time switching unit, of a space switching unit of a data channel sequence correction unit and of a control unit. As a result of corresponding mode selection, the different functionalities for a switching network are obtained with a single component, resulting in a significant reduction in an overall expenditure for development and manufacture.

Abstract: A switching system for a data stream utilizing striping with a parity stripe, so if a fabric of the system fails, the data stream can still be reconstructed with the parity stripe. The system uses receive and transmit interfaces which implement space division, and fabrics which implement hybrid space/time division.

Abstract: A method for transporting packets through an electronic internetwork is provided. The electronic network includes a plurality of nodes, and the transportation unit a frame. A frame is transported from a source node to one or more destination nodes. A frame comprises a payload. The payload of the frame includes one or more headers and one or more packets associated with each header. A source address is an address corresponding to the address of the source node of a packet, and a destination address is an address corresponding to the address of the destination node of a packet. A current node is a node processing a particular frame in the electronic internetwork. Each of the headers includes a destination address field that indicates the destination address of the associated packets. Headers provide mechanism for simplified routing and extracting packets.

Abstract: Methods for searching a composite path for virtual container signals in a similar CLOS switching network is provided that is capable of switching various signal tributaries. The method can include managing a link use state between each state with a linked list and a bit map, searching connectable candidate paths using the link use state and setting a selected or an optimal path among candidate paths as searched, and managing a connection state of channels in the set path using an N-tree data structure and a data structure.

Abstract: A method for communicating information is disclosed wherein a time slot is allocated in a time division multiple access system for a transmission from a subscriber to a headend. Synchronization of a clock of the subscriber with respect to a clock of the headend is enhanced using a message transmitted from the headend to the subscriber which is indicative of an error in a subscriber transmission time with respect to the time slot. A feedback loop process is used to determine at least one of fractional symbol timing correction and carrier phase correction of a transmission from the subscriber to the headend. Filter coefficients are generated at the headend from a ranging signal transmitted from the subscriber to the headend and transmitting the filter coefficients from the headend to the subscriber, the filter coefficients being used by the subscriber to compensate for noise in a transmission from the subscriber to the headend.

Abstract: A switching unit, equipped with a plurality of port cards and a plurality of switch cards connected in a non-parallel fashion to the port cards. Each port card has a first M-way commutator and a second M-way commutator, wherein the total number of first M-way commutators over all the port cards is N and wherein the total number of second M-way commutators over all the port cards is also N. Each switch card has a first N-way commutator and a second N-way commutator, wherein the total number of first N-way commutators over all the switch cards is M and wherein the total number of second N-way commutators over all the switch cards is also M. Each switch card further has a unit for controllably time switching a plurality of signals output by each first N-way commutator and providing a plurality of switched signals to the corresponding second N-way commutator.

Abstract: Apparatus implements combined packetized time-division multiplexed (TDM) streams and TDM cross connect functions. The apparatus includes an input buffer, a reassembly state machine, a frame buffer, and a segmentation state machine. The frame buffer includes multiple bins for storing cell data. The segmentation state machine retrieves information from the bins as associated with each DS0 and assembles output cells for transmitting output DS0s. The cells may be in asynchronous transfer mode (ATM) format, allowing a single ATM backplane to be used for voice signals, data signals, and combined voice/data signals. Various types of ATM cell formats are supported.

Abstract: A switch matrix among tributaries of a telecommunication network operating on flows of data which are arranged according to SDH protocol, said switch matrix comprising a set of parallel branches, each of said branches comprising at least a space stage able to select and pack from the input data flow a subset of data to be exchanged, a second time stage able to store the data subset to be exchanged and comprising a random access memory device associated with a write memory and a read memory, said write memory and read memory being driven by a microprocessor and a master counter. The invention is characterized in that the read memory and write memory of each random access memory device are updated in association with a spare read memory which is common to read memories on all branches in parallel and with a spare write memory which is common to write memories on all branches in parallel, respectively.

Abstract: A wide-coverage, high-capacity, switching network is modeled after a classical space-time-space switch. In the switching network, each of the space stages comprises geographically distributed optical space switches and the time stage comprises a plurality of geographically distributed high-capacity electronic switching nodes. User-access concentrators, each supporting numerous users, access the network through ports of the distributed optical space switches. A user-access concentrator is a simple device which need only have a single access channel to access the network, although two or more access channels may be used. Such a user-access concentrator can communicate with a large number of other user-access concentrators by time-multiplexing the access channel.

Abstract: Data frames are converted to a format suitable for transparent, flexible concatenated transport such that a network element not supporting flexible concatenation may transparently pass the data frames. Flexible concatenation involves nonstandard data frames such as an STS-4c or an STS-Nc in which the time slots do not occupy rigidly defined contiguous time slots. In transparent flexible concatenation, the pointer from the parent time slot is used for each of the child time slots and the concatenation identifier is set to indicate no concatenation. In this way, the concatenated data appears to be a series of conventional STS-1s such that pointer processing may be successfully accomplished even by a network element not capable of handling non-standard concatenations. A downstream receive framer reconstructs the original STS-Nc based on the N STS-1s and a concatenation table the contents of which are shared between the transmit framer and the downstream receive framer.

Abstract: The present invention guarantees that voice data (and other information types) will switch within a predetermined time period. Systems and methods consistent with the present invention accomplish this guarantee by, among other things, establishing permanent virtual paths or circuits between each network element, guaranteeing each voice line a slot in a packet in each frame, employing both octet switching and packet switching, synchronizing the operation of the network elements to a reference clock, and providing several levels of network redundancy.

Abstract: Techniques to test performance of terminals and access points in CDMA data (e.g., cdma2000) systems. A framework of protocols and messages is provided to support systematic performance testing of terminals and to ensure interface compatibility. The framework comprises a Forward Test Application Protocol (FTAP) for testing forward channels and a Reverse Test Application Protocol (RTAP) for testing reverse channels. Techniques are also provided to (1) test different types of channels (e.g., traffic channels as well as auxiliary channels), (2) test bursty data transmissions, (3) support “persistence” testing (i.e., continued testing over connection and disconnection), (4) force the settings of certain auxiliary channels (e.g., so that the error rate of the channels may be determined), and (5) collect, log, and report various statistics that may be used to derive performance metrics such as throughput and packet error rate.

Abstract: An exchange equipment using STM able to achieve an improvement of an efficiency of use and an improvement of ease of increase of terminal cards, that is, an STM type exchange, including a time switch, for performing exchange processing of time division multiplexed data, wherein a ring highway is connected via a terminal common unit to an upstream highway and a downstream highway coupled to this time switch via a highway interface unit or directly and wherein a plurality of terminal cards are connected to this ring highway. Each terminal card is provided with an add/drop unit which drops and adds the data from and to an assigned time slot on the ring highway according to control information indicating time slot assignment information determined by the control unit and adds the data and with a card control unit which controls the add/drop unit.

Abstract: A system for transporting traffic is provided. The system transports traffic from a first network access path over a transport network path having multiple channels and transports traffic from a second network access path over the same transport network path. The system transports the traffic using transport network path channels wherein the bandwidth of the first network access path is higher than the capacity of any of the transport network path channels and wherein the bandwidth of the second network access path is higher than the capacity of any of the transport network path channels. The system allocates a first quantity of the transport network path channels for transporting traffic from the first network access path. The system allocates a second quantity of the transport network path channels for transporting traffic from the second network access path. And, the sum of the first quantity plus the second quantity is less than or equal to the total number of channels in the transport network path.

Abstract: A highway switch control system for controlling a time division multiplex highway switch of T-S-T three-stage switches in a multiprocessor typed electronic switching system, comprises a plurality of sets of first switches of time sharing switching method, second switches of highway switching method, third switches of time sharing switching method, and processors for controlling each switch, the two processors to be connected together getting information on spare time slots of the mutual switches and deciding time slots for use in the connection, thereby controlling a connection between required switches.

Abstract: An implementation of a synchronous state machine, responsive to a time division multiplexed external input signal having plural time slots in a repetitive structure, has all of its flip-flop outputs hooked up to a state memory so that the state produced by each time slot is stored until that time slot is again repeated at the external input, at which point the stored state is recalled from memory for being input along with the incoming time slot data; in this way the hardware is shared between time slots. A substitution element is disclosed having a flip-flop with its output routed to memory and for providing a memory output as its output. A design methodology is taught whereby a state memory and a substitution element is substituted for each flip-flop in a synchronous state machine implemented for one time slot of a repeating pattern of time slots.