Abstract: Some embodiments provide a method for applying a security policy defined for a logical network to an MHFE that integrates physical workloads (e.g., physical machines connected to the MHFE) with the logical network. The method applies the security policy to the MHFE by generating a set of ACL rules based on the security policy's definition and configuring the MHFE to apply the ACL rules on the network traffic that is forwarded to and/or from the physical machines. In order to configure an MHFE to implement the different LFEs of a logical network, some embodiments propagate an open source database stored on the MHFE, using an open source protocol. Some embodiments propagate a particular table of the database such that each record of the table creates an association between a port of an LFE stored in a logical forwarding table and one or more ACL rules stored in an ACL table.

Abstract: A novel multi-stage folded Clos network and a linecard for use in a network is disclosed. The Clos network can consist of three stages, an access stage, a lower stage, and an upper stage. The access stage and the upper stage can include a plurality of switches or conventional access points. The lower stage can include a plurality of linecards. Each linecard can be made of two switch chips, each of which are connected to the ports of the linecard, and contain the same number of ports. Each switch chip can forward information in only one direction and one is used to send direction from the access stage to the upper stage, and the other from the upper stage to the access stage. The lower stage can consist of a number of sub-stages, each sub-stage can be entirely of either conventional switches or linecards.

Abstract: A service access control method, a service access control apparatus and a cluster terminal for a broadband cluster system are provided. The method includes: determining a service type of a to-be-accessed service, the service type including a service with a low delay requirement, determining whether a current subframe meets a preset access condition for a service with a low delay requirement when it is determined that the to-be-accessed service is the service with the low delay requirement, and completing access of the to-be-accessed service if the current subframe meets the preset access condition for the service with the low delay requirement.

Abstract: Methods and systems are presented for testing smart card operations and functions for multiple smart cards and associated readers. The methods and systems use a multiplexer and a demultiplexer to connect smart card sockets to probe cards that can be inserted into smart card readers using actuators. The methods and systems described herein test a response of a selected smart card reader or terminal connected to the smart card reader to insertion of the probe card.

Abstract: Certain aspects of the present disclosure are directed to an apparatus for wireless communication. The apparatus generally including a processing system configured to generate a first frame including an indication of whether resources are available to be shared with a first one or more wireless nodes, where the apparatus is part of a first basic service set and the first one or more wireless nodes are part of one or more second basic service sets, and a first interface configured to output the first frame for transmission.

Abstract: Some embodiments provide a method for applying a security policy defined for a logical network to an MHFE that integrates physical workloads (e.g., physical machines connected to the MHFE) with the logical network. The method applies the security policy to the MHFE by generating a set of ACL rules based on the security policy's definition and configuring the MHFE to apply the ACL rules on the network traffic that is forwarded to and/or from the physical machines. In order to configure an MHFE to implement the different LFEs of a logical network, some embodiments propagate an open source database stored on the MHFE, using an open source protocol. Some embodiments propagate a particular table of the database such that each record of the table creates an association between a port of an LFE stored in a logical forwarding table and one or more ACL rules stored in an ACL table.

Abstract: Provided are a synchronization method, a wide area system protection apparatus, a plant station and a computer readable storage medium. The method includes: sending to a second plant station a first data frame that includes a sequence number p and a sending timestamp of the first data frame; receiving a second data frame sent by the second plant station, and recording a receiving timestamp of the second data frame, the second data frame including a sequence number q of the second data frame, a sending timestamp of the second data frame and a receiving timestamp of the first data frame, and the first data frame being adjacent to the second frame on the second plant station; calculating a time phase difference and a crystal oscillator frequency deviation between the first plant station and the second plant station; and adjusting time and a clock frequency of the first plant station.

Abstract: Embodiments of systems and methods for sending messages between cores across multiple field programmable gate arrays (FPGAs) and other devices are disclosed. A uniform destination address directs a message to a core in any FPGA. Message routing within one FPGA may use a bufferless directional 2D torus Network on Chip (NOC). Message routing between FPGAs may use remote router cores coupled to the NOCs. A message from one core to another in another FPGA is routed over a NOC to a local remote router then to external remote router(s) across inter-FPGA links or networks to the remote router of the second FPGA and across a second NOC to the destination core. Messages may also be multicast to multiple cores across FPGAs. A segmented directional torus NOC is also disclosed. The insertion of shortcut routers into directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth.

Abstract: Disclosed herein is a processing system, including: a GPU generating a video; a memory storing data; a data bus connecting the GPU and the memory to each other; a DMA controller connected to the data bus; an input/output bridge connected to the data bus and connected to an external bus for transferring data to and from an external processing system which cooperates with the processing system; and a CPU cooperating with the GPU to share the data stored in the memory. The GPU issues a data transfer instruction of the data stored in the memory to the DMA controller without intervention of the CPU. The DMA controller controls, when the data transfer instruction is received, the input/output bridge to transfer the data stored in the memory to the external processing system.

Abstract: An indication of an input data stream comprising data records, stored at a stream management service, that are to be batched for a computation at a batch-oriented data processing service is received. A set of data records of the input data stream are identified, based on respective sequence numbers associated with the records, for a particular iteration of the computation. Metadata associated with the particular iteration, comprising identification information associated with the set of records on which the computation is performed during the particular iteration, is saved in a repository.

Abstract: Some embodiments provide a method for a hardware forwarding element. Based on a set of characteristics of a packet, the method determines to copy a packet to a particular temporary storage of a set of temporary storages of the hardware forwarding element. Based on a property of the particular temporary storage, the method stores only a particular portion of the packet in the particular temporary storage. A same size portion of each packet copied to the particular temporary storage is stored in the particular temporary storage.

Abstract: Some embodiments provide a method for applying a security policy defined for a logical network to an MHFE that integrates physical workloads (e.g., physical machines connected to the MHFE) with the logical network. The method applies the security policy to the MHFE by generating a set of ACL rules based on the security policy's definition and configuring the MHFE to apply the ACL rules on the network traffic that is forwarded to and/or from the physical machines. In order to configure an MHFE to implement the different LFEs of a logical network, some embodiments propagate an open source database stored on the MHFE, using an open source protocol. Some embodiments propagate a particular table of the database such that each record of the table creates an association between a port of an LFE stored in a logical forwarding table and one or more ACL rules stored in an ACL table.

Abstract: An electronic device includes circuitry configured to establish a steady-state connection with another device via a communication link. A backchannel data frame is detected in a steady-state data stream received from the other device via the communication link at a first predetermined data rate. The circuitry is configured to modify one or more signal transmission parameters based on signal information included in the backchannel data frame.

Abstract: A relay device includes a target port coupled to another device; and a processor coupled to the target port and configured to extract identification information on the other device and identification information on a link aggregation group (LAG) configuration applied to the other device, from a frame received through the target port, and determine LAG configuration to be applied to the target port based on the identification information on the other device and the identification information on the LAG configuration applied to the other device.

Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Abstract: The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost).

Abstract: An image processing apparatus of one aspect of the present invention determines, upon receipt of a packet in a power saving state at a second communication rate slower than a first communication rate, whether or not to change the communication rate, on the basis of a communication protocol type and a port number, and an attribute of the packet represented by a data section of the packet. If the communication protocol type, the port number, and the attribute of the received packet indicate a request for a service predetermined as a network service that corresponds to the first communication rate, the image processing apparatus changes the communication rate from the second communication rate to the first communication rate at the time of shifting from the power saving state to the normal power state so as to provide the service.

Abstract: The disclosure relates to a method 10 performed in a scheduling device 3 for scheduling communication resources to a wireless device 4 configured for wireless communication within a communication system 1. The method 10 comprises detecting 11, within a group of wireless devices of a first priority class, a first wireless device 4 to be scheduled; determining 12 a cluster time for the first wireless device 4; and scheduling 13, for the duration of the determined cluster time, consecutive communication resource units to the first wireless device 4.

Abstract: A method and apparatus of a device that broadcasts data to multiple hardware forwarding engines is described. In an exemplary embodiment, a central processing unit of the device receives the data to broadcast to the plurality of hardware forwarding engines. The device further writes the data to a broadcast log. In addition, the device transmits a signal to one or more co-processors that the data is available to be read, wherein each of the plurality of hardware forwarding corresponds to one of the one or more co-processors. Each of these co-processors reads the data in the broadcast log by receiving the signal that the data is ready to be read from the broadcast log. In addition, each co-processor determines a broadcast log entry for the data for that co-processor. Each co-processor further reads the data from the broadcast log entry via a direct memory access in memory that stores the broadcast log and the plurality of hardware forwarding engines use the data to process network traffic.

Abstract: A digital audio conferencing system has a fixed base station that is in communication with a far end (R.E.) system over a communication network. The base station is associated with a wireless loudspeaker and one or more wireless microphones. The base station operates to receive F.E. audio signals to be played by the wireless loudspeaker, and it operates to remove acoustic echo picked up by the wireless microphones. A first clock controlling F.E. audio signal sampling at the base station, and a second clock controlling audio signal sampling and at a wireless microphone are synchronized to one master, reference clock that controls the operation of the base station. Acoustic echo included in an audio signal picked up by a wireless microphone is removed by AEC functionality running in the base station.

Abstract: Systems, methods, devices, and network architectures are disclosed for creating and implementing secure wireless, wired, and/or optical networks using specially modified “stealth” packets, cells, frames, and/or other “stealth” information structures. This enables stealth packets, network elements, and networks to have a low probability of detection, interception, and interpretation. The “stealth” packets, switches, networks, and methods provide invisibility or “cloaking” by modifying previously existing standards rules for packet structures, protocols, timing, synchronization, and other elements. Stealth packets, network elements, and networks may be further enhanced with encryption techniques by encrypting various parts of, or the entire packet structure itself, for example, headers, preambles, payload, and/or other packet elements.

Abstract: A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract: Embodiments of the present invention provide systems, devices and methods for improving the efficient deployment and configuration of networking equipment within a network build-out. In certain embodiments of the invention, an iterative analysis of inter-node equipment placement and connectivity, and inter- and intra-node traffic flow is performed to identify a preferred deployment solution. This analysis of deployment optimization takes into account both configurations from a network node perspective as well as from a network system perspective. Deployment solutions are iteratively progressed and analyzed to determine a preferred solution based on both the cost of deployment and satisfaction of the network demands. In various embodiments of the invention, a baseline marker is generated from which the accuracy of the solution may be approximated that suggests to an engineer whether the deployment is approaching an optimal solution.

Abstract: An embodiment of the invention may comprise pairing a first switching module with a second switching module such that the first switching module is enabled to switch signals received via its first input ports and its second input ports to its first output ports and second output ports, wherein the signals received by the first input ports of the first switching module are communicated from the first output ports of the second switching module, and the signals communicated by the first output ports of the second switching module are signals received by the second input ports of the second switching module and forwarded to the first output ports of the second switching module.

Abstract: A switching device comprises a plurality of switch cores, each switch core having a plurality of ports associated with the switch core. A first switch core is configured to perform ingress processing of a data frame. The data frame is then directed to a second switch core that is configured to perform egress processing of the data frame.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Abstract: A method and apparatus are provided for multiplexing one or more Low-Order (LO) ODUj/ODUflex clients into a High-Order (HO) ODUk in an Optical Transport Network (OTN). LO bytes are multiplexed in accordance with a tributary slot assignment for a selected LO ODUj of the HO ODUk stream using a permutation matrix. In an implementation, each byte on each ingress port of a W-port space-time-space switch is configurably assigned to an associated timeslot of an associated egress port, using time-division multiplexing. The number of TribSlots assigned to an ODUflex may be increased and decreased hitlessly. A Clos-like Space-Time-Space switch is used to interleave bytes from Low-Order ODUk words into High-Order ODUk words.

Abstract: The addition of high throughput capability elements to beacon frames and peer link action frames in wireless mesh networks enable the utilization of desirable features without further modifications to the network. Rules can be established for high throughput mesh point protection in a mesh network, Space-time Block Code (STBC) operations and 20/40 MHz operation selections. However, features such as PSMP (power save multi-poll) and PCO (phased coexistence operations) are barred from implementation to prevent collisions.

Abstract: Time division multiplexed input signals (i.e., separated into time slots) are spread in each time slot with a destination code. This spreading is applied for destination identification as opposed to signal information modulation. Each spreading signal is associated with a particular destination for a particular time slot. These spread signals are then combined on a code division bus. Output signals for retransmission to the destinations are recovered from the bus by application of despreading codes. Each despread signal has a destination code which appears in its individual time slot. In a variant code division multiplexed signals are directed to a destination by use of time slot interchanger to achieve time division switching to route the CDMA multiplexed channels.

Abstract: The deployment and scaling of a network of electronic devices can be improved by utilizing one or more network transpose boxes. Each transpose box can include a number of connectors and a meshing useful for implementing a specific network topology. When connecting devices of different tiers in the network, each device need only be connected to at least one of the connectors on the transpose box. The meshing of the transpose box can cause each device to be connected to any or all of the devices in the other tier as dictated by the network topology. When changing network topologies or scaling the network, additional devices can be added to available connectors on an existing transpose box, or new or additional transpose boxes can be deployed in order to handle the change with minimal cabling effort.

Abstract: A time-space switch in a ring architecture includes input circuitry including N links each receiving M timeslots, a two-dimensional matrix of a plurality of switching circuits, the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N links in a pipelined manner, and output circuitry including N links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix. The input circuitry, the two-dimensional matrix, and the output circuitry are arranged in a ring architecture therebetween. A link encoding protocol method performed in electrical circuitry includes receiving a plurality of time slots, grouping the plurality of time slots into time slot groups, performing a cyclic redundancy check between adjacent time slot groups, 64/65B encoding the time slot groups, and forward error correction encoding a plurality of 65B codewords from the 64/65B encoding.

Abstract: A switching device in a network system for transferring data includes one or more source line cards, one or more destination line cards and a switching fabric coupled to the source line cards and the destination line cards to enable data communication between any source line card and destination line card. Each source line card includes a request generator to generate a request signal to be transmitted in order to obtain an authorization to transmit data. Each destination line card includes a grant generator to generate and send back a grant signal to the source line card in response to the request signal received at the destination line card to authorize the source line card to transmit a data cell to the destination line card.

Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Abstract: A cross-connect system includes a mapping unit that maps second signal frames on which cross-connection is performed with a space switch, into third signal frames on which cross-connection is performed with the space switch and a time switch; a selection unit that selects either first signal frames on which cross-connection is performed with the space switch and the time switch and corresponding clock signals, or the third signal frames and corresponding clock signals; a cross-connection unit that receives either the first signal frames and corresponding clock signals or the third signal frames and corresponding clock signals selected by the selection unit and performs cross-connection for either the first signal frames or the third signal frames; and a demapping unit that demaps the third signal frames output from the cross-connection unit into the second signal frames and output the second signal frames.

Abstract: A packet switch that scales gracefully from a capacity of a fraction of a terabit per second to thousands of terabits per second is disclosed. The packet switch comprises edge nodes interconnected by independent switch units. The switch units are arranged in a matrix having multiple rows and multiple columns and may comprise instantaneous or latent space switches. Each edge node has a channel to a switch unit in each column and a channel from each switch unit in a selected column. A simple path traversing only one of the switch units may be established from each edge node to each other edge node. Where needed, a compound path comprising at most two simple paths may be established for any edge-node pair. In a preferred configuration, the switch units connect at input to orthogonal sets of edge nodes. A distributed control system expedites connection-request processing.

Abstract: A transmission apparatus stores frame data of a first frame in a second frame having a bit rate different from that of the first frame through regulation of the amount of stuffs to be stored in the second frame. The transmission apparatus includes: a storage unit storing the first-frame frame data; a first control unit controlling a timing of writing the first-frame frame data in the storage unit based on first stuff information indicating the amount of stuffs contained in the first frame; an arithmetic and logic unit obtaining second stuff information indicating the amount of stuffs to be contained in the second frame based on a bit rate ratio between the first frame and the second frame; and a second control unit controlling a timing of reading out the first-frame frame data stored in the storage unit based on the second stuff information.

Abstract: A multi-stage switching system comprises a first stage including a plurality of groups of switching devices. Each group of switching devices includes more than one switching device, and each group of switching devices is associated with a corresponding single device identifier (ID). A second stage includes a plurality of switching devices. The switching devices of the first stage are coupled to the switching devices of the second stage via a plurality of uplinks. Switching devices of the first stage are configured to associate a target device ID and a target port ID to a data unit received via a front port of the switching system. The switching devices of the first stage and the switching devices of the second stage are configured to direct the data unit through the switching system using the target device ID and a target port ID.

Abstract: A method, an apparatus, and a system for processing packets are disclosed. The method is applied to a distributed architecture of multiple service boards; the distributed architecture includes a main control board, at least one service board, and at least one interface board. The method includes: determining a specified CPU corresponding to a received packet; and, by the service board corresponding to the CPU, processing the received packet. Through the embodiments of the present invention, the received packets are processed in the service board corresponding to the specified CPU. Therefore, the packets are evenly distributed to all service boards for being processed, the workload of the main control board is relieved, the service throughput is increased significantly, and the packet processing efficiency of the whole architecture is improved.

Abstract: Aggregation Switches connected via a virtual fabric link (VFL) are each active and each coupled to a multi-chassis link aggregate group (MC-LAG), which is assigned to a multi-chassis link aggregate group virtual local area network (MC-LAG VLAN). A virtual Internet Protocol (IP) interface is allocated to the MC-LAG VLAN and configured on both Aggregation Switches.

Abstract: A stored transmission packet having a structure intended for use in a new link-adaptation mechanism, and a method and an apparatus for transmitting the transmission packet using the same are disclosed. The structure includes a payload composed of a plurality of transmission data units, a MAC header appended to the payload, and a PHY header appended to the MAC header, wherein the payload includes a link recommendation command in which information on a transmission mode is recorded, among a link-adaptation mechanism including Link Assessment, in which the state of a channel used to transmit and receive the transmission packet and the quality thereof is assessed, Link Recommendation, in which a transmission mode suitable for a current channel state is recommended using the result of Link Assessment, and Link Adjustment, in which the channel state is adjusted using information on the recommended transmission mode.

Abstract: Methods and systems for routing frames are provided. A system includes an initiator operationally coupled to a first switch that is coupled to a second switch. The first switch includes a plurality of ports for sending and receiving frames and includes a routing table that identifies a port identifier steering table based on an area field of a frame header of a frame received by the first switch. The first switch also includes a plurality of port identifier tables, where each port identifier table is associated with a unique area field and identifies a same port of the first switch for a plurality of area fields. The second switch stores an area steering table with port identification information associated with an area field of a frame header of a frame received by the second switch and a same port of the second switch is assigned to multiple area fields.

Abstract: A hierarchy of schedules propagate minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule. The minimum guaranteed scheduling rate for a parent schedule entry is typically based on the summation of the minimum guaranteed scheduling rates of its immediate child schedule entries. This propagation of minimum rate scheduling guarantees for a class of traffic can be dynamic (e.g., based on the active traffic for this class of traffic, active services for this class of traffic), or statically configured. One embodiment also includes multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different categories of traffic (e.g., propagated minimum guaranteed scheduling rate, non-propagated minimum guaranteed scheduling rate, high priority, excess rate, etc.) of scheduled items can be propagated through the hierarchy of schedules accordingly without being blocked behind a lower priority or different type of traffic.

Abstract: An apparatus that includes W interfaces to a circuit-switched network, where W is an integer number that equals the product of smaller integer numbers X and N. The apparatus also includes X discrete switching apparatus each having N ones of the W network interfaces, as well as a plurality of switching-expansion interconnects each interconnecting ones of the X switching apparatus, such that the W network interfaces are collectively interconnected in a non-blocking manner.

Abstract: A method and apparatus for selective packet discard have been disclosed where two bits are added to a packet to indicate various discard options.

Abstract: Techniques are described for providing managed virtual computer networks that have a configured logical network topology with virtual networking devices, such as by a network-accessible configurable network service, with corresponding networking functionality provided for communications between multiple computing nodes of the virtual computer network by emulating functionality that would be provided by the virtual networking devices if they were physically present.

Abstract: A serial channel switch circuit and modular packet switch using the serial channel switch circuits are disclosed. The serial channel switch circuit has a reconfigurable table for internal logical-to-physical channel switch translation. Depending on the slot in which a card containing such a serial channel switch circuit is inserted in the modular packet switch, its serial channel switch circuit may receive a different set of reconfigurable table values that are specific to that location. A global set of logical channel values can be applied to each card, which performs logical-to-physical channel mapping according to its location in the modular packet switch. Other embodiments are also described and claimed.

Abstract: A scalable switch, a system of switches and methods, configured to sense a carrier at the output of the respective switch. The invention intelligently, and dynamically, controls the connection of a respective switch input to a respective switch output as a function of a carrier being present, or absent, at a selected output. Alternatively, a control plane is adopted to make request to send and acknowledge clearance to send. These control methods operate on a step-by-step manner allowing fast and parallel connectivity to be established to connect a variety of interfaces, including Ethernet, PCI, SCSI, and FibreChannels. The present invention reduces switch cost, energy cost, and switch volume, while allowing scalability of connection requirements, reduction of delay, and promotion of green IT.

Abstract: Expanding the coverage of a time-shared network comprising electronic edge nodes interconnected by bufferless fast-switching optical nodes is enabled by combining spatial switching with temporal switching. The output side of each edge node preferably connects to a large number of core switches through individual time-locked channels and the input side preferably connects to each of a small number of core switches through a channel band having a sufficiently large number of channels. Wavelength routers may be used to aggregate individually-routed channels into WDM links.

Abstract: A method for transmitting data in TDM mode is provided to solve the problem in the prior art that the data processing between a transmitter side and a receiver side could not be real time and the delay time during data transmitting would be longer. The method comprises: packaging TIME DIVISION MULTIPLEXING (TDM) frame head information and data to be sent into a TDM frame at a transmitter side, and transmitting the TDM frame to a receiver side; receiving the TDM frame at the receiver side. With the solution according to the present invention, it is possible to perform real time data processing between the transmitter side and the receiver side and shorten the delay time during data transmitting.