Abstract: Methods, apparatuses, and systems are presented for transmitting data packets in a wireless network over a multi-access channel involving sequentially sending a plurality of medium access control (MAC) data packets from a transmitter over the multi-access channel, using a physical layer protocol based on a standard physical layer protocol having a short interframe spacing (SIFS), wherein the plurality of MAC data packets includes at least a first data packet and a second data packet separated by a reduced interframe spacing that is less than SIFS, attempting to receive the plurality of MAC data packets at a receiver using the physical layer protocol, including the first data packet and the second data packet separated by the reduced interframe spacing, and sending from the receiver a single acknowledgement packet associated with attempting to receive the plurality of MAC data packets.

Abstract: A method of processing data based on programmed instructions includes referencing a number of locations in memory by forming addresses and correct buffer mappings corresponding to separate buffers in the plurality of buffers, and communicating data from the referenced locations in memory to a processing unit. The processing unit concurrently receives inputs from the separate buffers in the plurality of buffers and outputs to another buffer in the plurality of buffers.

Abstract: A multiport concentrator concentrates network data from different links in a network and carried on a plurality of lower speed lines into a stream of data carried on a higher speed line. A measurement system determines network statistics from the stream of data carried by the higher speed line.

Abstract: A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data reading and writing. The design issues a first command or access command, such as a read command or write command to one memory bank, followed by an active command to a second memory bank, enabling efficient reading and writing in a multiple data flow environment, such as a SONET/SDH virtual concatenation environment using differential delay compensation.

Abstract: The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a group includes one or more nodes. The memory locations can be quickly searched to determine the group that represents the shortest distance from the source node and that includes one or more nodes. Nodes may be grouped into additional groupings that do not correspond to the set of memory locations, when the distance from the source node to the nodes exceeds the range of memory locations. Advantageously, the disclosed system and method provide the ability to reach asymptotically optimal performance.

Abstract: A communication system supporting communication of packet data. It comprises a core network, which includes a number of packet data support nodes, a number of gateway nodes for communication with external packet data networks, and a number of radio networks. Each radio network includes radio network control means. At least some of the packet data support nodes include a separate functional server node. A number of the functional server nodes are provided to control at least a number of radio network control means such that the functional server nodes are able to control any radio network control means.

Abstract: A response monitoring apparatus using a remote including an electrical circuit including a user activated input, a transmitter, and a receiver, where the electrical circuit is adapted to detect operation of the user activated input and temporarily activates the receiver. A validation and error checking system ensures valid transmissions occurring in both wireless and wired communications. The validation and error checking system retrieves data from the remote memory to create transmission data groups. The validation and error checking system calculates a checksum value for the transmission data groups and creates a checksum data group that includes the checksum. The validation and error checking system transmits the data and ensures that the data is properly sent.

Abstract: Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a virtualization controller for controlling data transfer between a host system and a plurality of storage devices. The virtualization controller comprises a plurality of first ports for connection with the plurality of storage devices each having a storage area to store data; a second port for connection with the host system; a processor; and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area.

Abstract: The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a network identify a new message flow, they determine the proper processing for packets in that message flow and cache that information for that message flow. Thereafter, when routers in a network identify a packet which is part of that message flow, they process that packet according to the proper processing for packets in that message flow. The proper processing may include a determination of a destination port for routing those packets and a determination of whether access control permits routing those packets to their indicated destination.

Abstract: A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices is disclosed. The memory devices include a first memory bank configured for data being written to the first memory bank while data is read from the first memory bank at a timeslot and a second memory bank, which is smaller than the first memory bank and configured for writing the data read from the first memory bank to the second memory bank and reading data from the second memory bank. The system further includes an address comparer configured to compare a write address of the first memory bank with a read address of the first memory bank and select data for output from the first memory bank if the write address is smaller than the read address and select data from the second memory bank if the read address is equal to or smaller than the write address.

Abstract: A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40).

Abstract: Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch.

Abstract: On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous data, separate from video data. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value corresponding to a memory address within the display device forming a buffer. When received by the display device the on-screen-display graphics data is loaded into the appropriate memory locations within the buffer corresponding to the address values. At the display device, an embedded stream processor is utilized to strip the header information from each packet and determine the appropriate memory location that the data is to be stored. A trigger packet is sent at the end of the data stream for a screen of on-screen-display graphics.

Abstract: Shared memory provides buffering and switching for all frames that flow through a fiber channel switch. Received frames are written to shared memory by the receiving port then read from shared memory by the transmitting port. Shared memory provides for data to be written to a buffer at one rate, and read from a buffer at a different rate, or vice versa.

Abstract: A digital switching system includes a multiplexer for multiplexing time slots from a plurality of circuits, a switching memory for storing and switching the multiplexed data for one frame period, switching control equipment for directing the interchange of the time slots stored in the switching memory in response to a switching request from an upper layer controller in a network, and a demultiplexer for demultiplexing into the plurality of circuits the time slot data as read out using address data supplied from the switching control equipment. The switching control equipment includes a control memory unit for writing connection information from the upper layer controller to either a first or a second control memory, and sequentially reading out the stored connection information in read-out order for the switching memory, and a selection unit for selecting read-out from either the first or the second control memory in response to the switching request.

Abstract: An improved analog front end and methods for increasing the power efficiency of duplex signals on a transmission line are disclosed. The improved analog front end bifurcates a hybrid into a fixed portion and an adaptive portion. The adaptive portion combines a biquad and a summer to produce a filter transfer function suited to compensate for transmission line irregularities. A method for configuring a local transceiver to minimize power requirements at a remote transmitter is disclosed. Broadly the method entails, applying a transmit signal to a front end in the absence of a remote signal; optimizing the transmit signal power; recording the reflected transmit signal; applying an adaptive filter in response to transmission line irregularities; and controllably adjusting the adaptive filter to minimize the amplitude of the reflected version of the transmit signal in the receive path. A method for recovering a remotely generated signal is also disclosed.

Abstract: An architecture, method, and apparatus for managing a data buffer (Data Buffer Management DBM). A data buffer within the DBM is an unified linear memory space, and is divided into numbered physical pages with a predetermined page size. A memory map translates logical address spaces for storing/reading DBM transferred data to the physical address spaces. Each packet to be written into DBM is assigned a frame number or frame handler; thereafter, that frame number will be passed by the original owner (a device attached to the data buffer) to different processes for reading out and/or modifying the associated packet or packet data. Frame number assignment is done prior to actual data transfer by request of the data owner. The frame number request is done prior to moving data from the owner's local memory into the DBM's data buffer. Frame number is allocated dynamically by the DBM.

Abstract: The present invention relates to a method of operating a buffered crossbar switch. The proposed method reduces power dissipation in a buffered crossbar switch by reducing the number of crossbar buffer write processes.

Abstract: A system and method of protocol and frame classification in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the packet or frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit, such as the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address and flags indicating whether the frame uses a virtual local area network, preferably using hardware to quickly and in a uniform time period. The stored key characteristics of the packet are then used by the network processing complexes in its further processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame.

Abstract: A digital cross-connect switching system that has a single-stage architecture, a scalable bandwidth, and reduced connection memory storage requirements. The scalable bandwidth digital cross-connect switching system includes a plurality of digital cross-connect building blocks. Each digital cross-connect building block includes at least one cross-connect having a plurality of input ports and a plurality of output ports, at least one connection memory communicatively coupled to the cross-connect, and at least one OR gate. Bandwidth is scaled in the digital cross-connect switching system by interconnecting predetermined numbers of the digital cross-connect building blocks. In general, the size of the digital cross-connect switching system increases as the square of the bandwidth requirement.

Abstract: A group switching apparatus for multi-channel data is disclosed. It includes a speech memory to temporarily store a time slot to be switched, and a connection memory (CM) to store group connection information. Also, it includes a processor matching unit to interface group connection information provided from an upper processor to the CM and a counter to count a system clock signal and output a read address for the CM. Additionally, an offset generating unit receives group connection information outputted from the CM and generates a first offset value according to a signal representing an ‘ON’ state of group connection, and an adder adds the output of the counter and the output of the offset generating unit and outputting the added value as a read address for the SM.

Abstract: The present invention provides a system device, which sets-up IDs for plural devices, On-Line, especially for illuminating equipments connected with standard DMX signals, mainly by logging related data with non-volatile memory elements (NOV-RAM, EEPROM, and FLASH etc.), and separately depositing, On-Line, the operation data needed by the entire system, into designated individual devices with specifically arranged communication protocols and procedures, and enabling said device operating in standard DMX signal system.

Abstract: A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network is provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A provisioning register stores provisioning information describing the communication system and the communication ports. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-1 equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally its intermediate states are restored, processed, and saved when it changes to process a different data stream or a different frame of data of a given service.

Abstract: In general, in one aspect, the disclosure describes an apparatus capable to select a queue. The apparatus includes a queue occupancy device to indicate an occupancy status of the queues, a queue occupancy cache to record an update in occupancy status of a particular queue, a next queue selector to select a queue based on said queue occupancy device and a most recently serviced queue, and a queue identification register to identify a most recently serviced queue.

Abstract: A prime number based pointer allocation technique. A packet-forwarding system incorporating the technique stores cells of a packet in packet memory, according to allocated pointers that have a fixed correspondence to locations in the packet memory. Each packet input interface of an ingress module has a memory parameter counter that is incremented by a different prime number each time a memory pointer is allocated to that input interface. The memory parameter counter includes a memory interface portion and a memory bank portion that correspond to the memory interfaces and memory banks of a packet memory with which the memory pointers are associated.

Abstract: A method for employing an associative memory to implement a switch is disclosed. The method comprises the step of receiving data in a first time slot. The method also comprises the step of examining the associative memory to determine if the data should be stored. Additionally, the method comprises the step of storing the data in a memory location and transmitting the data in a second time slot.

Abstract: Defines and handles segments in messages to place pauses and interruptions within the communication of a message between transmitted segments of the message. A port cache of the destination node of each transmitted message obtains a message control block (MCB) which is used to control the reception of inbound segments within each message sent or received by the node. Each MCB stays in the cache only while its message is being communicated to the port and may be castout between segments in its message when there is no empty cache entry to receive a MCB for a current message being communicated but not having its MCB in the cache.

Abstract: A network switch configured for switching data frames across multiple ports utilizes an efficient arbiter to store the data frames. Each port possesses queuing logic for requesting a free pointer from a free buffer queue. A multi-level arbitration logic arbitrates all the requests of equal priority from the network switch ports in a round robin scheme. The arbitration logic comprises a plurality of cells that cascaded to output an acknowledgement signal in response to an inhibit signal and a request signal as well as a counter that is incremented upon an asserted acknowledgement signal.

Abstract: A channel interface architecture for a time division multiplexed (TDM) data communication system has a plurality of TDM communication ports coupled to serial TDM communication channels. The channel interface architecture interfaces data from any channel of any TDM communication port with any TDM communication channel of any other TDM communication port, on a per time slot/channel basis. The architecture includes a parallel data bus portion, an address bus portion, and a control portion. Each of a plurality of TDM communication channel interface units, associated with the ports, includes a multipage memory that stores data received from an associated serial communication link. The memory also selectively stores data that has been asserted onto the data bus portion of the bus architecture from another interface unit.

Abstract: The invention relates to a switching device for switching input data frames (IDF) from a plurality of N input lines (i1, i2, . . . in, iN) to output data frames (ODF) on a plurality of M output lines (o1, o2, . . . on, oM). The switching device contains a number K of switch pattern units, each containing a specific switch pattern. A number K of frame store memories (FSMj) each store all input data frames from all input lines in every frame period. Each frame store memory is used for selecting bits to a sub-group of M/K output lines. The parallelly working units (u1, u2, . . . uK) each sequentially select a plurality of M/K bits from the stored input data frames and simultaneously assign the selected bits to the output data frames on the respective sub-group of output lines. The selection and assigning of bits in each unit is performed at a M/K times higher clock rate than the bit rate on the input data lines.

Abstract: Flow of data units to an address resolution processor is controlled to inhibit multiple data units from a single multicast flow from being enqueued with the address resolution processor. In a switch having a plurality of Input/Output Application Specific Integrated Circuits (“I/O ASICs”) with a plurality of ports, no more than one data unit from each I/O ASIC is permitted to be enqueued with the address resolution processor at any point in time. A separate learn pending indicator may be defined for each I/O ASIC in the switch.

Abstract: A web interface system (10) for a debit card service in a telecommunications network includes at least one service logic program (28) implementing the debit card service expressed in a web browser readable format, and a web server (30) adapted to store the at least one service logic program (28) and provide access thereto, in the form of at least one web page, by users via a web browser (36). A call scripting process (54) residing in the web server (30) continuously receives user inputs (52) entered on the at least one web page (34) and communicates the user inputs (52) to a predetermined node in the telecommunications network.

Abstract: The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a network identify a new message flow, they determine the proper processing for packets in that message flow and cache that information for that message flow. Thereafter, when routers in a network identify a packet which is part of that message flow, they process that packet according to the proper processing for packets in that message flow. The proper processing may include a determination of a destination port for routing those packets and a determination of whether access control permits routing those packets to their indicated destination.

Abstract: A system and method for assigning departure timeslots to arrival data in an ATM switch is described. The departure timeslots are assigned to arrival data when no departure data is pending or when arrival data has a higher priority than pending departure data.

Abstract: The invention relates to a network interface apparatus called a router or the like which is provided in a network system and relays the transmission of a data packet as a bundle of information. In order to know the permission or inhibition of communication of the data packet at a high speed while suppressing an increase in memory capacity, there is provided a coupling management table in which one VLAN ID is allocated to each terminal (each MAC address) and coupling information showing whether the communication from the terminal having a transmitting side VLAN ID to the terminal having a receiving side VLAN ID is permitted (logic “1”) or inhibited (logic “0”) has been stored at each of the coordinate points using the VLAN ID on the transmitting side and the VLAN ID on the receiving side as coordinates.

Abstract: The address of a latest Serving GPRS Support Node (SGSN) is provided to a Gateway GPRS Support Node (GGSN) by a special Update SGSN Address Request message which is sent from the SGSN to the GGSN. For a subscriber whose subscription permits, the address of the latest SGSN node is sent in the Update SGSN Address Request message for a qualified packet data protocol (PDP) context. A qualified PDP context (1) has a static PDP address; and (2) is not activated. The Update SGSN Address Request message can be sent from the SGSN to the GGSN in either a GPRS Attach scenario or an Inter-SGSN Routing Area Update Scenario. In response to the Update SGSN Address Request message, the GGSN sends an Update SGSN Address Response message which advises whether the updating of the address for the SGSN at the GGSN has been successful.

Abstract: The invention provides method and apparatus for identifying signals for a set of communication devices in a signal stream having signals for a number of different sets of communication devices. Some embodiments of the invention are methods and devices for extracting signals for a first set of communication devices from a signal stream having signals for a number of different sets of communication devices. Other embodiments of the invention are methods and devices for inserting into a signal stream signals from a first set of communication devices. Yet other embodiments of the invention are time division multiplexing and demultiplexing methods and apparatuses that use a content addressable memory to identify sets of signals for a particular set of communication devices. In addition, some embodiment of the invention are used in fiber optic telecommunication networks. These embodiments include an optical network unit that receives an integrated signal stream having signals for different types of applications.

Abstract: Described herein is an ATM cable network having a plurality of ATM subscriber interface units or set-top boxes (STBs) in individual neighborhood homes. A coax distribution plant provides a plurality of communication channels between the STBs and the a neighborhood node. A cable headend serves the neighborhood node and its associated STBs through a fiber-optic trunk providing a plurality of different communication channels or frequencies. The headend includes an ATM node switch having switch ports associated with each of the different communication channels. A resource manager at the headend assigns individual STBs to respective communications channels. STBs share both upstream and downstream communications channels and switch ports. In an extended autoregistration procedure, the ATM node switch is configured to assign exclusive ranges of VPI/VCI values to the individual STBs tuned to the single switch port.

Abstract: An apparatus and method for transferring data among clients of a time division multiplexed network is provided. In one aspect of the preset invention the apparatus includes clock circuits that allow for a variable number of time slots and a variable bus cycle of the network. In another aspect of the present invention a network interface module includes an indirection register that contains relationships between memory storage locations and channels of a time domain multiplexed network. In yet another aspect of the present invention, a network interface module is provided that comprises a memory, and first and second registers. In one mode of operation of the network interface module, data from the memory for a client is pre-fetched from the memory, prior to the start of a bus cycle and is stored in the registers to minimize memory access delays in the system.

Abstract: A channel interface architecture for a time division multiplexed (TDM) data communication system has a plurality of TDM communication ports coupled to serial TDM communication channels. The channel interface architecture interfaces data from any channel of any TDM communication port with any TDM communication channel of any other TDM communication port, on a per time slot/channel basis. The architecture includes a parallel data bus portion, an address bus portion, and a control portion. Each of a plurality of TDM communication channel interface units, associated with the ports, includes a multipage memory that stores data received from an associated serial communication link. The memory also selectively stores data that has been asserted onto the data bus portion of the bus architecture from another interface unit.

Abstract: A repeater communications module (RCM) that enhances signals in a communications network comprises a processor coupled to a communications medium and optionally to a host application. The RCM operates in one of two modes: (1) interface or host application controlled, and (2) standalone. In the interface mode, the RCM receives packets from a host application, modifies the packets and transmits message packets in accordance with a transmit role table (TRT). In standalone mode, the RCM initiates packets and transmits message packets in accordance with the TRT. All RCMs can be configured to repeat message packets which are received from the communications medium in accordance with a repeater role table (RRT).

Abstract: A multiplex extender 26 for permitting discrete I/O devices 34, not individually equipped to decode multiplex channel addresses, to be multiplexed on a time division multiplexed control bus 10. The multiplex extender 26 is connected intermediate the time division multiplexed control bus 10 and a branch line 30 and includes a multiplex channel address decoder 78, a data disconnect switch 82 and a branch line controller 90. The multiplex channel address decoder 78 is selectively programmed to one of the multiplex channel addresses of the time division multiplexed control bus 10. The multiplex channel address decoder 78 produces one or more output signals, each being determined by the multiplex channel address which has most recently been decoded.

Abstract: A device for transferring binary data between a time-division multiplex and a RAM includes circuitry for assigning, for each time slot of the multiplex, a logical channel number. This enables two HDLC controllers, respectively for transmission and reception, to be shared between all the channels of the multiplex.

Abstract: The present invention discloses a cell switching network which includes a cell switch (AS) coupled to a first terminal (T1) and a function unit (FU). The cell switch is also coupled to a second and a third terminal (T2,T3) via a cell switching access network (AAN). The first terminal exchanges information with the second terminal via the function unit (FU) and a predetermined part of the information is indicative of the information exchange between the first and the second terminal. The function unit is adapted to process the information and modifies the above predetermined part of the information so that it becomes indicative of information exchange between the function unit and the third terminal. The information is thereupon exchanged between the first and the third terminal via the function unit.

Abstract: An internet activity analyzer includes a network interface controller, a packet capturing module, a packet analysis module, and a data management module. The network interface controller is connected to a transmission medium for a network segment and is arranged to receive the stream of data packets passing along the medium. The packet stream is filtered to remove undesired packet data and is stored in a raw packet data buffer. The packet data is decoded at the internet protocol layer to provide information such as timing and sequencing data regarding the exchange of packets between nodes and the packet data for exchanges between multiple nodes may be recompiled into concatenated raw transaction data which may be coherently stored in a raw transaction data buffer. An application level protocol translator translates the raw transaction data and stores the data in a translated transaction data buffer.

Abstract: A digital telecommunications switching system includes a main normal rate switch having multiple, bi-directional ports for selectively switching timeslot associated with normal rate channels multiplexed on incoming and outgoing digital links. Each timeslot in the frame includes a predetermined number of bits. The normal rate switch switches timeslots received from any one of the switch ports to any one of the other switch ports at the normal rate. An "add-on" subrate switch is modularly connected to the normal rate switch and selectively switches one or more bits corresponding to one or more subrate channels within a timeslot at a data transmission rate which is less than the normal rate.

Abstract: To reduce memory space of a speech path memory in a switching circuit for a multi-slot time division signal, only data in effective time slots of an input signal are stored one after another in a speech path memory to be switched into different time slot of an output signal in the present invention. Recording relations between time slot number of the input signal where data to be switched are carried and an address of the speech path memory where the data are stored, a conversion table converts switching control data indicating each time slot number of the input signal of data to be switched into each time slots of the output signal to address data of the speech path memory where the data to be switched are stored, and generates an idle bit pattern inserting signal when the data to be switched are not stored.