Abstract: In one embodiment, a method generally includes a first edge (E) node in a network receiving an encapsulated data packet, wherein the encapsulated data packet comprises an outer header and a data packet, wherein the outer header comprises a first router locator (RLOC) corresponding to the first E node, wherein the data packet comprises an internet protocol (IP) header, and wherein the IP header comprises a destination endpoint identification (EID) corresponding to a host H. The first E node determines whether the host H is attached to the first E node. And in response to the first E node determining the host is attached to the first E node, the first E node forwards the data packet to the host H. The first E node receives a message from another node after the host H detaches from the first E node and reattaches to another E node, wherein the message comprises the destination EID.

Abstract: A communication apparatus installed on a vehicle as a master apparatus includes: a slave port communicating with an on-vehicle control apparatus; two or more master ports are paired with two or more slave apparatuses installed on the vehicle, and communicate with the two or more slave apparatuses using different channels based on Distributed System Interface (DSI) protocol; two or more buffer memories provided corresponding to the two or more master ports; and a control section sorting and storing commands addressed to the two or more slave apparatuses, respectively, from the on-vehicle control apparatus into the two or more buffer memories, respectively, and when receiving a trigger instructing transmission of the commands from the on-vehicle control apparatus, reading the commands from the two or more buffer memories, and simultaneously transmitting the commands from the two or more master ports, respectively.

Abstract: A network is configured. Constraints are stored. A plurality of processing stages is processed. For at least one of the plurality of processing stages, an application agent utilizes an input declarative requirement with at least some of the constraints to determine an output declarative requirement that is at a lower level than a level of the input declarative requirement. Each processing stage corresponds to an interaction agent that is able to specify the input declarative requirement for that stage.

Abstract: VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spacially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spacially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane.

Abstract: Disclosed are a switch, a switching system, a switching network chip component, and a forwarding chip component. The switch includes: a switching network chip component packaged as an independent device, a forwarding chip component packaged as an independent device, and a controller. The switching system includes at least one switch and at least two network devices connected to the switch. The switching network chip component includes: a first cartridge housing, a switching network chip, a first heat dissipation component, and a first power supply component arranged inside the first cartridge housing. The forwarding chip component includes: a second cartridge housing, a forwarding chip, a second heat dissipation component, and a second power supply component arranged inside the second cartridge housing.

Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

Abstract: VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spacially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spacially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane.

Abstract: A system and method are provided for updating network protocols. A new ASIC is designed to adapt to future network protocols, the ASIC including at least one packet editing program. The ASIC is configured to classify a received packet to determine new protocols to which the packet is to be updated, delete selected existing headers of the packet, insert new headers in the packet based on the classification, and modify selected headers based on the classification.

Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

Abstract: A multistage relay communication system 100 includes a trunk network 1 and branch networks 2 (2a, 2b), each of which includes one or more communication apparatuses 4. The communication apparatus 4 can switch between a trunk mode to operate in the trunk network 1 and a branch mode to operate in the branch network 2. In the trunk network 1, the communication apparatus 4 carries out fixing of a communication path and redundancy of data based on a path table in order to achieve real-timeness and a data arrival rate. Meanwhile, in the branch network 2, when a communication failure occurs, the communication apparatus 4 autonomously searches for a communication path and constructs a path table, in order to at least secure a data arrival rate even if real-timeness is impaired within an allowable range.

Abstract: In some embodiments, a system includes multiple access switches, a switch fabric having multiple switch fabric portions, and a control plane processor. Each switch fabric portion is coupled to at least one access switch by a cable from a first set of cables. Each switch fabric portion is configured to receive data from the at least one access switch via the cable from the first set of cables. The control plane processor is coupled to each switch fabric portion by a cable from a second set of cables. The control plane processor is configured to send control information to each access switch via a cable from the second set of cables, a switch fabric portion, and a cable from the first set of cables. The control plane processor is configured to determine control plane connections associated with each access switch and is configured to determine data plane connections associated with each access switch as a result of the control plane connections.

Abstract: A plurality of frame buffers of a communication device store input frames for respective flows, which are units of managing communication. A sequential scheduler and an adjustment scheduler cyclically visit the plurality of frame buffers to read a frame for external output from each frame buffer. The sequential scheduler reads one frame per a visit to each frame buffer at a speed lower than a communication speed of the communication device. The adjustment scheduler reads one or more frames per a visit to each frame buffer such that a restriction on read quantity defined by a reference value greater than the shortest frame size is imposed.

Abstract: A printed circuit board (PCB) for an Advanced Telecommunications Computing Architecture (ATCA) shelf. The ATCA shelf may include a backplane providing a payload power supply and a standby power supply. Additionally, the PCB may include a first shelf management controller (ShMC) and a multiport switch, the multiport switch electrically coupling the first ShMC with a second ShMC on a second PCB by way of the backplane, the first ShMC utilizing standby power provided by the backplane at least when payload power is not available.

Abstract: A distributed switch may include a plurality of sub-switches. These sub-switches may be arranged in a hierarchy that increases the available bandwidth for transmitting multicast data frames across the switch fabric. Moreover, the distributed switch may be compatible with link aggregation where multiple physical connections are grouped together to create an aggregated (logical) link. Link aggregation requires similar data frames to use the same data path when traversing the distributed switch. With a unicast data frame, the sub-switch in the distributed switch that receives the data frame typically identifies the destination port (during a process called link selection) and forwards the data frame to the sub-switch containing that port. However, with multicast data frames, instead of the receiving sub-switch performing link selection to determine the destination port, link selection may be done by a different sub-switch or not done at all.

Abstract: A distributed switch may include a plurality of sub-switches. These sub-switches may be arranged in a hierarchy that increases the available bandwidth for transmitting multicast data frames across the switch fabric. Moreover, the distributed switch may be compatible with link aggregation where multiple physical connections are grouped together to create an aggregated (logical) link. Link aggregation requires similar data frames to use the same data path when traversing the distributed switch. With a unicast data frame, the sub-switch in the distributed switch that receives the data frame typically identifies the destination port (during a process called link selection) and forwards the data frame to the sub-switch containing that port. However, with multicast data frames, instead of the receiving sub-switch performing link selection to determine the destination port, link selection may be done by a different sub-switch or not done at all.

Abstract: A mobile communication system according to the present invention includes: a step A in which a mobile station UE transmits an uplink data signal using a shared uplink resource designated by an uplink scheduling grant to a radio base station eNB upon reception of the uplink scheduling grant including CB-RNTI; a step B in which the radio base station eNB transmits a downlink control signal including the CB-RNTI upon successful reception of the uplink data signal transmitted by the mobile station UE; and a step C in which the radio base station eNB transmits MAC-CE including C-RNTI of the mobile station UE using a downlink resource designated by the downlink control signal.

Abstract: A switching device includes multiple interfaces and a switch fabric. The switch fabric includes switch integrated circuits arranged in a number of stages. Multiple virtual switch planes may be implemented in the switch fabric. Data traffic received at the interfaces is selectively assigned to different ones of the virtual switch planes.

Abstract: In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.

Abstract: In some embodiments, a system includes multiple access switches, a switch fabric having multiple switch fabric portions, and a control plane processor. Each switch fabric portion is coupled to at least one access switch by a cable from a first set of cables. Each switch fabric portion is configured to receive data from the at least one access switch via the cable from the first set of cables. The control plane processor is coupled to each switch fabric portion by a cable from a second set of cables. The control plane processor is configured to send control information to each access switch via a cable from the second set of cables, a switch fabric portion, and a cable from the first set of cables. The control plane processor is configured to determine control plane connections associated with each access switch and is configured to determine data plane connections associated with each access switch as a result of the control plane connections.

Abstract: In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric physically distributed across a plurality of chassis. The multi-stage switch fabric has a plurality of ingress ports and a plurality of egress ports. The switch core is configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports. The switch core is also configured to provide non-blocking connectivity at line rate between a first peripheral processing device disposed with a first chassis and a second peripheral processing device disposed within a second chassis.

Abstract: A system for embedding metadata in data packets has logic that is configured to insert metadata into a data packet after the payload data and padding, if any. The logic further adjusts the packet's overhead, such as a frame check sequence, to account for the added length of the packet. The packet remains compliant with applicable protocols, such as Ethernet, and can be successfully communicated in accordance with such protocols while carrying the metadata. In this regard, the insertion of the metadata is transparent to protocol stacks such that the metadata data does not cause an error or the protocol stacks to render the packet invalid. In particular, the protocol stacks view the inserted metadata as part of the packet's pad field, and the inserted metadata should not cause any errors in the operation of the protocol stacks or prevent the protocol stacks from processing the packet.

Abstract: A method for communication, in a network element that includes multiple ports, includes buffering data packets entering the network element via the ports in input buffers that are respectively associated with the ports. Storage of the data packets is shared among the input buffers by evaluating a condition related to the ports, and, when the condition is met, moving at least one data packet from a first input buffer of a first port to a second input buffer of a second port, different from the first port. Respective output ports, via which the buffered data packets are to exit the network element, are selected from among the ports. The buffered data packets are forwarded to the selected output ports.

Abstract: A network device includes a hybrid switch fabric configured for switching packets and circuits that includes a packet switching portion that distributes packets across a plurality of packet ports of fabric chips within the hybrid switch fabric and operates in accordance with packet switching behavior requirements, and a circuit switching portion for switching circuits, wherein the circuit switching portion of the hybrid switch fabric directly connects a single input of the hybrid switch fabric to a single output of the hybrid switch fabric via a pre-determined path through the fabric chips and operates in accordance with circuit switching behavior requirements. The packet switching portion and the circuit switching portion include one or more fabric chips, wherein the fabric chips each include a plurality of ports each dynamically configurable as one of a packet port for receiving and outputting packet-switched data and a circuit port for receiving and outputting circuit-switched data.

Abstract: A router includes multiple routing engines. If the active routing engine fails, a backup one of the routing engines detects the failure and assumes the role of active routing engine. A redundancy controller circuit, connected to the multiple routing engines, facilitates the selection and switching of the routing engines. Portions of the packet forwarding engine, in addition to the routing engine, may be redundantly implemented. The active routing engine controls the selection of the redundant portion of the packet forwarding engine.

Abstract: A one-dimensional circulating switch may be defined by connections between several switch modules and one or more temporal cyclic rotators. Where a switch module that is part of a first one-dimensional circulating switch is also connected one or more temporal cyclic rotators that define a second one-dimensional circulating switch, a two-dimensional circulating switch is formed. A two-dimensional circulating switch is flexible and may scale to capacities ranging from a few gigabits per second to multiple Petabits per second.

Abstract: Source circuits (10) produce messages that may each be processed by any one of a plurality of processing circuits (14). A network of distributor circuits is provided between the source circuits and the processing circuits (14). Local decisions by the distributor circuits in the network decide for each message to which one of the processing circuits the message will be routed. Messages are supplied to at least two parallel distributor circuits. These distributor circuits (12a) select from further distributor circuits (12b) in the network on the basis of current availability of individual ones of the further distributor circuits (12b). The respective messages are in turn forwarded from the selected further distributor circuits (12b) to data processing circuits (14) along routes selected by the selected further distributor circuits (12b) on the basis of current availability of the data processing circuits (14) and/or subsequent distributor circuits (12c) in the network.

Abstract: A network includes at least two core local area network (LAN) fabrics, each including a first core switch cluster deployed at a first sub-core and a second core switch cluster deployed at a second sub-core different from the first sub-core. The network also includes a multi-port link aggregation group to link the first core switch cluster and the second core switch cluster.

Abstract: In a first embodiment of the present invention, a non-blocking switch fabric is provided comprising: a first set of intra-domain switches; a second set of intra-domain switches; a set of inter-domain switches located centrally between the first set of intra-domain switches and the second set of intra-domain switches, wherein each of the ports of each of the inter-domain switches is connected to an intra-domain switch from the first or second set of intra-domain switches.

Abstract: A network, including: a first tile having a processor, a top brick connected to the processor, a first bottom brick, and a first intermediate brick; a second tile having a second intermediate brick and a second bottom brick; multiple connections connecting the top brick with the second intermediate brick and the first intermediate brick with the second bottom brick using a passthrough on an intermediate tile between the first and second tiles, where the first, intermediate, and second tiles are positioned in a row; and a third tile having a plurality of caches connected to a third bottom brick, where the second and third tiles are positioned in a column, and the first bottom brick, second bottom brick, and third bottom brick belong to a bottom layer of the network, and where the first and second intermediate bricks belong to an intermediate layer of the network.

Abstract: A network, including: a first tile having a processor, a first top brick connected to the processor, a first bottom brick, and a first intermediate brick; a second tile having a second intermediate brick and a second bottom brick; multiple connections connecting the first top brick with the second intermediate brick and the first intermediate brick with the second bottom brick using a passthrough on an intermediate tile between the first and second tiles, where the first, the intermediate, and the second tiles are positioned in a row; and a third tile having a plurality of caches connected to a third bottom brick, where the second and third tiles are positioned in a column, and the first bottom brick, the second bottom brick, and the third bottom brick belong to a bottom layer of the network, and where the first and second intermediate bricks belong to an intermediate layer of the network.

Abstract: An overlaid switching network is derived by overlaying perpendicularly one multistage interconnection network with a second multistage interconnection network. The new network is formed by placing a switching element corresponding to the position of switching elements in either multistage interconnection network. Each switching element in the overlaid network has the ports defined by the two multistage interconnection networks as does its interconnection networks. A special case occurs when the number of rows and columns of the first multistage interconnection network is the number of columns and rows of the second multistage interconnection network, respectively. The overlaid switching networks also inherit their upgradeability from the multistage interconnection networks from which they are derived, such as in the case of a redundant blocking compensated cyclic group multistage network.

Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

Abstract: A switching device includes multiple interfaces and a switch fabric. The switch fabric includes switch integrated circuits arranged in a number of stages. Multiple virtual switch planes may be implemented in the switch fabric. Data traffic received at the interfaces is selectively assigned to different ones of the virtual switch planes.

Abstract: A network comprises a plurality of interconnected switches that implement a topology database synchronization technique in which each switch determines whether its topology database has already been transmitted to a neighboring switch when a new link is formed to the neighboring switch. When a new electrical connection is detected, the local switch determines whether any of its other ports have already been connected to the same neighboring switch. If no other port on the local switch has been connected to the neighboring switch, the local switch transmits its topology database to the neighboring switch. If the local switch determines that it has already been connected to the neighboring switch via another one of its ports, the local switch does not yet again copy of the database to the neighboring switch. Also, link state record updates are propagated via only one inter-switch link to a neighboring switch, not all possible links.

Abstract: A network of global coverage, scalable to hundreds of petabits per second, comprises bufferless switch units each of dimension n×n, n>1, arranged in a matrix of ? columns and ? rows, ?>1, interconnecting a maximum of ?×n edge nodes. Each edge node has ? upstream channels to ? switch units in ? different columns and ? downstream channels from ? switch units in ? different rows. All upstream channels to a switch unit are time-locked to the switch unit, thus enabling coherent switching at the switch unit. The switch units are preferably fast-switching optical nodes. Alternatively, the switch units may comprise fast-switching optical nodes each of dimension m×m, arranged in a first ?×? matrix, and latent space switches each of dimension n×n, n>1, arranged in a second ?×? matrix, ?>1, where ?×m=?×n. An edge node time locks to each optical node and each latent space switch to which it connects.

Abstract: Systems and methods according to these exemplary embodiments provide for dynamically scalable switching fabrics. A dynamically scalable switching fabric can include a first set of fabric element (FE) interfaces and a second set of FE interfaces, interconnectable by a reconfigurable crossbar. By selectively populating the FE interfaces, different switching capabilities, e.g., bandwidth per processor blade and/or number of processor blades supported, can be achieved. When the population of the FE interfaces is modified, the reconfigurable crossbar can reconfigure the links between FEs. According to one embodiment, a three-stage CLOS architecture can be implemented. According to another embodiment, a multi-plane architecture can be implemented.

Abstract: A hybrid switch module configured on a common support structure providing networks the ability to automatically reconfigure point-to-point links, per software controls, to optimize network topology by combining a network switching device with a physical layer switch using switching logic. The hybrid switch module is an integrated unit that can operate at a physical layer, routing signals between dedicated ports, and operate as a packet switch for non-dedicated ports.

Abstract: A network, including: a first tile having a processor, a first top brick connected to the processor, a first bottom brick, and a first intermediate brick; a second tile having a second intermediate brick and a second bottom brick; multiple connections connecting the first top brick with the second intermediate brick and the first intermediate brick with the second bottom brick using a passthrough on an intermediate tile between the first and second tiles, where the first, the intermediate, and the second tiles are positioned in a row; and a third tile having a plurality of caches connected to a third bottom brick, where the second and third tiles are positioned in a column, and the first bottom brick, the second bottom brick, and the third bottom brick belong to a bottom layer of the network, and where the first and second intermediate bricks belong to an intermediate layer of the network.

Abstract: Embodiments of a network architecture include a backbone node having a plurality of independent routers or switches connected in a matrix, wherein the matrix includes a plurality of stages of routers or switches, to form a node having a node switching capacity that is greater than the node switching capacity of the individual routers or switches. A method includes assigning one of a plurality of backbone networks to a destination network address, associating a next hop loopback address with the destination network address, and advertising the destination network address in combination with the next hop loopback address through the selected backbone network address.

Abstract: Systems and methods include providing a router that may be deployed as multiple logical routers that share a common fast interconnect. These logical routers may functionally serve as core routers, peering routers, aggregation routers, etc. A further aspect of the system and methods is that the resources assigned to a logical router are allocated from a pool potentially including multitude of hardware cards. A further aspect of the system and methods is that a logical router may be independently managed by the owner of the router or by an owner of the logical router.

Abstract: A one-dimensional circulating switch may be defined by connections between several switch modules and one or more temporal cyclic rotators. Where a switch module that is part of a first one-dimensional circulating switch is also connected one or more temporal cyclic rotators that define a second one-dimensional circulating switch, a two-dimensional circulating switch is formed. A two-dimensional circulating switch is flexible and may scale to capacities ranging from a few gigabits per second to multiple Petabits per second.

Abstract: A multi-plane cell switch fabric system prevents a decrease of the effective switching capacity when switching the variable-length packets. Distribution units classify input variable-length packets for each address, arranges the packets by a first division length unit, divides the packets into fixed-length cell payloads by a second division length unit that is an integer multiple being twice or more as large as the first division length unit, and forms a fixed-length cell by providing destination information, a source ID, a sequential number, and packet head tail information to each of the cell payloads. The cells are distributed to all the switching units one by one whenever the cells are collected to be the same number as the plural switching units. The reordering units classify the cells, reorder the sequential number in an original order, and reassemble the packets by the packet head tail information of the cell.

Abstract: In accordance with an aspect of the present invention, a corresponding list of muxes is maintained for each combination of a peripheral and a mux option. The list is then retrieved to program the required muxes to connect the communication paths from a peripheral on the corresponding mux option, based on which the list is retrieved. In an embodiment, the information is maintained in the form of a table, with each entry storing the data corresponding to a mux and mux option. The entries are linked by appropriate pointers to form the linked list.

Abstract: A switch matrix for selectively connecting at least one of N signal inputs to at least one of M signal outputs, N and M being integers greater than two, includes a cluster of N input switches arranged about each of the M signal outputs resulting in at least M clusters of N input switches, each input switch having a switch input and a switch output, the switch outputs being connected to respective signal outputs, the clusters and the input switches in the clusters being arranged to permit adjacent switch inputs of adjacent clusters to be connected to form input switch nodes; and a steering switch for each of the signal inputs. The steering switch selectably connects a signal input to an input switch node, wherein the combination of the steering switches and the input switches are operable to connect a desired signal input to a desired signal output.

Abstract: A high capacity network comprises a plurality of edge nodes with asymmetrical connections to a plurality of switch planes, each switch plane comprising fully meshed fast-switching optical switch units. Upstream wavelength channels from each source edge node connect to different switch planes in a manner which ensures that upstream wavelength channels from any two edge nodes connect to a common switch unit in at most a predefined number, preferably one, of switch planes. Thus, switch units in different switch planes connect to upstream channels from orthogonal subsets of source edge nodes. In contrast, downstream wavelength channels from a switch unit in each switch plane connect to one set of sink edge nodes. In an alternate arrangement, the upstream and downstream asymmetry may be reversed.

Abstract: A method and apparatus for routing and forwarding between virtual routers is described. A method in a single network element comprises peering a first virtual router to a second virtual router, wherein the first and second virtual routers have separate address spaces and separate routing tables, distributing a set of one or more routes from the first virtual router to the second virtual router, wherein a first of the set of routes identifies the first virtual as a next hop of the first route, said first route including a destination, and downloading to a set of one or more forwarding tables, the destination and the next hop.

Abstract: A switching device includes an input stage switch group 1-1 including a plurality of input lines, an output stage switch group 1-3 including a plurality of output lines, an intermediate stage switch group 1-2 arranged between the input stage switch group and the output stage switch group, and a scheduler 1-22 deciding a signal path of each of intermediate stage switches 1-21 in the intermediate stage switch group based on information input to the respective input lines. The intermediate stage switch group is divided into a plurality of groups, a plurality of the schedulers is arranged in a distributed fashion to correspond to the plurality of groups, respectively and the schedulers operate independently of one another.

Abstract: A linearly expandable router is comprised of first, second, third and fourth router components. First, second and third discrete links couple an input side of a routing engine of the first router component (102) to an input side of a routing engine of the second, third and fourth router components. Similarly, fourth and fifth discrete links couple the input side of the routing engine for the second router component to the input side of the routing engine of the third and fourth router components, respectively. Finally, a sixth discrete link couples the input side of the routing engine for the third router component to the input side of the router engine for the fourth router component.

Abstract: A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.

Abstract: A system, device, and method for managing communication services in an optical communication system utilizes a optical service agent (OSA) that operates within the domain of the network user and manages various communication services on behalf of the network user. The OSA interacts with the optical communication network to obtain various communication services and manages those communication services for the network user based upon predetermined parameters defined by the network user. An authenticated auto-discovery mechanism is used to automatically identify and authenticate OSA-enabled users and to distribute information between peer OSA-enabled users. A peer-to-peer signaling mechanism is used to extend OSA functionality to OSA-enabled users that do not interface directly with the optical communication network.