Abstract: A self-routing data switching system is disclosed. The data switching system includes a plurality of repetitive switching matrix planes, each of which is electrically connected between a less number of input terminals and a larger number of output terminals, thereby reducing the head-of-line blocking effect. Each switching matrix plane includes a switching element array interconnected between the input ports and the output ports for determining whether the data packet from an input port can be transmitted to a designated output port. The data switching system further includes a plurality of pre-processors to manage the input timing of data packets into the switching matrix array in order to avoid output conflict.

Abstract: Disclosed a method of increasing the whole switch capacity by utilizing the presently used switch network as it is. The present invention, the method of increasing a switch capacity in a switch network system in which three or more switch stages including a plurality of switching elements are connected in serial by using a predetermined logical circuit, the method comprising the steps of: adding switch stage including a plurality of switching elements to correspond to the each switch stage; grouping switching elements of a first switch stage and last switch stage in the switch stage and the added switch stage by a predetermined unit, respectively; and connecting the grouped switching elements of the first stage with corresponding switching elements of an intermediate switch stage which is placed between the first stage and last stage, respectively, and connecting the grouped switching elements of the last switch stage with the corresponding switching elements of the intermediate switch stage, respectively.

Abstract: A network node (10) for switching digital information of different protocol types is described. A plurality of modules (12-x, 13-x, 14-x) are provided which are arranged in an input stage (12), a central stage (13) and an output stage (14). Each module (12-x) of the input stage (12) is connected to each module (13-x) of the central stage (13) and each module (13-x) of the central stage (13) is connected to each module (14-x) of the output stage (14). A standard interface (15) for all protocol types is in each case provided between the input stage (12) and the central stage (13) and between the central stage (13) and the output stage (14). Each of the modules (13-x) of the central stage (13) is designed for one protocol type. The interfaces (15) comprise means for forwarding information as a function of the protocol type to a module (13-x) of the central stage (13) adapted thereto.

Abstract: A chassis for holding modules including a set of first modules oriented horizontally in the chassis and a set of second modules oriented vertically in the chassis. A midplane is oriented orthogonally to the sets of first and second modules. The midplane has connector pins extending from its first side through its second side. Each of the first modules has a first connector for mating with the connector pins extending from the first side, and each of the second modules has a second connector for mating with the connector pins extending from the second side.

Abstract: In another embodiment, an ASIC device includes a first RAM that stores a code for each of multiple first time slots. Each code is combined with corresponding data from a first bus to specify a previously stored operation. A second RAM receives the combined data and code for each first time slot and applies the specified operation for each first time slot to generate modified data for each first time slot. A third RAM stores information specifying a second time slot to correspond to each first time slot and communicates the information for each second time slot as an address. A fourth RAM stores the modified data for a previous frame and the modified data for a current frame, locates the modified data for each first time slot of the previous frame according to the address, and communicates the modified data for each time slot of the previous frame to a second bus in the corresponding second time slot while the modified data for the current frame is being stored.

Abstract: In a matrix switch method, pieces of timing information synchronous with the signal speeds of input data parallelly input to N (N is a positive integer) input terminals are extracted. The respective input data are switched/output to N output terminals through a switch. Output signals from the output terminals of the switch are regenerated by using the pieces of timing information extracted from the corresponding input data. A matrix switch device is also disclosed.

Abstract: A multi-packet-switch system having a standard primary switch interconnect to handle inter-switch packet traffic, separate buffer areas for each primary interconnect and the device ports, the ability to identify specific packet streams by an identifier in each packet, and the ability to specifically manage static routing of packets based on the packet stream identifier. Creating secondary switch interconnects between device ports, and routing identified packet streams to these secondary switch interconnects. The secondary switch interconnects can be dedicated to identified packet streams, thus eliminating primary interconnect buffer contention with other packet streams.

Abstract: In a stack of multi-port network communication units each unit has a forwarding database, the units are connected by way of a cascade, and at least some of the units are connected to links constituting a trunk. When a unicast data packet is received at a first of said units and the unicast data packet has a destination address which is not the subject of an entry in the forwarding database of the first unit, the unicast data packet is sent by way of the cascade to the other units in the stack, accompanied by a flag. When a second unit has in its forwarding database an entry, associating the destination address with forwarding data, it sends a management packet indicating said destination address and the identity of said second unit, so that the database of the first unit can be immediately updated.

Abstract: An apparatus is described comprising an ingress port and a plurality of switch planes where each of the switch planes has a dedicated scheduler and each of the switch planes are communicatively coupled to the ingress port. The switch planes may further have at least one input control port and at least one output control port where each of the input control ports are coupled to each of the output control ports in a crossbar arrangement. The communicative coupling may further comprise one of the input control ports coupled to the ingress port. Furthermore, the ingress port may have at least one unicast queue which is dedicated to a specific egress port. The ingress port may also have a multicast queue.

Abstract: Generally speaking, the cell switching architecture of the present invention offers a powerful, simple, and in many ways elegant solution to the problem of providing cost-effective, high-bandwidth, fault-tolerant cell switching. The architecture is based on a network of switching elements connected in a hypercube topology to form a switch fabric. The generalized hypercube is D dimensional, where D≧3 when all radices in the radix set are 2 and D≧2 when at least one of the radices is greater than 2. A fully-populated switch is fully symmetric: each switching element has the same number and kind of connections to both its neighbors and to the outside world as every other switching element. In an exemplary embodiment, each switching element is connected to one data source and one data sink, e.g., a Utopia bus or other broadband connection. In the same exemplary embodiment, links between switching elements are bidirectional and synchronous, operating in accordance with a Cell Exchange Cycle (CEC).

Abstract: A unique trace word is assigned to each incoming signal routed by a sliced switch fabric having two or more parallel switches. The unique trace word is encoded into each incoming signal following an overall format that ensures that each sliced trace word (i.e., the subset of bits in the overall format routed by each parallel switch) also uniquely identifies each incoming signal. In this way, the present invention ensures that the switch configuration of each and every parallel switch can always be verified. As such, any improper switch configuration can be detected, including those misconfigurations in which all but one of the parallel switches are correctly configured as well as those misconfigurations in which all of the parallel switches are identically, but incorrectly configured.

Abstract: Enhanced performance is realized in a multi-fabric/multi switch group interconnect network by providing asymmetric fabric topologies wherein at least one link between a user-port and a switch-port (or between a pair of switch ports) is different in the fabrics. Asymmetry in fabric topology can increase lower-distance (distance-1) pairs, increase network bisection capacity, or reduce the number of switches employed. End nodes can choose at the time of connection the fabric which offers a shorter connection or fewer router hops. Alternatively, a connection can be set up to use either fabric with the end node dynamically exercising its preference for the fabric that offers the shorter path at the time of data transfer. While the number of router hops does not significantly alter message latency in wormhole-routed networks, it does lower link occupancy and thereby average link contention.

Abstract: In one embodiment, in a switching system, an ASIC device on a card coupled to a backplane communicates switched data to an outgoing network interface for the card without using the backplane, and remaining ASIC devices on the card communicate switched data, to other cards using the backplane for communication to outgoing network interfaces for the other cards. In another embodiment, an ASIC device includes a RAM storing a code for each first slot to combine with corresponding data from a first bus to specify an operation, a RAM applying the operation to generate modified data for each first slot, a RAM communicating as an address information specifying a second slot to correspond to each first slot, and a RAM locating the modified data for each first slot of a previous frame according to the address and communicating this modified data to a second bus in the corresponding second slot while the modified data for a current frame is being stored.

Abstract: A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the plurality of banks and the first and second buses, and a processor core connected to the first and second buses and the single port memory. The bus switch circuit may be controlled statically, independent of activities on the buses, or may be controlled dynamically according to the activities.

Abstract: An ATM switch includes a plurality of stages in which each stage has basic switches and the stages are interconnected. The ATM switch includes M×N basic switches per each stage and a part for interconnecting between the stages. The M×N basic switches are divided into N groups. The part connects an output port of each basic switch at a front stage to M input ports of the basic switches at a back stage. At the output port, a wavelength-multiplexing part is used, and, at the input port, a wavelength-demultiplexing part is used. Further, a wavelength-switching part for switching optical signals of M wavelength-multiplexed optical signals arriving from the M wavelength-multiplexing part and outputting the switched wavelength-multiplexed optical signals to the M wavelength-demultiplexing part is used.

Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.

Abstract: A telephony service system employing a cable network and a telephony service method. The system includes a directory unit, a plurality of network segment units each including a headend unit, and a plurality of routers respectively formed in each network segment unit. The directory unit stores the IP address corresponding to a telephone number of a first cable phone. The plurality of network segment units each having a headend unit read IP addresses stored in the directory unit based on a received telephone number of a second cable phone, and determine a connection audio session using an Internet protocol from the read IP address to set a call path with the first cable phone. The plurality of routers set a call path between the network segment units. According to the cable network of a packet type, unlike a PSTN network of a switch network, the local call charge is reduced.

Abstract: A fault tolerant processing system includes at least two processing planes. Each processing plane processes an input signal and generates an output signal. The system further includes plane termination logic for receiving the output signals of the processing planes to generate a non-redundant output signal. Each processing plane is provided with devices for detecting a fault in the plane, and devices for substituting, in response to detection of a fault in the plane, a signal component, referred to as control component, representing a predetermined logical state for each one of those components of the processed input signal that are affected by the detected fault. Furthermore, the plane termination logic includes devices for performing logical operations on the output signals of the planes such that, in the generation of the non-redundant output signal, unaffected signal components of a received signal override corresponding control components of another received signal.

Abstract: LAN interface logic (33) receives frames from a LAN segment (32), and frame transport logic (40, 54, 56) transfers frames to and from an ATM network. Forwarding logic (36) is used to (i) determine whether a mapping between a destination address (DA) and a virtual connection (VC) in the ATM network exists, (ii) forward frames containing a known DA to the frame transport logic for transfer to the ATM network, (iii) forward frames containing unknown DAs to the frame transport logic for transfer to a broadcast and unknown server (BUS 74) in the ATM network, and (iv) pass unknown DAs to a LAN emulation client (LEC) processor (42, FIG. 5) to resolve the address. The LEC processor creates a LAN emulation address resolution protocol (LE_ARP) request message containing the unknown DA, and the LE_ARP request message is transferred to a LAN emulation server (LES 76). The LES returns an ATM address of a remote LEC via which the destination node can be reached.

Abstract: Several rotator switch architectures are provided that enhance performance of a basic rotator switch. The rotator switches having double buffered tandem nodes, multiplexing two or more sources onto each tandem node, partitioning the rotator into two or more parallel space switches, two or more rotator planes multiplexing from/to source and destination nodes to provide data path redundancy, priority queueing on source nodes scheduled locally or globally, or redundancy in the schedulers are shown.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: In a switch having two parallel planes (A, B) for providing redundancy, cells are received from the two planes in redundancy terminating unit comprising that first the cells are separated whether they are ordinary switched cells, called unicast cells, or cells which are switched or copied to a plurality of the outputs of the planes, these cells being called multicast cells. At each cell time a selection of one received cell is made by a selector control unit (3) and this selection is made substantially at random, among possible received unicast cells and a multicast cell as stored in a FIFO (35) having an output register (37). If received cells have different priorities the random selection is made among cells having the maximum priority of the priority of the received cells. A unicast cell which is not selected, is discarded but a non-selected multicast cell remains in the register until it is selected.

Abstract: Disclosed is a multi-stage (NXN) interconnection network which has N input ports and N output ports, for transmitting packets from the input ports to the output ports. The network comprises a multi-stage packet switching network having at least logMN switching stages; and each of the switching stages having N/2 MXM switching elements, where M is the number of input or output ports of each switching element. Each switching element at each stage comprises X bypassing input ports, M−X input routing ports, X bypassing output ports and M−X output routing ports, where X is 1 or integer of more than 1. The bypassing output ports of each switching element at each stage are connected to bypassing input ports of each of switching elements which are disposed in a same position of a next stage, respectively, and the output routing ports of each switching element at each stage are connected to input routing ports of each of the switching elements at the next stage by means of perfect shuffle connection.

Abstract: An interconnection network in which a control plane and data planes are separate and the bandwidth is extendable, and a method for transferring data includes a control plane including control routers connected to the processors, for exchanging control information and generating information on setting a path for a message transmitted between the processors, and a control line for connecting the control routers together in a predetermined topology, and one or more data planes each including data routers each connected to the processors, for transmitting and receiving messages using the path information on messages generated by the control router, and a data transfer line for connecting the data routers together in the same topology as that of the control plane.

Abstract: Dense physical and electrical connection of (i) flat flexible multiconductor cables of the printed circuit or ribbon types, to (ii) to spaced-parallel planar modules, particularly to switching modules containing switching chips, is realized by (1) a particular connection geometry in combination with (2) a spring clip connector. Flat flexible multiconductor cables routed through free space either in (i) “X” and, optionally also, “Z” planes, or else in (ii) “Y” planes exclusively, have their conductors' ends stripped and bent 90° so as to lie upon conductive pads, arrayed along lines angled 45° to both the “X” and “Y” planes, located on the substrates of switching modules that are within “Z” planes.

Abstract: A cross-connecting optical translator array that electronically switches opto-electronically converted signals received from optical transmission systems and that uses an optical transmitter to generate optical signals having the required wavelength for succeeding optical transmission systems. The cross-connecting optical translator array includes optical converters that are coupled to an input side of an electronic space switch fabric. Optical transmitters are coupled to an output side of the electronic space switch fabric. The optical transmitters are selectable to provide optical interface capability with the various wavelength optical fibers used in optical transmission systems. The combination of the optical converters and the optical transmitters operationally provide an optical translator that receive optical signals at a first wavelength and can transmit optical signals at a second wavelength. The operating speed of the array is compatible with that of the optical transmission systems.

Abstract: A multistage switch has an M.times.N switch size selectively connecting M incoming lines and N outgoing lines and consists of S stages of discrete switches each having a switch unit, wherein the discrete switches are permanently cross-connected in accordance with a prescribed rule. Stored connection information regarding the overall multistage switch and the states of connection of the switch units of the discrete switches are retrieved. Then, utilizing the fact that an output terminal of a switch in a cth (where c.ltoreq.S-1) stage of the multistage switch is to be logically connected to an input terminal of a switch in a (c+1)th stage, connection information relating to the overall switch is generated from the results of retrieval. The generated connection information relating to the overall multistage switch is compared with connection information that has been stored in memory in advance, whereby a connection path that has been set for each discrete switch is prevented from being severed accidentally.

Abstract: A plurality of input signals are switched in an apparatus including redundant switching planes and hardware for receiving an output signal from each of the redundant switching planes. Each switching plane is for switching the plurality of input signals, and each switching plane includes at least two switching modules, each switching module being connected to receive a subset of the input signals directly from an input signal source coupled to the apparatus. Each switching module is further connected to receive a remaining subset of the input signals from remaining switching modules on the same switching plane; and each switching module generates an output signal having components selected from the plurality of input signals. To improve performance in the event of a double fault, each switching module detects whether any of the remaining switching modules on the same switching plane are faulty.

Abstract: A switching network having a plurality of independent switching units with each switching unit switching one bit of each group of data from external data links through a telecommunication switching system. The plurality of switching units is greater than the number of bits that must be switched which increases reliability. This allows the extra switching units to be utilized as replacement switching units should a switching unit actively switching a bit of the incoming data be disabled. The switching units provide full broadcast switching of data from any individual external link to any number of the other external links. A plurality of port units terminate the external links, and a plurality of control paths are provide from a central controller to each of the port units. Each of the switching units communicated one of the control paths. For control, each port unit determines a set of control information that is identical from a majority of the control paths.

Abstract: A fault tolerant multicast ATM switch fabric is constructed as a multistage interconnection network through which cells move from input to output along a pre-established data path. The control phase proceeds concurrently with the data phase by which cells move continuously without idle clock cycles in between. The control logic resolves the state of the switching elements and sends this state information to the data path logic ahead of the cell transfer. The switch consists of three IC designs: control, data path, and switch port controller ICs. The successful realization of the switch relies critically on the design of the control IC which incorporates a new combinatorial hardware design running a dedicated algorithm. A switch port controller delegates, based on local decisions, the replication and routing of multicast cells to a selected group of switch port controllers on a per call basis, thereby supporting any multicast group in a unified manner.

Abstract: In a check system for checking information indicative of connections in a multistage switching network comprising S stages of switching groups and a main control section for controlling the switching groups, the multistage switching network has a switching size of M by N (M.times.N) that is defined by M input lines and N output lines. Each of the switching groups comprises a plurality of switching sections each of which has a plurality of input terminals, a plurality of output terminals, a switching unit for use in connecting these terminals with each other, and a switch control unit for controlling the switching unit. The main control section comprises a memory unit which stores information indicative of connections between the individual switching sections. The main control section has a function of checking whether an output terminal having a specific number of a switching group in a C-th stage (C.ltoreq.

Abstract: A small broadband cross-connect system (10) includes a two-stage matrix (12) for processing and cross-connecting optical and electrical telecommunication network signals. An administration subsystem (14) provides centralized control and synchronization to the two-stage matrix (12). The two-stage matrix (12) may be expanded from 96 ports to 192 ports in a cost and space effective manner.

Abstract: A system (10) for transmitting data is presented. The system (10) includes a data transmission medium (12, 28) and an overhead generator (40) connected to the data transmission medium (12, 28), such as through a switch. The overhead generator (40) digitally encodes control data into one or more bytes in a data transmission frame (70) used to transmit data over the system (10). The system also includes a monitor/selector (22) coupled to the data transmission medium (12, 28). The monitor/selector (22) reads the digitally encoded control data in the byte in the data transmission frame (70). A processor (24) coupled to the monitor/selector (22) processes the digitally encoded control data in the data transmission frame (70).

Abstract: An apparatus and method for selecting improved routing paths in an emulated LAN over an ATM network is disclosed. Such an apparatus and method are realized by having an editor associated with a distributed LAN emulation server selectively modify Routing Information Protocol (RIP) update messages according to information retrieved from an associated routing table. More particularly, the editor modifies RIP update messages so that they will more accurately reflect the position of the network router that broadcast the RIP update message, relative to the position of a network router associated with the distributed LAN emulation server, with respect to any given destination network.

Abstract: A small broadband cross-connect system (10) includes a two-stage matrix (12) for processing and cross-connecting optical and electrical telecommunication network signals. An administration subsystem (14) provides centralized control and synchronization to the two-stage matrix (12). The two-stage matrix (12) may be expanded from 96 ports to 192 ports in a cost and space effective manner.