Abstract: A packet-based telecommunication system (100) is disclosed, comprising a first media gateway (124) having a first CODEC structure (130), a second media gateway (126) having a dual function CODEC structure (132), wherein the dual function CODEC structure is adapted to provide tandem free operation between itself and the first CODEC structure, and wherein the dual function CODEC comprises a first element (134) adapted to negotiate tandem free operation, and a second element (136) communicatively coupled to the first element and adapted to selectively convert data coding responsive to the first element.

Abstract: An apparatus and method for distributing data transmission from a plurality of data input queues in a memory buffer to an output. The method includes associating a priority indicator with each data input queue, determining a priority indicator having a highest priority level among the plurality of priority indicators and selecting the data input queue associated with the priority indicator having the highest priority level to transmit to the output.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: A method for proposing at least one transmission rate change including calculating a plurality of latency values, computing at least one derivative-based proposed change from the plurality of latency values, and proposing a rate change selected from the at least one derivative-based proposed change. Also provided is a system including a rate controller controlling the transmission rate of data between two stations over a network and a rate reporter in communication with the rate controller.

Abstract: A cell multiplexing apparatus comprising call monitors and multiplexers. The call monitors monitor a plurality of channels for their call setting status and select at least two channels for which the same cell may be assembled, i.e., for which the destination of the calls is the same. The multiplexers receive audio information or information already assembled in asynchronous transfer mode (ATM) cells from the channels selected by the call monitors, and disassemble and multiplex the received information for assembly into the payload of a new ATM cell.

Abstract: A method for controlling a bus in a digital interface is disclosed. In the present method, after a self identifying process when a bus reset occurs, a determination is made whether a node which needs to transmit isochronous data is a new node which needs to newly transmit isochronous data or a previously connected node which had been transmitting isochronous data before the bus reset. Thereafter, priority is given to previously connected nodes in allocating channels and bandwidth to previously connected node(s).

Abstract: A novel data transfer scheme for efficiently transferring data between multiple data generating processing units in a processing element wherein each processing unit may generate data at different rates. The data output of each processing unit is multiplexed into a single data stream and written to a memory buffer. A centralized software processor such as a CPU or DSP implements a demultiplexer operative to read the contents of the input buffer, demultiplex the data and distribute it to individual unit buffers thus recreating the original data streams generating by each of the processing units. The multiplexed data stream is generated by partitioning the outputs of the data generating processing units into multiple multiplexer groups based on individual data rates. The outputs of the various groups are collected by a multiplexer and used to build a single data stream having a well-defined structure.

Abstract: A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port interface, wherein the second data port interface supports a plurality of data ports for transmitting and receiving data at a second data rate, along with a third data port interface for transmitting and receiving data at a third data rate. A CPU interface is provided and configured to communicate with a CPU. The switch includes a first internal memory communicating with the first data port interface, the second data port interface, and the third data port interface. A first memory management unit having an external memory interface for communicating data from at least one of the first data port interfaces and the second data port interface to and from an external memory is also provided.

Abstract: A method of and apparatus for identifying a signal transmitting source detects a switching of a signal on the reception side thereby to prevent a transmission error from occurring when a signal is switched. The apparatus for identifying a signal transmitting source comprises a transmitting source identifying code extracting circuit for extracting a transmitting source identifying code provided in a SDDI format header of a received signal, a preceding transmitting source identifying code holding circuit for detecting a change of the transmitting source identifying code, and a transmitting source identifying code comparing circuit for detecting a switching of a transmitted signal based on the transmitting source identifying code thus changed, thereby detecting a switching of the transmitting source.

Abstract: A network switch includes a plurality of receive ports for receiving addressed data packets and a plurality of transmit ports for forwarding the addressed data packets and is responsive to data in the packets for directing received packets to the transmit ports. The switch includes, with respect to at least one transmit port, a bandwidth controller for at least one selected packet type. The bandwidth controller diminishes an aggregate count in response to the sizes of packets of the one type destined for the transmit port and continually augments the aggregate count at a selectable rate. The switch compares the aggregate count with a threshold and initiates a discard of packets of the one type before they can be forwarded from the transmit port so as to limit the proportion of available bandwidth occupied by packet so of the one type with respect to the transmit port.

Abstract: A message division communication method and system are disclosed for a communication system comprising a host, an intermediate device connected to the host through a high-speed bus and a remote device connected to the intermediate device or the host through a low-speed bus. A message is transmitted in such a manner that the host designates and notifies the remote device of a maximum message length determined in a way corresponding to the transmission rate of the low-speed bus and divides the message into division messages each not exceeding the maximum message length thereby to transmit and receive the division messages between the host and the remote device. Even with a communication system in which low-speed and high-speed buses coexist, a message can be transmitted and received by a common communication control scheme.

Abstract: A reference timing architecture is disclosed that provides a level of flexibility that was not available with the architecture in the prior art. In particular, the present invention provides for multiple reference timing outputs that can be routed to equipment nodes relying on the timing information, wherein each of the timing processing paths that provide timing outputs can be controlled independently of one another.

Abstract: Method and apparatus are disclosed for an optoelectronic network interface device allowing reconfiguration of ports in a Local Area Network (LAN). More particularly, the optoelectronic interface device is integrated to include optical ports for communicating with a network, electronic circuits for providing an interface to end-users and a controllable electronic switch between the optical ports and electronic circuits. In response to a control signal, the switch dynamically reconfigures the connection between selected optical ports and selected electronic circuits.

Abstract: The method for controlling congestion from a terminal in a frame relay network, according to the present invention, comprises the steps of: detecting congestion in the network by receiving a congestion notification frame with a BECN bit=1; reducing a transmission window size based on the ratio of the congestion notification frames with the BECN bits=1 to received frames; enlarging the transmission window size, when the congestion subsides and frames with the BECN=0 in the received frames increase; and stopping the enlargement of the transmission window size when the transmission window size attains the maximum transmission window size.

Abstract: The invention provides a system and method of a selecting an egress connection from egress connections at a node for a call being established in a network along a path being associated with the node. Each connection has sufficient bandwidth to carry the call and terminates at a same destination point in said path. The system and method comprise utilizing at least a bandwidth load balance value for each connection in a set of the connections to select the egress connection from the set. An administrative factor score may be used to further define members of the set.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: A memory for searching information through prefix analysis, in particular for building routing tables for nodes of high speed communication networks, such as Internet network, has a memory element which stores a set of information items each associated with a mask information indicative of the number of significant characters in the respective prefix and with a target information. For the implementation of a search criterion based on the longest prefix match, each cell comprises an information field that provides either an address of a next row for the continuation of a search or an information relating to a target reached, and a pair of flags (GO, TARGET) specifying the contents of the information field.

Abstract: A receiving method for absorbing cell-fluctuation with a minimum data delay in low-speed transmission in an ATM switching network. In a cell fluctuation absorption receiving method of a CLAD device equipped in an ATM switching network, the CLAD device for assembling or disassembling cells from or to a bit string having a fixed communication speed of data communication from the connected communication device includes a CLAD unit having a receiving buffer corresponding to the communication speed of each of the addresses, and before storing the first received cell data, storing dummy data in a receiving buffer, the dummy data corresponding to the fluctuation guarantee time.

Abstract: The invention relates generally to data communication networks and more particularly to a method of bandwidth management in a multiservice connection-oriented network which uses one or more overlooking factors and one or more overbooking models. The method allows an edge node which has received a connection request to accurately determine the bandwidth available on a given link in the network, by ensuring that different overlooking models and different overbooking factors are normalized at the edge node.

Abstract: An ATM switching system including a switch unit having a plurality of input ports and output ports, and a multiplexer for multiplexing cell trains from at least two output ports into a single cell train and outputting the cell train to and output port. A demultiplexer can be provided in place of the multiplexer. The switch unit includes a buffer memory for storing cells from the input ports while forming a queue chain for each output port, a demultiplexer for distributing the cells from the buffer memory to output ports, and a buffer memory control circuit for controlling write and read operations of the buffer memory. The buffer memory control circuit has a control table for outputting an identifier of an output port the cells read from the buffer memory are to be output. Cells are read from the chain designated by the identifier.

Abstract: In a connection oriented communications network such as an asynchronous transfer mode (ATM) network, virtual circuit (VC) connections are aggregated onto virtual path (VP) connections to simplify traffic management through core switching elements. This invention provides a system and a method of introducing network level fairness between VP connections in the core. Resource management (RM) cells are used to import relevant traffic weighting parameters from the VC/VP aggregation point to the VP switching element. The weighting parameters are used by a queuing scheme at each switching function to introduce a fairness level component to each VP.

Abstract: A synchronization device for a synchronous digital message transmission system producing a synchronous output signal including successive transport modules synchronized to a frame clock from a digital input signal. The synchronization device includes a receiver unit for receiving the input signal, a packet assembly device for packaging the input signal into subassemblies of the transport modules, a buffer memory, a writer for writing data bits of the input signal out of the subassemblies into the buffer memory with a write clock, a reader, for reading data bits out of the buffer memory with a read clock in order to form the output signal, and a sending unit (SO) for sending synchronous output signals. The effective bit rate of the subassemblies compared to the standardized value is either lowered or raised by selecting the write clock lower than the read clock.

Abstract: A method capable of optical packet switching even in a case where physical optical data in an optical packet switch has not the shape of a packet but the shape of continuous data, and a system therefore are provided. The optical switching method includes the steps of (a) detecting input terminals into which an optical packet is input, of an optical switch and switching the optical packet to destination output terminals of the optical packet, and (b) when there are the input terminals into which the optical packet is not inputted in step (a), detecting other input terminals into which the optical packet, which direct an output terminal among the plurality of output terminals connected to the input terminals, is inputted, and searching a blank output terminal and switching dummy data from the input terminal to the blank output terminal.

Abstract: Digitally compressed video/audio bit streams, when transmitted over digital communication channels such as digital subscriber loop (DSL) access networks, ATM networks, satellite, or wireless digital transmission facilities, can be corrupted due to lack of sufficient channel bandwidth. This invention describes schemes to ensure lossless transmission of bit streams containing pre-compressed video signals within the communication channels. The schemes herein comprises a rate conversion system that converts the bit rate of a pre-compressed video bit stream from one bit rate to another, and that is integrated with a digital communication channel, and a means to convey the maximum channel transmission rate to the rate conversion system to allow satisfactory transmission of the bit stream from the input of the rate converter through the transmission facility.

Abstract: A multi-port packet processor on an integrated circuit provides an efficient means to interface multiple high-speed packet-based communications channels. The multi-port packet processor includes multiple port processors. Each port processor can include a channel interface for coupling to a respective communications channel, a channel processor for processing the data packets received through the channel interface, and an interprocessor communications interface for providing communication between the port processors. The channel interface can be designed to process data packets using a particular set of packet-based protocols. Alternatively, the channel interface can be designed having programmable controls to allow processing of data packets using a selected set, from a number of possible sets, of packet-based protocols.

Abstract: A method for communicating information in a communication network having a first high speed device, a second high speed device, and a low speed device includes transferring data between the first high speed device and the second high speed device at a first rate and transferring data between the first high speed device and the low speed device at a second rate different from the first rate. Transferring data between the first high speed device and the low speed device at a second rate different from the first rate includes receiving at the first rate, at a buffer system, data from the first high speed device and transmitting at the second rate, to the low speed device, data from the buffer system. Transferring data between the first high speed device and the low speed device at a second rate different from the first rate also includes receiving at the second rate, at the buffer system, data from the low speed device and transmitting at the first rate, to the high speed device, data from the buffer system.

Abstract: Deterministic type packet-switching transmission networks are networks in which the different flows of information follow virtual paths defined in advance for which any change requires a reprogramming of the interconnection nodes. The advantage of determinism is that it makes it easier to estimate the maximum delay time that the packets may undergo during their journey in the network. However, it remains to be verified that the network is appropriately sized for the transmission of the different information flows, with the constraints of maximum delay times and of regularity imposed by the connected items of equipment. A method is proposed here for the sizing of the network. In this method, the verification of compliance with these constraints is based on the determining of the jitter components added by the different interconnection nodes of the network, at their different output ports.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: For data packet communication between a plurality of nodes via a communication network, a data communication interface device is used in at least one of a transmitting end and a receiving node. The interface device includes a plurality of interface chips each including a storage section of a predetermined capacity for buffering a data packet to be transmitted or having been received via the communication network, and a control section for controlling each of the interface chips to thereby control transmission or reception of the data packet to or from the communication network. The number of the interface chips to be connected to the control section is optionally selectable in such a manner that an overall buffer storage size in the interface device can be freely adjusted by just increasing or decreasing the number of the interface chips.

Abstract: A network adapter capable of adapting its transmission speed to that of another adapter of the same or slower speed so as to mix adapters of different speeds in the same communication network. In send mode, the adapter selects one of a plurality of transmission speeds based on the message header including a field specifying the message speed, which speed is known to be supported by the adapter at the addressed receive node. The sending adapter prefixes the message with a synchronization byte which defines transmission speed selected and transmits the message at the selected speed. In receive mode, the adapter decodes within one clock cycle the message speed from the message synchronization byte, and responsive thereto generates the clock for gating the receive message into adapter memory.

Abstract: A network comprises routers, wherein at least some of the routers are configured to receive a number of datastreams and to output an aggregated datastream. Subject to the precondition that a limiting bit rate ri and a number of burst bits bi can be quoted for each datastream i supplied to a router from outside the network, such that the number Aiin(t1, t2) of data bits which are received at an input of the routers, between a time t1 and a later time t2, satisfies the relationship Aiin(t1, t2)≦ri*(t2−t1)+bi, each router j controls the output of data packets in the aggregated datastream ia(j) such that, for a limiting bit rate Ria(j)ag and for a predeterminable burst bit number Bia(j), the number Aia(j)out(t1, t2) of data bits output in the aggregated datastream ia(j) satisfies the relationship Aia(j)out(t1, t2)≦Ria(j)ag*(t2−t1)+Bia(j), wherein Ria(j)ag and Bia(j) are independent of the observation time period.

Abstract: Techniques whereby a transmitter/receiver pair are cooperatively arranged to buffer incoming data to both the transmitter and the receiver. The transmitter and receiver of the pair are coupled, generically, by pre-existing channel which has a known, fixed capacity. The transmitter/receiver pair exploits whatever delay is permissible, as determined by end-users of the data, for the data stream or streams that are using the channel for the purpose of accommodating periods of excessive instantaneous aggregate data transfer demands. The matched transmitter/receiver pair thereby permits (i) the transmission of a variable rate stream over a channel with capacity less than the peak rate of the stream, or (ii) the multiplexing of variable and/or fixed rate data streams.

Abstract: A method and apparatus are provided for minimizing overhead in packet re-transmission in a communication system. Each packet is given a sequence number, based on a current transmission rate, the size of the packet, and a previously assigned sequence number. The packet size can be adapted so that the entire packet fits into a single transmission block. The packet size may also be adapted based on throughput. The packet size may be adapted based on the transmission rate and/or throughput, whether the packet is being transmitted the first time or if it is being re-transmitted. Alternately, if the packet is being re-transmitted, the packet is transmitted at its original transmission rate, regardless of the current transmission rate.

Abstract: A method of handling data packets in a series of network switches is disclosed. An incoming data packet is received at a data port of a first lower capacity switch of the series of network switches and a stack tag is resolved from a header of the incoming data packet. The incoming data packet is forwarded to a first higher capacity switch, on a first stacked connection operating at a first data rate, based on the stack tag. A destination address of said incoming data packet is resolved by the first higher capacity switch and the header of the incoming packet is modified. The incoming data packet is forwarded to a second higher capacity switch, on a second stacked connection operating at a second data rate, based on the resolved destination address, where the header of the incoming data packet is modified and the incoming data packet is forwarded to a second lower capacity switch on a third stacked connection operating at the first data rate.

Abstract: A data switch for network communications includes at least one first data port interface which supports a plurality of data ports which transmit and receive data at a first data rate. At least one second data port interface is provided; the at least one second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the at least one first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory.

Abstract: An ATM system transmits different types of cells (data, forward resource management (RM) and backward RM) from station A through switch(es) to station B. Different fields in an Available Bit Rate (ABR) table provide controls over the rate of such cell transmissions. First particular field values in such table control the selection of successive ones of cell decision blocks which determine the type of cell to be transmitted. Second particular field values in such table control the selection of one of a plurality of entries in an exponent table which also provides other parameter values controlling the generation of an explicit rate. Third particular field values in the ABR table control the selection of an individual one of a plurality of rate decision blocks each indicating an individual rate of cell transmission from the station A to the station B.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An entry storing packet information to be retrieved at a high speed is hit by retrieval with a high-speed retrieval mechanism. Packet information to be retrieved at a medium speed is not cataloged in the high-speed retrieval mechanism and is miss-hit by retrieval with the high-speed retrieval mechanism, but is hit by retrieval with a medium-speed retrieval mechanism. The other packet information is cataloged in only a low-speed retrieval mechanism, which is realized by software or the like, and is hit by retrieval with the low-speed retrieval mechanism. This construction can realize a table-type data retrieval mechanism which can realize required retrieval performance at low cost and can dynamically cope with a variation in packet arrival frequency to reduce unnecessary cost.

Abstract: A network switch for network communications includes a first data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is configured to communicate with a CPU, and an internal memory communicates with the first data port interface and the second data port interface. A memory management unit is provided, including an external memory interface, for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, for communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit.

Abstract: A method of identifying a target data packet from a series of data packets being received or transmitted by a communications device, each data packet having a series of data values. The method having the steps of establishing a condition for the target data packet, the condition having a particular data position value and an associated particular data value; storing the particular data position value in a first content addressable memory, the first content addressable memory receiving a value related to a data position of a data value and the first content addressable memory generating a position match indicator; storing the particular data value in a second content addressable memory, the second content addressable memory receiving the data value and the second content addressable memory generating the data value match indicator; comparing the position match indicator and the data value match indicator to determine if the condition for the target data packet has been satisfied by the transmitted data value.

Abstract: Techniques for determining an output rate for a bit stream, the output rate being determined by applying information read from the bit stream to available bandwidths. The techniques are employed to construct a statistical multiplexer 80 that multiplexes varying bit-rate bit streams. Minimum and maximum output rates for each bit stream are determined such that neither a queue for the bit stream in the multiplexer nor the bit stream's decoder will underflow or overflow. The multiplexer first allocates each bit stream its minimum bandwidth and then allocates any remaining bandwidth to the bit streams in proportion to the difference between the minimum and maximum output rates for the bit streams, with no bit stream receiving more than its maximum output rate. If there is not enough bandwidth to give every bit stream its minimum rate, glue frames may be inserted, or low priority channels dropped.

Abstract: An exchange constituting an ATM network administers the number of UBR connections for every line port included in the exchange. Upon receiving a request for setting a UBR connection, the exchange determines the route of the UBR connection on the basis of the number of the UBR connections administered for every line port included in the exchange.

Abstract: A method is disclosed for transmitting data packets in wide area networks (WAN) by way of a synchronous digital data transmission network (SDH), wherein the data packets are packed into synchronous transport modules (STM-N) and are transmitted by way of virtual connections formed by subunits of synchronous transport modules of the same size. The virtual connections are entered into an address table and an evaluation of the target address of the data packets takes place in one of the network elements of the synchronous digital data transmission network. On the basis of the address table and the target address, at least for a part of the data packets, a decision is made by at least one of the network elements of the synchronous digital data transmission network as to which one of the virtual connections is used to transmit this data packet. Furthermore, a network element is disclosed, which operates in accordance with the transmission method.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM network includes a set of interconnected switches and gateways. The ATM network is capable of providing both a conventional connection-oriented service or a connectionless service. Where a connectionless service is required, at the input interface, source and destination addresses are inserted into the header and fields in the header are set to values which indicate that a connectionless service is required and whether or not additional processing is also required. At each node between the input interface and the output interface, where a connectionless service is required, each ATM cell is routed in accordance with its source address and destination address and/or a routing table which is set up by routing protocol or network management.

Abstract: High transmission capacity in a twisted pair signal line, where power is limited by a power spectral-density mask and an aggregate signal power constraint, is obtained by: (1) allocating data to multitone sub-bands according to a lowest marginal power-cost per bit scheme and (2) in an environment where an aggregate power budget remains after all bits have been allocated to all sub-bands with sufficient margins to carry a bit, assigning additional bits to sub-bands with otherwise insufficient power margins to carry a single bit, by frequency-domain-spreading a single bit across several sub-bands at correspondingly reduced power levels, to permit the otherwise unacceptable noise levels to be reduced on average by despreading at the receiving end.

Abstract: The invention relates to a packet switching system comprising at least a coupling device which comprises a main memory for buffering packets arriving by auxiliary lines, a main memory controller for generating addresses for the packets to be stored in the main memory and for controlling the write and read operations of the packets and a demulfiplexer controlled by the main memory controller for transporting the packets by trunk lines. The main memory controller comprises an address memory for producing an address for a write operation, buffers assigned to each trunk line, for buffering the addresses produced by the address memory, and a decoding device. The decoding device is provided for selecting a buffer for an address to be stored in dependence on the destination of the packet, for selecting a buffer for producing an address for the read operation from the main memory and for accordingly controlling the demultiplexer.

Abstract: A method and apparatus for digitally synchronizing data units received from multiple asynchronous data sources which includes storing the data necessary to compensate for phase and frequency differences between the independently clocked asynchronous sources. The method includes the step of comparing the input queues for each of said data streams against a set of known threshold conditions, and generating the composite output upon satisfaction of the threshold conditions. This method allows data from asynchronous data sources to be properly interleaved without implementation of complex phase or frequency compensation techniques, and without a large amount of data storage for buffering the input data. Furthermore, in its preferred embodiment, this invention allows the implementation of a fixed rate output clock, which greatly simplifies the design over the prior art.

Abstract: The invention provides a time division multiplexing system for a digital exchange which suppresses appearance of a time slot which, although exchanging can be performed by a time division switch, is put into a non-used state to improve the efficiency in use and which allows line interface apparatus to be accommodated in a time division multiplexing highway even where the line interface apparatus require a multiplicity larger than that of the highway to suppress an increase in circuit scale and simplify the circuit construction.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.