Having Input Or Output Storage Or Both Patents (Class 370/395.71)
  • Patent number: 12063156
    Abstract: A system for admission and flow control is disclosed. In some embodiments, the system includes a switch for routing network traffic, having multiple classes of service (CoSs), from multiple ingress ports to one or more of multiple egress ports. The system also includes multiple ingress-level class of service queues (InCoS-Qs) and one or more egress-level class of service queues (EgCoS-Qs), each InCoS-Q and EgCoS-Q corresponding to one of CoSs. The switch is configured to detect congestion in a particular EgCoS-Q, corresponding to a particular CoS, the particular EgCoS-Q being associated with a particular host; identify an InCoS-Q corresponding to that particular CoS, and associated with that particular host; and block that InCoS-Q, while allowing routing of the network traffic from one or more InCoS-Qs corresponding to that particular CoS, the one or more InCoS-Qs corresponding to one or more other hosts.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: August 13, 2024
    Assignee: Enfabrica Corporation
    Inventors: Gurjeet Singh, Ari Aravinthan, Shimon Muller, Jay Peterson, Shrijeet Mukherjee
  • Patent number: 10547532
    Abstract: A method for parallel processing of ingress packets destined to a plurality of inline tools is provided. An ingress packet is processed to extract a plurality of packet header fields and to generate a packet identifier. A hash index is generated by hashing information associated with the plurality of packet header fields. A copy of the ingress packet and the packet identifier are stored in a hash table entry using the generated hash index. The ingress packet is simultaneously forwarded to each of the plurality of inline tool devices.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: January 28, 2020
    Assignee: NetScout Systems, Inc.
    Inventors: Peter C. Vinsel, Andrew R. Harding, Gordon Beith, Erik W. Hjelmstad
  • Patent number: 10133597
    Abstract: Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Kun Tian, Zhiyuan Lv, Yao Zu Dong
  • Patent number: 9762479
    Abstract: Multiple network controllers are interconnected in a full mesh structure, e.g., through a cyclical cross connector, to form a distributed control system for a network of a large number of nodes. A network controller acquires characterizing information of links emanating from a respective set of nodes, communicates the information to each other network controller, and determines a route set from each node of the respective set of nodes to each other node of the network. The network controller may determine, for each link included in the route set, identifiers of specific route sets which traverse the link. Accordingly, a state-change of any link in the network can be expeditiously communicated to network controllers to take corrective actions where necessary. A network controller may rank routes of a route set according to some criterion to facilitate selection of a favourable available route for a connection.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 12, 2017
    Inventor: Maged E. Beshai
  • Patent number: 9571413
    Abstract: A method and an apparatus for implementing round robin scheduling are provided. The method includes: acquiring, from a queue, original location information of elements in the queue; performing location mapping processing on the original location information of the elements in the queue based on a set algorithm to obtain mapped location information of the elements in the queue, where the set algorithm or parameters used by the set algorithm change according to a set rule during each time of round robin scheduling; and starting from an element corresponding to a set initial location, performing round robin scheduling according to mapped queue sequences corresponding to the mapped location information of the elements. The method and the apparatus for implementing round robin scheduling can reduce the cost of storage devices and can ensure a balance in scheduling of elements in a service queue.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: February 14, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Dongchuan Li, Guoming Shen, Xianqin Li
  • Patent number: 8971325
    Abstract: Exemplary embodiments of a system and method enable application of policy using Layer 2 fields for a data frame, simplified data structures, or both. In accordance with one aspect of the present invention, a policy may be based upon a destination address (DA), a source address (SA), or a virtual local area network identification (VID) associated with a data frame.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: March 3, 2015
    Assignee: Marvell International Ltd.
    Inventor: Donald Pannell
  • Patent number: 8937958
    Abstract: According to one embodiment, a router includes a plurality of input ports and a plurality of output ports. The input ports receive a packet including control information indicating a type of access. Each of the input ports includes a first buffer and a second buffer which store the packet. The output ports output the packet. Each of the input ports selects at least one of the first buffer and the second buffer as a buffer in which the packet is stored on the basis of the control information and a state of the output port serving as a destination port of the packet.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hui Xu
  • Patent number: 8917738
    Abstract: Described embodiments provide a method of processing packets of a network processor. One or more tasks are generated corresponding to received packets associated with one or more data flows. A traffic manager receives a task corresponding to a data flow, the task provided by a processing module of the network processor. The traffic manager determines whether the received task corresponds to a unicast data flow or a multicast data flow. If the received task corresponds to a multicast data flow, the traffic manager determines, based on identifiers corresponding to the task, an address of launch data stored in launch data tables in a shared memory, and reads the launch data. Based on the identifiers and the read launch data, two or more output tasks are generated corresponding to the multicast data flow, and the two or more output tasks are added at the tail end of a scheduling queue.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: December 23, 2014
    Assignee: LSI Corporation
    Inventors: Balakrishnan Sundararaman, Shailendra Aulakh, David P. Sonnier, Rachel Flood
  • Patent number: 8902899
    Abstract: A method includes receiving a first packet at an input of a switching device and determining whether to insert first data associated with the first packet into a normal buffer of the input. The determination of whether to insert first data associated with the first packet into the normal buffer includes determining whether the first output identifier matches a second output identifier corresponding to second data in the normal buffer that is associated with a second packet. The first data is inserted into the normal buffer when the first output identifier matches the second output identifier.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Chrysos, Anil Pothireddy, Brian T. Vanderpool
  • Patent number: 8891523
    Abstract: An apparatus includes a multiprocessor including a plurality of processors including respective memories. Each of the memories has a dedicated storage location for multicast messages. At least one bus is coupled in common to the plurality of processors. The apparatus further includes an IPC unit coupled to the at least one bus and configured to retrieve multicast messages from the dedicated storage locations via the at least one bus and to selectively route the retrieved multicast messages among the plurality of memories.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwan-jin Yong, Hyoung-jin Yun, Woon-hyug Jee
  • Patent number: 8873574
    Abstract: A network-attached storage apparatus is configured to be in communication with a local device. The apparatus includes storage devices for storing data, one interface for establishing communication with the network and another interface for establishing communication with the local device. A processor enables the interfaces to alternatively establish communication with the local device or the network.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: October 28, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thomas H. Szolyga, Mike McCullough
  • Patent number: 8798074
    Abstract: In general, techniques are described for packet queuing within ring networks. In accordance with the techniques, a network device of a ring network comprises a memory having a different queue for each order-dependent pair of the network devices. Each pair represents a different order-dependent combination of the network devices that includes an ingress network device that provides an ingress to the ring network and an egress network device that provides an egress from the ring network. The network device further comprises an interface for receiving a packet from a neighboring one of the plurality of network devices and a control unit that, in response to receiving the packet, stores the packet to one of the queues based on which network devices is the ingress and which network device is the egress for the packet. The control unit forwards the stored packet via the ring network according to a scheduling algorithm.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 5, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Kireeti Kompella, Pradeep Sindhu, Jean-Marc Frailong, David J. Ofelt
  • Patent number: 8767724
    Abstract: Non-destructive data storage is disclosed. An information change is stored that is associated with a business object such that tracking of the information change is enabled with respect to one a transaction time and/or an effective time. The stored information change is accessed with respect to a time.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: July 1, 2014
    Assignee: Workday, Inc.
    Inventor: John Malatesta
  • Patent number: 8730802
    Abstract: A system and method of transmitting packets from a wireless device is provided. According to a broad aspect, the wireless device is to transmit a packet on a communication channel during a time window based on whether or not the communication channel is expected to be torn down during the time window. If the communication channel is not expected to be torn down during the time window, then the wireless device transmits the packet late in the time window. However, if the communication channel is expected to be torn down during the time window, then the wireless device transmits the packet during the time window just prior to when the communication channel is expected to be torn down. This prevents having to re-establish the communication channel merely to transmit the packet if the communication channel is torn down.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 20, 2014
    Assignee: BlackBerry Limited
    Inventor: Arun Munje
  • Patent number: 8730974
    Abstract: Network entities such as an access device and a gateway analyze messages exchanged during a communication session to identify information items of interest such as, for example, email addresses, universal resource locators, file paths, and attachments. References to and/or the contents of the identified information items may be stored in a database that associates the identified information items with the participants of the communication session. The participants in the communication session may be identified by conventional caller ID information, or by an Internet protocol address, an electronic serial number, or a variety of other identifiers. Information received at the beginning of a later communication session that identifies participant(s) in that communication session may then be used to select from the database, information items from previous communication session, that are associated with the identified participant in the current communication session.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: May 20, 2014
    Assignee: Broadcom Corporation
    Inventors: Jeyhan Karaoguz, Noel Whitley
  • Patent number: 8395996
    Abstract: Techniques that assist in processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, only a subset of FDP packets received by the network device is forwarded to the CPU for processing, the other FDP packets are dropped and not forwarded to the CPU. In this manner, the amount of processing that a CPU of the network device has to perform for incoming FDP packets is reduced. This enables the network device to support newer FDPs with shorter periodic interval requirements.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: March 12, 2013
    Assignee: Foundry Networks, LLC
    Inventors: Yuen Wong, Pedman Moobed
  • Patent number: 8379524
    Abstract: Network switching and/or routing devices can use multiple priority data streams and queues to support prioritized serial transmission of data from line cards (or the like) through a fabric switch to other line cards (or the like). Preemption logic is used to insert within a data stream commands indicating a switch from one priority level data to another. Delimiter commands and combination switch/delimiter commands can also be used. Multiple crossbars are implemented in the fabric switch to support the various data stream priority levels.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: February 19, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Mick R. Jacobs, Michael A. Benning
  • Patent number: 8259724
    Abstract: A data transmitting apparatus makes it possible to send out a retransmitting packet at early timing even when a delivery tree structure is unclear.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: September 4, 2012
    Assignee: Panasonic Corporation
    Inventors: Kazunobu Konishi, Eiichi Muramoto, Takahiro Yoneda, Ichiro Takei, Masashi Kobayashi, Taisuke Matsumoto
  • Patent number: 8184642
    Abstract: Program clock references in first and second MPEG data streams are re-stamped in accordance with delays introduced into the first and second MPEG data streams. Accordingly, the program clock references in the first MPEG data stream are re-stamped according to a variable delay in the first MPEG data stream, and the program clock references in the second MPEG data stream are re-stamped according to a variable delay in the second MPEG data stream. The re-stamped program clock references in the second MPEG data stream are corrected according to a fixed delay in the second MPEG data stream. The first and second MPEG data streams are multiplexed, and the multiplexed first and second MPEG data streams are transmitted and received.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: May 22, 2012
    Assignee: Zenith F. ectronics LLC
    Inventors: Jin H. Kim, Timothy G. Laud, Lay Yee Lim
  • Patent number: 8155011
    Abstract: Techniques are provided for assisting in the processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, only a subset of FDP packets received by the network device is forwarded to the CPU for processing, the other FDP packets are dropped and not forwarded to the CPU. The processing is performed using dual memory structures that enable receipt of FDP packets by the network device to be decoupled from the processing of FDP packets by the CPU of the network device.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: April 10, 2012
    Assignee: Foundry Networks, LLC
    Inventors: Yuen Wong, Pedman Moobed
  • Patent number: 8149848
    Abstract: A system and method for providing enhanced information to a user is described. A broadband access gateway communicatively coupled to a plurality of access devices may collect information about multimedia content available on the access devices and/or information exchanged with access devices. The gateway may search the collect information upon receiving information identifying a called or calling party, to find information that may be associated with the called or calling party. Selected items of the information associated with the called or calling party may then be delivered to the access device of the called or calling party. Information accessible to the gateway via a broadband connection may also be made available to the user of the access device.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: April 3, 2012
    Assignee: Broadcom Corporation
    Inventors: Jeyhan Karaoguz, Marc Abrams, Nambirajan Seshadri
  • Patent number: 8040901
    Abstract: In general, techniques are described for packet queuing within ring networks. In accordance with the techniques, a network device of a ring network comprises a memory having a different queue for each order-dependent pair of the network devices. Each pair represents a different order-dependent combination of the network devices that includes an ingress network device that provides an ingress to the ring network and an egress network device that provides an egress from the ring network. The network device further comprises an interface for receiving a packet from a neighboring one of the plurality of network devices and a control unit that, in response to receiving the packet, stores the packet to one of the queues based on which network devices is the ingress and which network device is the egress for the packet. The control unit forwards the stored packet via the ring network according to a scheduling algorithm.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: October 18, 2011
    Assignee: Juniper Networks, Inc.
    Inventors: Kireeti Kompella, Pradeep Sindhu, Jean-Marc Frailong, David J. Ofelt
  • Patent number: 8031723
    Abstract: A device comprising i) input ports and output ports for receiving and transmitting data packets, ii) a receiver to extract primary switching or routing data and secondary data to be handled and to associate the secondary data with a selected storage address, iii) a memory for storing the secondary data extracted at the storage address, iv) a switching stage and a routing stage configured to receive the storage address and the primary switching or routing data and to determine tertiary data designating at least one of the output ports and to determine new primary data, v) extracting the tertiary data and the new primary data from the switching stage and the routing stage to deliver the data and the storage address as a function of a selected criterion, and vi) sending the secondary data stored at the storage address, combined with the new primary data to each output port designated by the tertiary data.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: October 4, 2011
    Assignee: Alcatel Lucent
    Inventor: Albert Lespagnol
  • Patent number: 8018936
    Abstract: A method and apparatus is shown for communicating Fibre Channel frames between distinct fabrics. A proxy zone is established in each fabric with a physically present local device and a remote fabric device. A router creates a proxy device in each fabric for every device not physically connected to the fabric. The proxy devices appear to be directly attached to the router. The router handles all address translations between proxy and physical addresses. When multiple routers are encountered, the ingress router does all address translation. No routing or encapsulation headers are used except when routing between two routers. The source ID and the originator exchange identifier are stored at the egress router for all link requests that require special handling. When replies pass through that router, the destination ID and originator exchange identifier are compared with the stored information. On a match, the reply is specially handled.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: September 13, 2011
    Assignee: Brocade Communications Systems, Inc.
    Inventor: David Peterson
  • Patent number: 7974282
    Abstract: For continuing multicast data transfer according to path control information after being switched from an active status to a standby status, it is necessary that the standby status hold the same path control information as the active status. However, a synchronization of the path control information thereof is not guaranteed. To solve the above-mentioned problem, this invention provides a data transfer apparatus coupled to a network, including a plurality of interfaces for transmitting and receiving data, in which the data transfer apparatus is configured to: create transfer destination information for correlating a destination of the data with the interfaces for transmitting the data to be transmitted to the destination; and transmit, upon reception of multicast data via one of the interfaces before being judged that the transfer destination information has been created, the multicast data from at least one of the interfaces irrespective of the transfer destination information.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: July 5, 2011
    Assignee: Alaxala Networks Corporation
    Inventors: Takeshi Shibata, Kenichi Sakamoto, Hidehiro Fukushima
  • Patent number: 7974275
    Abstract: Methods for aging datagrams in the memory portion of a datagram distribution device or other network device are provided. According to some of these methods, an attribute of each datagram entering the device may be used to assign an initial aging counter value to each datagram. Then, the attribute-specific aging counter values may be used to extend the time until expiration of certain datagrams relative to other datagrams. Also, devices for implementing these methods are provided.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: July 5, 2011
    Assignee: Broadcom Corporation
    Inventor: Chien-Hsien Wu
  • Patent number: 7961721
    Abstract: A router for a network is arranged for guiding data traffic from one of a first plurality Ni of inputs (I) to one or more of a second plurality No of outputs (O). The inputs each have a third plurality m of input queues for buffering data. The third plurality m is greater than 1, but less than the second plurality No. The router includes a first selection facility for writing data received at an input to a selected input queue of the input, and a second selection facility for providing data from an input queue to a selected output. Pairs of packets having different destinations Oj and Ok are arranged in the same queue for a total number of Nj,k inputs, characterized in that Nj,k<N for each j,k.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: June 14, 2011
    Assignee: NXP B.V.
    Inventors: Theodorus Jacobus Denteneer, Ronald Rietman, Santiago Gonzalez Pestana, Nick Boot, Ivo Jean-Baptiste Adan
  • Patent number: 7916719
    Abstract: A method and HARQ memory apparatus in a BWA communication system are provided where the HARQ memory apparatus includes a memory configured to partition the entire memory area in units of slots corresponding to the size of a concatenation block, to input/output a plurality of channel data to the slot in units of the concatenation block, to store a new concatenation block in an empty slot, and to combine a retransmitted concatenation block with a prestored concatenation block and store the combined concatenation block at a prestored location. Accordingly, the required amount of memory can be reduced by using a buffer efficiently. In particular, when a memory is embedded in an integrated circuit, the size and power consumption of the integrated circuit can be reduced.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Woo Roh, Ji-Yun Seol, Bong-Gee Song, Jong-Han Lim, Jung-Ho Lee
  • Patent number: 7869440
    Abstract: Streaming data is processed through one or more pipes of connected modules including mixers and/or splitters. The data is carried in composite physically allocated frames having virtual subframes associated with different ones of the splitters, mixers, and other transform modules. Nesting trees and pipe control tables represent the structure of the pipes. A frame allocator is assigned to a particular module in a pipe. Rather than issuing a control transaction to all modules when any one of them completes an operation upon its source data, a control manager requests a module to begin its operation only when all of its input subframes have become available. Frame control tables record when any module has completed an operation, and a pipe control table lists which modules provide data to which other modules.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: January 11, 2011
    Assignee: Microsoft Corporation
    Inventors: Rafael S. Lisitsa, George H. J. Shaw, Dale A. Sather, Bryan A. Woodruff
  • Patent number: 7856022
    Abstract: Transferring I/O from a first storage device coupled to a storage area network to a second storage device coupled to the storage area network includes blocking I/O operations for a first port of the first storage device coupled to the storage area network, where the first port is associated with a first identifier. Transferring I/O also includes coupling the second storage device to the storage area network via a port associated with a second identifier different from the first identifier, coupling a virtualization engine to the storage area network via a first port provided with the first identifier and via a second port, and causing at least a portion of I/O operations received by the virtualization engine through the first port thereof to be routed through the second port thereof to the second storage device without host/application disruption.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: December 21, 2010
    Assignee: EMC Corporation
    Inventor: Ian Wigmore
  • Patent number: 7848334
    Abstract: A device is coupled to a first network and a second network and comprises a first storage element and a second storage element. The device stores data packets originating from the first network in the first storage element and stores data packets destined for the second network in the second storage element. In particular, the device slaves the writing of a data packet intended for the second network into the second storage element to the reading of the data packet from the first storage element so that the transfer time inside the device is constant for all the data packets.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: December 7, 2010
    Assignee: Thomson Licensing
    Inventors: Jean-Charles Guillemot, Claude Chapel, Thierry Tapie
  • Patent number: 7839861
    Abstract: Embodiments of the invention relates to bandwidth requirements within a packet data network. A method and system for analysing traffic is described herein. The method may utilises an estimation of a concave hull function of the arrived traffic within the buffer. The use of such a concave hull representation may allows for more efficient data processing and for a direct measurement of desired service rates for differing predetermined control parameters.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: November 23, 2010
    Assignee: Corvil Limited
    Inventors: Fergal Toomey, Ian Edward Dowse, Matthew Charles Davey
  • Patent number: 7822916
    Abstract: A search engine device includes a lookup circuit, such as a content addressable memory (CAM) array. This lookup circuit is configured to generate multiple active match signals in response to detecting multiple matches between a search operand applied to said lookup circuit and multiple entries therein, during a search operation. A priority sequencer circuit is also provided. This priority sequencer circuit, which is electrically coupled to outputs of the lookup circuit, is configured to sequentially encode each of the multiple active match signals according to priority.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: October 26, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Tingjun Wen
  • Patent number: 7778254
    Abstract: A method for managing congestion in a stack of network switches includes the steps of receiving an incoming packet on a first port of a network switch for transmission to a destination port and determining if the destination port of the packet is a monitored port. Thereafter, the method determines a queue status of the destination port, if the destination port is determined to be a monitored port, and preschedules transmission of the incoming packet to the destination port if the destination port is determined to be a monitored port.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: August 17, 2010
    Assignee: Broadcom Corporation
    Inventors: Shiri Kadambi, Mohan Kalkunte, Shekhar Ambe
  • Patent number: 7773592
    Abstract: Method and system for routing frames in a network is provided. The method comprises, receiving a frame at a receive port of a networking switch element; determining a transmit port and a virtual lane for routing the frame; asserting a request signal to the transmit port; waiting for an accept signal from the transmit port; determining if an output link on the transmit port is unavailable and if a flow control credit is available for transmitting the frame; sending the frame to the transmit port if the accept signal is asserted; and transmitting the frame on the output link and de-asserting the request signal.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: August 10, 2010
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Leonard W. Haseman
  • Patent number: 7769003
    Abstract: A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Rene Glaise, Alain Blanc, Francois Le Maut, Michel Poret
  • Patent number: 7764710
    Abstract: If an input word bit includes overhead data, the input word bit is ignored. If the input word bit includes non-overhead data and the corresponding bit position in a first buffer is empty, the non-overhead data is stored in the corresponding bit position in the first buffer, and the corresponding bit position in the first buffer is marked as full. Otherwise, the non-overhead data is stored in the corresponding bit position in a second buffer, and the corresponding bit position in the second buffer is marked as full. When all bit positions in the first buffer are marked as full, the data is shifted out of the first buffer, rotated to be in data arrival sequence, and made available for further processing. Then, the data in the second buffer is transferred to the first buffer, and the bit positions in second buffer are reset to be marked as empty.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: July 27, 2010
    Assignee: Altera Corporation
    Inventor: Peter Bain
  • Patent number: 7672315
    Abstract: Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: March 2, 2010
    Assignee: Transwitch Corporation
    Inventors: Dinesh Gupta, Dev Shankar Mukherjee, Rakesh Kumar Malik
  • Patent number: 7660247
    Abstract: Methods and systems for dynamically adjusting credits used to distribute available bus bandwidth among multiple virtual channels, based on the workload of each virtual channel, are provided. Accordingly, for some embodiments, virtual channels with higher workloads relative to other virtual channels may receive a higher allocation of bus bandwidth (more credits).
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bruce L. Beukema, Jamie R. Kuesel, Robert A. Shearer, Bruce M. Walk
  • Patent number: 7653075
    Abstract: A network system includes a first device and a second device separated by a network having asymmetric routes in which traffic forwarded in a first direction from the first device to the second device may travel a different route than traffic forwarded in a second direction from the second device to the first device. At least three intermediate processing devices are located between the first device and the second device, wherein at least two of the intermediate processing devices are located along different asymmetric routes. The intermediate processing devices intercept a communication flow between the first device and the second device, and encapsulate the communication flow within network tunnels so that communications associated with the communication flow in the first direction and the second direction are forwarded between a same set of at least two of the intermediate processing devices.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: January 26, 2010
    Assignee: Juniper Networks, Inc.
    Inventors: Balraj Singh, Nitin Gugle
  • Patent number: 7630406
    Abstract: Embodiments of methods and apparatus for providing a delayed attack protection system for network traffic are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: December 8, 2009
    Assignee: Intel Corporation
    Inventors: Kapil Sood, Jesse Walker, Emily H. Oi
  • Patent number: 7606153
    Abstract: Prior to alteration of the communication route connecting the enterprise servers 51 to 53, ports a, b and c of the enterprise server 51 are each connected with port 1 of the storage system 7 through the communication route. When enterprise server 54 is connected with the storage system 7 in response to a new connection request, the communication port of the storage system 7 with which ports a, b and c are respectively connected through the communication route is altered to port 3. Due to this alteration, the enterprise server 544 can be connected through its port f via the communication route with the port 1 of the storage system 7, which was thus freed.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: October 20, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Hironobu Nakaya, Hiroyuki Shobayashi
  • Patent number: 7594024
    Abstract: A storage server in a storage area network (SAN) environment connecting host computers and storage devices. The storage server includes a plurality of storage processors and a switching circuit. Data is routed between the storage processors via the switching circuit according to routing tags. The routing tags are examined prior to completely receiving the data, allowing the data to be routed with minimal delay.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: September 22, 2009
    Assignee: NetApp, Inc.
    Inventors: Nilesh Shah, Rahim Ibrahim, Nghiep Tran, Tuan Nguyen
  • Patent number: 7594074
    Abstract: To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data caching control units are connected to each other through an interconnection, the data caching control units are divided into plural control clusters, each of the control clusters including at least two or more data caching control units, control of a cache memory is conducted independently for each of the control clusters, and one of the plural data caching control units manages, as a single system, protocol transformation units and the plural control clusters based on management information stored in a system management information memory unit.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: September 22, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Fujimoto, Mutsumi Hosoya, Naoki Watanabe, Kentaro Shimada
  • Patent number: 7512134
    Abstract: The disclosed invention relates to a method and system to transmit data packets through a switched network system that is composed of a plurality of routing entities. The method determines whether or not the output port assigned to the data packet and the associated input port are local to the routing entity by referencing an index pointer to a routing table.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Claudiu Schiller, Leah Shalev
  • Patent number: 7499452
    Abstract: Methods and apparatus that allow recovery in the event that sequence counts used on receive and transmit sides of a communications link become out of sync are provided. In response to receiving a packet with an expected sequence count from a receiving device, a transmitting device may adjust pointers into a transmit buffer allowing the transmitting device to begin transmitting packets with the sequence count expected by the receiving device.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: March 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Shearer, Martha E. Voytovich, Craig A. Wigglesworth
  • Patent number: 7492781
    Abstract: The object of the invention is to create a router which has an enhanced processing speed. According to the invention, before access through a readout unit, the pointers for information packets stored in the buffer memory are arranged as required. If an overflow is imminent in a buffer memory area, for example, then individual pointers are selected and removed from the buffer memory area. The selected pointers are shifted into an additional buffer memory area, for example. This additional buffer memory area is then preferentially read out, so that the selected pointers are read out before the pointers in the buffer memory area. The criterion for the selection of a pointer is, for example, an expired reactivation time or a buffer memory area that is filled above a threshold value.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: February 17, 2009
    Assignee: Alcatel
    Inventor: Ralf Klotsche
  • Patent number: 7450594
    Abstract: In multi-connections, a message writing apparatus is provided. This message writing apparatus (21) comprises a path recognizing section (21a), a received message assembling section (21b), a receive control section (21c), an arbitrating section (21d) and an external memory control section (21e). When a received ATM cell is written/readout in/from a receiving buffer, it is written/read out in a memory area corresponding to each path, which enables the processing of AAL5 messages from a plurality of paths and improves the transfer processing capability, thereby leading to realizing a shortening of the data transfer time.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: November 11, 2008
    Assignee: Fujitsu Limited
    Inventors: Akira Yamamori, Takeshi Sasaki, Eiji Maeda, Masao Maeda, Tatsuya Oku, Yoshinori Okuda, Tsuguo Okada, Akihiro Yasuo, Jinichi Yoshizawa
  • Patent number: 7406039
    Abstract: A system and method for managing the multipath failover protocol of a storage area network that includes storage systems that include multiple ports and multiple storage controllers. A number of available storage paths between each server and each storage unit of the storage system are identified. A storage path is selected. In the event that the storage path becomes inoperable, an alternate storage path is selected in replacement of the inoperable storage path. The alternate storage path will be selected so that it does not include a storage controller that was part of the inoperable storage path.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: July 29, 2008
    Assignee: Dell Products L.P.
    Inventors: Jacob Cherian, Thomas J. Kocis
  • Patent number: RE43466
    Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: June 12, 2012
    Assignee: Polytechnic University
    Inventors: Eiji Oki, Hung-Hsiang Jonathan Chao, Roberto Rojas-Cessa