Input Or Output Circuit, Per Se (i.e., Line Interface) Patents (Class 370/419)
  • Patent number: 8605624
    Abstract: Methods and devices are provided for detecting whether peer ports interconnecting two network devices can perform a novel protocol called Exchange Peer Parameters (“EPP”). If the peer ports are so configured to perform EPP, EPP services are exchanged between the peer ports. In a first phase, information is exchanged about peer port configurations of interest. In a second phase, the results of the exchange of information are applied to hardware and/or software of the respective ports, as needed.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: December 10, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Tushar Desai, Shashank Gupta, Praveen Jain, Kalyan K. Ghosh
  • Patent number: 8605698
    Abstract: A vehicle, comprises a vehicle network bus and a mobile router. The mobile router comprises a local area network interface comprising a first wireless transceiver of a first predetermined type to provide a link to first a local area network and a wide area network interface comprising a second wireless transceiver of a second predetermined type to provide a link to a wide area network. One of the wide area network interface and the local area network interface is selectively operable to establish a wireless communication link with a network management system comprising a communication server. The router further comprises an application executable by the at least one processor to selectively acquire predetermined data from the vehicle network bus. The communication agent is operable to upload the predetermined data to the network management system.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: December 10, 2013
    Assignee: Autonet Mobile, Inc
    Inventors: Douglas S Moeller, Ronald W Pashby
  • Publication number: 20130322460
    Abstract: A first cluster includes first switching devices that are compatible with a software-defined networking (SDN) protocol. A second cluster includes second switching devices within or partially overlapping the first cluster. Each second switching device is compatible with a protocol for an open systems interconnection (OSI) model layer. The first switching devices include one or more border switching devices located at a boundary between the first cluster and the second cluster. Each border switching device is also compatible with the protocol for the OSI model layer. The first switching devices effect first multipathing through the network except through the second cluster, and the second switching devices effect second multipathing just through the second cluster of the network. As such, the first switching devices and the second switching devices together effect end-to-end multipathing through both the first cluster and the second cluster of the network.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventors: Casimer M. DeCusatis, Keshav G. Kamble, Abhijit P. Kumbhare
  • Patent number: 8599846
    Abstract: A data and voice communication system includes communication between a line card and an accelerator card. Voice, data, and control traffic is received from the line card and is transmitted to the accelerator card via a physical link having separate voice, data, and control logical channels. The separate voice, data, and control logical channels are represented by labeled data packets.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: December 3, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Parvez Khan, Hamed Eshraghian
  • Patent number: 8599844
    Abstract: A packet network device includes a packet network processor memory system for storing information used to process and forward packets of information in and through the network device. The information is included in look-up tables whose entries can be mapped either horizontally or vertically into the memory system. In the event that the entries are mapped horizontally, a complete entry can be access at a single memory location and in the event that the entries are mapped vertically, the entries can be accessed at one or more memory locations.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: December 3, 2013
    Assignee: Force10 Networks, Inc.
    Inventors: Krishnamurthy Subramanian, Raja Jayakumar, Jason Lee
  • Patent number: 8594058
    Abstract: A method of dynamically adjusting a transmission capacity of a data transmission connection is proposed. The method comprises different steps at a network end node. An incoming frame-structured time division multiplex signal carrying incoming timeslots is received from a client. Furthermore, a request data set comprising for at least one incoming timeslot a corresponding subset is received. The subset has an identifier for identifying an existing data transmission connection and a status indicator for indicating to the network end node a status requested by the client for the corresponding timeslot. If the status indicator indicates a request for adding the timeslot to the data transmission connection or removing the timeslot from the data transmission connection, the network end node adjusts the transmission capacity of the data transmission connection.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: November 26, 2013
    Assignee: Alcatel Lucent
    Inventors: Alberto Bellato, Matteo Gumier, Paolo Fogliata
  • Patent number: 8594114
    Abstract: A bus driver circuit divides an internal data bus for an integrated circuit memory into at least two groups, designated by speed. A faster group of data lines and a slower group of data lines are placed in an interleaved fashion in order to provide a two group shielding solution. At the earliest opportunity following the reception of a read command, the data from memory banks in the memory is sorted into these two groups. For a DDR3 memory, the sorting method is based on the A2 column address, known as C2. All of the data is brought out of the banks in parallel and sorted as it enters the main amplifiers. These main amplifiers are also divided into two groups, faster and slower. Each amplifier then connects to a data line (G-line) of the same group. The clock assigned to the fast group fires right away, thereby connecting the data associated with the fast amplifiers to the fast data group. This data group then proceeds to the output buffers through the entire data path as fast as possible.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: November 26, 2013
    Assignee: ProMOS Technologies PTE. Ltd.
    Inventor: Jon Faue
  • Publication number: 20130308642
    Abstract: A communication apparatus communicating with an external apparatus via a relaying device is provided. The communication apparatus includes a communication unit configured to perform communication with the relaying device, and a control unit configured to reduce a communication speed of the communication unit to a lower speed if the communication apparatus is to be shifted from a first power mode to a second power mode in which power consumption is lower than that in the first power mode. The communication unit, if the communication apparatus shifts to the second power mode, transmits identification information of the communication apparatus to the relaying device using a first method, and after a predetermined time has passed, transmits the identification information to the relaying device using a second method.
    Type: Application
    Filed: May 13, 2013
    Publication date: November 21, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tomohiro Kimura
  • Patent number: 8588244
    Abstract: An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 19, 2013
    Assignee: Lantiq Deutschland GmbH
    Inventors: Shridhar Mubaraq Mishra, Tina Zhang, Chunfeng Hu, Hak Keong Sim
  • Patent number: 8588221
    Abstract: An interface includes three sub-interfaces. A first and second sub-interface receive first/second inbound IQ data streams, respectively, packetize the first/second inbound IQ data streams to obtain first/second inbound IQ data packets, respectively, and transmit the first/second inbound IQ data packets to the baseband processor via a first/second set of RX lanes, respectively. Each first/second inbound IQ data packet comprises a data packet identifier out of a common set of possible data packet identifiers. A third sub-interface receives outbound IQ data packets from the baseband processor via a TX lane, and depacketizes the outbound IQ data packets to obtain an outbound IQ data stream. The third sub-interface receives an RX not-acknowledge signal via the TX lane that identifies a defective first or second inbound IQ data packet within the first/second inbound IQ data packets.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: November 19, 2013
    Assignee: Intel Mobile Communications GmbH
    Inventors: Irene Schuster, Juergen Wahl
  • Patent number: 8582437
    Abstract: A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10 G/40 G data flows over a narrower interface to a second physical layer device having an inverse gearbox.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: November 12, 2013
    Assignee: Broadcom Corporation
    Inventors: Ali Ghiasi, Velu Pillai, Sundar Chidambara
  • Patent number: 8576873
    Abstract: A system and method for discovering channel impediments for Power over Ethernet (PoE) applications. Cabling power loss in PoE applications is related to the resistance of the cable itself. A PHY can be designed to measure electrical characteristics (e.g., insertion loss, cross talk, length, discontinuities, etc.) of the Ethernet cable to enable determination of the cable resistance. The determined resistance can be used in powering decisions and in adjusting power budgets allocated to power source equipment ports.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: November 5, 2013
    Assignee: Broadcom Corporation
    Inventor: Wael William Diab
  • Patent number: 8576861
    Abstract: A computer implemented method, apparatus, and computer usable program code for processing packets for transmission. A set of interface specific network buffers is identified from a plurality of buffers containing data for a packet received for transmission. A data structure describing the set of interface specific network buffers within the plurality of buffers is created, wherein a section in the data structure for an interface specific network buffer in the set of interface specific network buffers includes information about a piece of data in interface specific network buffer, wherein the data structure is used to process the packet for transmission.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Omar Cardona, James Brian Cunningham, Baltazar De Leon, III, Jeffrey Paul Messing
  • Patent number: 8576867
    Abstract: A pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach. Cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells, and then for nonconforming cells. Reservation vectors are used to permit the same time slot of the next frame to be reserved by a first queue, and the same time slot of the following time frame to be held for reservation by a second queue, to ensure equal time slot access by the first and second queues over successive time frames.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: November 5, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Ruixue Fan, Chi-Yu Lu
  • Patent number: 8576865
    Abstract: A switch includes a first IC and a second IC. The first IC includes a first set of (N+1) serializer/deserializer (SERDES) modules communicating with a first set of (N+1) SERDES modules of a switch IC; a first set of N SERDES modules communicating with a first set of N ports; and a first set of N multiplexer modules communicating with (i) the first set of N SERDES modules and (ii) the first set of (N+1) SERDES modules of the first IC. The second IC includes a second set of (N+1) SERDES modules communicating with a second set of (N+1) SERDES modules of the switch IC; a second set of N SERDES modules communicating with a second set of N ports; and a second set of N multiplexer modules communicating with (i) the second set of N SERDES modules and (ii) the second set of (N+1) SERDES modules of the second IC.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 5, 2013
    Assignee: Marvell International Ltd.
    Inventors: William Lo, Sehat Sutardja
  • Patent number: 8576866
    Abstract: Line cards receive control packets and perform a hierarchical rate limiting on those control packets. A set of identifier keys are extracted from the control packets and the protocol of those control packets are determined. At a first level, the control packets are rate limited per unique set of identifier keys per protocol. Those packets which fail the first rate limiting level are dropped. Those packets which pass the first rate limiting level are rate limited at a second level per protocol type. Those packets which fail the second level rate limiting are dropped while those packets which pass the second level rate limiting are sent to the control card for further processing.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: November 5, 2013
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventors: Anubhav Gupta, Arunkumar M. Desigan, Arun Sharma, Mukund Srinivasan
  • Patent number: 8576864
    Abstract: A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
  • Publication number: 20130290945
    Abstract: An information handling system is provided. The information handling system includes one or more devices coupled together to route information between the one or more devices and other devices coupled thereto based on routing information stored in the one or more devices. The one or more devices includes a routing processor, one or more line cards coupled to the routing processor, the one or more line cards receiving the routing information from the routing processor for routing data packets to a destination, and a memory coupled to the routing processor. The routing processor is configured to create an active image having a current state of the routing information and create a standby image having the current state of the routing information, wherein the standby image requests the current state of the routing information from the active image using a key that is calculated using a portion of the routing information.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: DELL PRODUCTS, L.P.
    Inventors: Vinay SAWAL, Swaminathan SUNDARARAMAN
  • Publication number: 20130287039
    Abstract: An Ethernet switch for use in an Ethernet network comprises a set of ingress ports for receiving data frames and a set of egress ports. A memory is associated with each ingress port and stores forwarding information indicating one or more of the egress ports to which data frames received by that ingress port should be forwarded. A control or management interface receives information about a network connection established, or to be established, through the switch. A switch controller causes forwarding information to be stored in a memory associated with a first ingress port which the network connection will use, on the basis of the received information about a network connection. Forwarding information is not stored in a memory associated with a second of the set of ingress ports which the network connection will not use.
    Type: Application
    Filed: June 24, 2013
    Publication date: October 31, 2013
    Inventors: Nigel BRAGG, Michael CHEN, John OSSWALD, Mirza ARIFOVIC
  • Publication number: 20130287031
    Abstract: Embodiments of the present invention disclose a method, an apparatus, and a system for forwarding data in a communications system. The implementation of the method includes: A data forwarding device forwards a data packet from a source end to a destination end by using a low-speed channel; during a procedure for forwarding the data packet from the source end to the destination end by using the low-speed channel, the data forwarding device receives a control command sent by a service processing node, where the control command is used to indicate that the data packet of the source end does not need to be forwarded to the service processing node; and the data forwarding device forwards the data packet from the source end to the destination end according to the indication of the control command by using a high-speed channel.
    Type: Application
    Filed: June 27, 2013
    Publication date: October 31, 2013
    Inventor: Xinyu GE
  • Patent number: 8571052
    Abstract: A Fibre Channel over Ethernet (FCoE) device obtains knowledge of the configuration of an attached Ethernet fabric during a fabric initialization or login (FLOGI) process. FCoE N_Ports obtain similar information during the port initialization or login (PLOGI) process. The FCoE device may provide network management services to attached FCoE devices. Embodiments include a management module or processor within an FCoE N_Port. The management module or processor receives information associated with an Ethernet fabric from the FCoE N_Ports and provides management services based on the information associated with the Ethernet fabric. The FCoE N_Port communicatively couples to at least one additional FCoE N_Port through the Ethernet fabric. The FCoE N_Ports may be implemented within a disc storage drive, a host bus adapter, and/or an FCoE switch. The capability of an N_Port to obtain this information allows a management module or processor at the N_Port to manage the Ethernet fabric.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Scott M. Carlson, Daniel G. Eisenhauer, Roger G. Hathorn, Jeffrey W. Palm, Sandy K. Kao, Renato J. Recio
  • Patent number: 8571024
    Abstract: An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: October 29, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Mohammed I. Tatar, Garry P. Epps, Oded Trainin, Eyal Oren, Cedrik Begin
  • Patent number: 8565251
    Abstract: In accordance with embodiments of the present disclosure, a switch may include a processor and a plurality of line cards, each line card including a table of addresses. The processor may be configured to: (i) read, from a first line card of the plurality of line cards, addresses relating to all flooding domains present on the first line card; (ii) store the addresses read from the first line card on a memory accessible to the processor; (iii) determine a second line card of the plurality of line cards, the second line card having the presence of at least one flooding domain not present on the first line card; (iv) read, from the second line card, addresses relating to all flooding domains present on the second line card; and (v) store the addresses read from the second line card on the memory.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: October 22, 2013
    Assignee: Fujitsu Limited
    Inventors: Bijendra Singh, Arun Saha, Arindam Paul
  • Patent number: 8565085
    Abstract: A disclosed method and device relate to defining a link aggregation group (LAG) media access control (MAC) address and assigning the LAG MAC address to two or more links to define a LAG. The LAG MAC address does not duplicate physical MAC addresses associated with the links in the LAG. Datagrams associated with the links in the LAG are routed based on the LAG MAC address.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: October 22, 2013
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Scott R. Kotrla, Howard H. Chiu, Donald Pitchforth, Jr., Michael U. Bencheck, Richard C. Schell, Matthew W. Turlington, Glenn Wellbrock, James D. Lee
  • Patent number: 8565261
    Abstract: A system including a media access controller, a rate adaptation layer (RAL), and a physical extension module. The RAL module is configured to communicate with the media access controller using a plurality of signal interconnections. The physical extension module is configured to (i) communicate with the RAL module using XGMII, and (ii) communicate with an external device using a physical extension interface. The RAL module is configured to store (i) a first mapping of 10 Gbps media independent interface (XGMII) signals onto a first subset of the plurality of signal interconnections, and (ii) a second mapping of 1 Gbps media independent interface (GMII) signals onto a second subset of the plurality of signal interconnections. The RAL module is also configured to choose a selected mapping from the first mapping and the second mapping, and communicate with the media access controller over the plurality of signal interconnections according to the selected mapping.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: October 22, 2013
    Assignee: Marvell International Ltd.
    Inventor: William Lo
  • Publication number: 20130272312
    Abstract: A local oscillator circuit and a corresponding method are provided. The local oscillator circuit includes a memory connected to a processor. The memory is configured to store local oscillator parameters corresponding to a plurality of center frequencies of a frequency spectrum. The processor is configured to apply the stored LO parameters when switching the frequency spectrum for a mixed-mode spectrum communication. The local oscillator also includes a plurality of registers connected with the processor, the plurality of registers configured to control switching of the frequency spectrum.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 17, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Moshe Tarrab, Ramon A. Gomez, Avi Kliger, Young Joon Shin, Dongsoo Daniel Koh
  • Publication number: 20130272313
    Abstract: Provided are a computer program product, system, and method for updating zone information in a distributed switch of data forwarders. For each data forwarder, a sequence number is maintained for zone distribution messages sent to the data forwarder. A change to the ports in the network is detected comprising at least one of an allocation or deallocation of at least one port in the network. The sequence number for each data forwarder is incremented in response to detecting the change. For each data forwarder, a zone distribution message is generated indicating the at least one port allocated and/or deallocated, port information indicating each port in the network that may communicate with each other port, and the sequence number for the data forwarder. The generated zone distribution message is transmitted for each data forwarder to the data forwarder for which the zone distribution message was added.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger G. Hathorn, Sriharsha Jayanarayana, Henry J. May, Stefan Roscher, Bharath B. Somayaji, Sudheer R. Yelanduru
  • Patent number: 8559453
    Abstract: A routing apparatus couples to another routing apparatus using a trunk formed by a plurality of channels, and has a plurality of input and output cards to input and output frames. Each input and output card includes a management table registering a transmitting source address, destination information, and a trunk attribute indicating whether a channel used for a transmission has a trunk structure, a learning request part searching the management table using a transmitting source address within a frame that is transmitted via the channel, and generating and supplying learning request information having information that is obtained by searching the management table to another input and output card, if the channel used for the transmission has the trunk structure, and a registering part registering learning request information supplied thereto in the management table.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: October 15, 2013
    Assignee: Fujitsu Limited
    Inventors: Michio Kuramoto, Kanta Yamamoto, Yasuyuki Mitsumori
  • Patent number: 8559422
    Abstract: A network for coupling at least one telephone service signal to at least one telephone device over a wiring. The network includes: a wiring having at least two conductors for carrying multiple time-domain multiplexed digitized voice channels; an exchange side device coupled to the wiring and operative to couple at least one telephone service signal to at least one digitized voice channel; and at least one subscriber side device coupled to the wiring and operative to couple the at least one telephone device to at least one digitized voice channel.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: October 15, 2013
    Assignee: Mosaid Technologies Incorporated
    Inventor: Yehuda Binder
  • Publication number: 20130259063
    Abstract: In a method for dynamic buffer adjustment at a line card of router, a current buffer occupancy at the line card is compared with at least a first buffer occupancy threshold, the first buffer occupancy threshold being calculated based on a buffer occupancy threshold parameter and a capacity of at least a first buffer memory at the line card; and an active buffer capacity is adjusted by at least one of activating and deactivating buffer memory blocks at the line card based on the comparing step, the activating including switching on the buffer memory blocks, and the deactivating including causing the buffer memory blocks to enter a sleep state.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicants: ALCATEL-LUCENT USA INC., ALCATEL-LUCENT
    Inventors: Marina Thottan, Arun Vishwanath, Vijay Sivaraman, David Neilson
  • Publication number: 20130259064
    Abstract: A network device includes an input circuit configured to receive a plurality of data streams. An output circuit is configured to transmit the plurality of data streams. A forwarding engine includes a plurality of different types of resources associated with transmission of the plurality of data streams and is configured to transfer data streams from the input circuit to the output circuit according to the plurality of different types of resources. A resource manager is configured to determine performance requirements for each of the plurality of data streams, determine whether the performance requirements for each of the plurality of data streams can be accepted, store data entries corresponding to the performance requirements in response to a determination that the performance requirements can be accepted, and program, for each of the plurality of data streams, the plurality of different types of resources based on the data entries.
    Type: Application
    Filed: May 30, 2013
    Publication date: October 3, 2013
    Inventor: Raghu Kondapalli
  • Patent number: 8547985
    Abstract: The disclosure is a network interface controller (NIC) capable of sharing buffers, which is coupled to a host and a network to make the network connection. The NIC includes a transmitting buffer, a transmitting controller, a receiving buffer, and a receiving controller. The transmitting controller controls the transmitting buffer to transmit the transmission data provided by the host to the network. The receiving controller controls the receiving buffer to transmit the reception data received from the network to the host, and determines a storage capacity of the receiving buffer. When the storage capacity is smaller than a set value, the receiving controller transmits a request signal to the transmitting controller, the transmitting controller generates a response signal according to the request signal and a status signal corresponding to the transmitting buffer, and the receiving controller controls whether reception data is stored in the transmitting buffer according to the response signal.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: October 1, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kuo-Nan Yang, Yen-Hsu Shih, Chia-Ying Chiu, Kai-Wen Cheng
  • Patent number: 8547963
    Abstract: An internet phone integrating system includes a PC, a VoIP phone, a softphone, an HID signal-transmitting unit, and a media transmitting unit. The VoIP phone provides an HID inputting signal. The softphone provides an HID outputting signal and a media controlling signal and decodes an audio coding streaming to a media data flow. The HID signal-transmitting unit receives the HID outputting signal from the softphone and sends the HID outputting signal to the VoIP phone, and receives the HID inputting signal from the VoIP phone and sends the HID inputting signal to the softphone. The media transmitting unit receives the media controlling signal and media data flow from the softphone and sends the media controlling signal and media data flow to the VoIP phone, and receives the media data flow from the VoIP phone and sends the media data flow to the softphone.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: October 1, 2013
    Assignee: Wistron Corp.
    Inventor: Shu-Yi Lin
  • Patent number: 8545246
    Abstract: An apparatus, in accordance with particular embodiments, includes a shell comprising two substantially parallel surfaces. The apparatus further includes a plurality of connector housings mounted between the two substantially parallel surfaces. The apparatus also includes a plurality of connectors coupled to the plurality of connector housings. Each connector is configured to move along at least one axis within its respective connector housing. The apparatus further includes a plurality of cables. Each cable is configured to couple together at least two connectors. The plurality of cables are arranged between the two substantially parallel surfaces.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 1, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Gary L. Myers, Kamran Esmaily, Upendranadh Reddy Kareti, Phillip S. Ting
  • Patent number: 8547995
    Abstract: Both the transmitter unit VTB and the receiver unit VRB feature a modular structure consisting of a base module or baseboard common to both units and one or more exchangeable adapter cards attached to or inserted into the baseboards to perform selected functions. The basebord is unitary; its components are activated depending upon the baseboard being in a VTB or a VRB. Each card is unique and earmarked and serves a specific purpose, e.g. for video coding and decoding, SMPTE processing, clocking/re-clocking, audio embedding/extraction. Upon inserting a card into a baseboard, the earmark is identified and the baseboard configured as transmitter or receiver baseboard. Functions in the baseboard can be implemented in Field Programmable Gate Arrays (FPGAs) and the network management, configuration, and/or control of the transmitting and/or receiving processes be performed by a softcore processors.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 1, 2013
    Assignee: Barox Kommunikation AG
    Inventors: Hans-Joachim Gelke, Angelo Banfi, Rudolf Rohr
  • Patent number: 8547993
    Abstract: Methods, apparatuses, and systems are presented for performing asynchronous communications involving using an asynchronous interface to send signals between a source device and a plurality of client devices, the source device and the plurality of client devices being part of a processing unit capable of performing graphics operations, the source device being coupled to the plurality of client devices using the asynchronous interface, wherein the asynchronous interface includes at least one request signal, at least one address signal, at least one acknowledge signal, and at least one data signal, and wherein the asynchronous interface operates in accordance with at least one programmable timing characteristic associated with the source device.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: October 1, 2013
    Assignee: NVIDIA Corporation
    Inventors: Lincoln G. Garlick, Richard A. Silkebakken, Prakash G. Apte, Paolo E. Sabella, Samuel H. Duncan, Dennis K. Ma, Sean J. Treichler
  • Patent number: 8542689
    Abstract: A method and device for local area network (LAN) emulation over an Infiniband (IB) fabric. An IB LAN driver at a first node on an IB fabric receives the port and associated local identifier (LID) of one or more remote peer nodes on the IB fabric. An IEEE 802.3 Ethernet MAC address with one LID imbedded is generated. The imbedded LID is for one or more remote peer nodes. The IB LAN driver sends the Ethernet MAC address to an Address Resolution Protocol (ARP). A logical address of a remote peer node is generated by a network protocol. The logical address is mapped to an Ethernet MAC address. The IB LAN driver sends the Ethernet MAC address onto the IB fabric to the one or more remote peer nodes. The remote peer nodes appear to reside on an Ethernet network to the network protocol.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: September 24, 2013
    Assignee: Intel Corporation
    Inventor: Arlin R. Davis
  • Publication number: 20130242999
    Abstract: According to one embodiment, a method for providing scalable virtual appliance cloud (SVAC) services includes receiving incoming data traffic having multiple packets directed toward a SVAC using at least one switching distributed line card (DLC), determining that a packet satisfies a condition of an access control list (ACL), designating a destination port to send the packet based on the condition of the ACL being satisfied, fragmenting the packet into cells, wherein the designated destination port is stored in a cell header of the cells, sending the cells to the destination port via at least one switch fabric controller (SFC), receiving the cells at a fabric interface of an appliance DLC, reassembling the cells into a second packet, performing one or more services on the second packet using the appliance DLC, and sending the second packet to its intended port.
    Type: Application
    Filed: May 30, 2012
    Publication date: September 19, 2013
    Applicant: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Dar-Ren Leu, Nilanjan Mukherjee, Vijoy A. Pandey
  • Patent number: 8537856
    Abstract: Briefly, in accordance with one embodiment of the invention, a wireless terminal may include an application subsystem and a communication subsystem. The communication subsystem in one embodiment may enable a virtual direct interface to a remote network to be presented to the application subsystem via a wireless communication system air link interface. The communication subsystem may allow applications of the application subsystem to be independent of any particular radio technology or network implementation of a wireless communication system air link interface. Once a session is established between the communication subsystem and the wireless communication system air link interface, the application subsystem may gain access to the remote network through the communication subsystem via a transport interface.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventor: Matthew A. Hayduk
  • Patent number: 8537849
    Abstract: A channel in a telemetry system is described. The channel includes a sample-and-hold circuit, a variable resistor circuit, and a control element. The sample-and-hold circuit is configured to hold a sample of a signal. The variable resistor circuit is communicatively coupled to the sample-and-hold circuit, and is configured to present a variable impedance to one or more signal lines during a time period designated for the channel. The variable impedance is representative of the sample held by the sample-and-hold circuit. The control element is configured to control the variable resistor circuit to present to the one or more signal lines an open circuit equivalent impedance during times other than the time period designated for the channel.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: September 17, 2013
    Assignee: General Dynamics Advanced Information Systems, Inc.
    Inventor: Michael D. Holt
  • Patent number: 8537696
    Abstract: A system and method are presented for changing physical layer (PHY) parameters in a PHY device of a communications system. New parameters are written to a first-in first-out queue in a serial interface, while the scheduled time for the changeover is written to a control register in the serial interface. When the time for the changeover occurs, the parameters are written to the PHY device via a port of the serial interface.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: September 17, 2013
    Assignee: Broadcom Corporation
    Inventors: A. Scott Hollums, Niki R. Pantelias, David A. Ferguson
  • Patent number: 8537847
    Abstract: A wedge-shaped digital clock wirelessly receives weather, traffic, and other information over the Internet for display along with the time of day. The clock is wedge-shaped so that it can rest in two orientations, one with the display tilted back slightly from vertical and one with the display substantially horizontal. An accelerometer can signal the orientation to an internal processor, which can flip the text on the display as appropriate for the user flipping or turning the housing upside down, for example.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: September 17, 2013
    Assignee: Sony Corporation
    Inventors: Hiroya Fujii, Isamu Arie, Ronald Clark, Justin Randolf Jakobson, Yuji Oikawa, Joe Wada, Rui Yamagami, Takuo Ikeda, Chia-Yao Lin, Junghee Yeo
  • Patent number: 8537848
    Abstract: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventors: Michael Klinglesmith, Mohan Nair, Joseph Murray
  • Publication number: 20130235881
    Abstract: A system includes a forwarding instance that is configured to receive a packet from a source on a port that is a member port of an etherchannel bundle. The forwarding instance is configured to update a table with information that correlates the source with the port. The forwarding instance is also configured to send a synchronization packet to other forwarding instances having ports that are member ports of the etherchannel bundle. Upon receipt of the synchronization packet, the other forwarding instances are configured to update tables with the information that correlates the source with the port.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Applicant: Cisco Technology, Inc.
    Inventor: Rajan Sharma
  • Patent number: 8532121
    Abstract: End-point devices, access points and other types of network nodes each employ multi-path management software to manage communication via multiple possible paths to the Internet backbone from communication applications that run on an end-point device. Although the multi-path management software on an end-point device may operate independently, it may also cooperate with the local communication applications and the multi-path management software located on the access points or other network nodes to select one or more pathways for the local communication applications. Alternatively, the multi-path management software of an end-point device may pass all or a portion of such management responsibility to a local communication application and/or to multi-path management software of another network node. In addition to managing the selection of one or more pathways, the multi-path management software seamlessly switches pathways as may become necessary to meet changing network conditions or bandwidth demands.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: September 10, 2013
    Assignee: Broadcom Corporation
    Inventor: James D. Bennett
  • Patent number: 8532114
    Abstract: A cluster router includes at least one control apparatus and at least two forwarding apparatuses. The control apparatus is connected to the forwarding apparatuses, and the forwarding apparatuses are connected with each other. The control apparatus is configured to generate a routing table of each forwarding apparatus and a packet processing information conversion table of each forwarding apparatus. The forwarding apparatus is configured to receive the routing table of the forwarding apparatus and the packet processing information conversion table of the forwarding apparatus, and execute data exchange between the forwarding apparatuses according to the routing table and the packet processing information conversion table.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: September 10, 2013
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Enhui Liu, Zhanfeng Wang, Qingzhi Liu
  • Patent number: 8532131
    Abstract: There is provided the multirate communication apparatus including: an interface board to connect with a plurality of lines of different bit rates and processing transmission signals of the lines having a first line capacity; a port to mount a transmission module to transmit and receive the transmission signals; a line identifying unit to identify a line type of the transmission module mounted in the port; a plurality of signal processor to process transmission signals having a second line capacity obtained by dividing the first line capacity by a predetermined number; and a line-configuration controller to control a configuration of lines processed in respective the signal processor, based on an identification result of the line identifying unit; wherein the signal processor processes the transmission signals in accordance with the line type of the transmission module mounted in the port, base on a control by the line-configuration controller.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: September 10, 2013
    Assignee: Fujitsu Limited
    Inventor: Takashi Honda
  • Patent number: 8531985
    Abstract: A network device includes port interfaces and a traffic buffer configured with queue sets for buffering packets transmitted or received on the port interfaces. The network device also includes a management module that stores one or more queue set profiles. The queue set profiles specify configuration parameters for buffering and managing traffic in the queue sets. To configure a queue set, one of the queue set profiles is associated with the corresponding port interface and the configuration parameters are applied to the queue set. This queue set is then configured in accordance with the queue set profile. Management of port interfaces is thus performed by applying a queue set profile to similar groups of queue sets.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: September 10, 2013
    Assignee: Alcatel Lucent
    Inventors: Prashant R. Rao, Phil S. Ghang, Ronald Francis Pardy, Lawrence S. Lavenberg
  • Patent number: 8531286
    Abstract: A security system includes at least one audio sensor and an alarm panel that transmits alarm report data through a communications network to at least one alarm receiver located at a central station remote from the premises that receives the alarm report data transmitted from the alarm panel through the communications network. A line card receives the alarm report data. An alarm receiver processor receives and processes regulated alarm report data in accordance with Underwriter Laboratories 1610 requirements. The line card is operable for receiving non-regulated alarm report data that is not regulated in accordance with Underwriter Laboratories 1610 requirements. The line card includes a secondary communications channel interfaced to a central station automation system and routes the regulated alarm report data to the central station automation system over the secondary communications channel and bypasses the alarm receiver processor.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: September 10, 2013
    Assignee: Stanley Convergent Security Solutions, Inc.
    Inventors: Gary Friar, Mark Davis
  • Patent number: 8526424
    Abstract: An improved telephony adapter compresses voice data, creates IP packets, and prioritizes the voice IP packets over the data IP packets. Preferably, the compression and packetization interval is such that the bandwidth occupied by the voice IP packets is approximately half of the minimum average available bandwidth in the upstream direction, thereby maintaining acceptable latency and voice quality of the speech. Further enhancement is achieved by causing the ISP to also give priority to voice packets that are destined to the telephony adapter, over the data packets that are destined to the telephony adapter.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: September 3, 2013
    Assignee: AT&T Intellectual Property II, L.P.
    Inventors: Ali M. Cherchali, Marius Jonas Gudelis, William G. Lester, Robert J. McLaughlin