Abstract: A system for path finding and terrain analysis. The system includes at least one processing unit, a graph processing unit and an artificial intelligence logic unit. A local bus is coupled to the at least one processing unit, the graph processing unit, the artificial intelligence unit and a bus interface unit. A memory bus is coupled to said bus interface unit, the at least one processing unit, a data memory, and a program memory. The graph processing unit further includes a network of interconnected nodes. Each of said nodes have at least one digitally programmable delay unit.

Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. It also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. An output terminal is configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements.

Abstract: A cable modem for connecting Customer Premises Equipment (CPE) includes a Media Access Control (MAC) layer controller, a Logical Link Control (LLC) bridge (113) interacting with the MAC layer controller, an IP stack processing IP frames and interacting with the LLC bridge (113), CPE interfaces (115, 116 and 117) and a multiplexer (114) of Customer Premises Equipment (CPE) interfaces linked to the CPE interfaces and to the LLC bridge (113). The CPE interfaces (115, 116 and 117) communicate with the multiplexer (114) through appropriate functions. The multiplexer (114) has functionality allowing for servicing the flow of frames between the cable network and the interfaces linked to it, directing the received frames to appropriate interfaces.

Abstract: For transporting data packets of a data stream between a packet-oriented network (LAN) and a channel-oriented data stream processing module (VMOD), a data stream controller (ST) is provided which, via a data channel allocation module (VMUX), accesses an interface module (PS) for exchanging the data packets with the network (LAN) and/or accesses the data stream processing module (VMOD). The data stream controller (ST) transmits a data channel allocation information item (DKl1, DKl2) to the interface module (PS) and/or to the data stream processing module (VMOD). Using a data channel allocation information item (DKl1, DKl2) in each case transmitted, the data packets are transmitted directly between the interface module (PS) and the data stream processing module (VMOD), bypassing the data channel allocation module (VMUX).

Abstract: In a communication system comprising a link layer device connectable to one or more physical layer devices, at least a given one of a plurality of ports of the one or more physical layer devices is designated as a port for which status information is to be requested by the link layer device on a more frequent basis than such information is to be requested for one or more other ports of the plurality of ports. The ports are then polled by the link layer device in accordance with a non-linear polling sequence such that the at least one designated port is polled more frequently than the one or more other ports. The designated port may comprise a port to which the link layer device transmits data in conjunction with a current data transfer. The non-linear polling sequence may thus be altered dynamically based on particular data transfers that are occurring between a link layer device and a physical layer device in a communication system.

Abstract: A method of data interchange within one or a network of microcomputers, wherein the microcomputers each have plural devices engaged for communication over a bus structure, the method including the steps of installing a TCP/IP protocol instruction set in each of the devices and in an operating system of each of the microcomputers in the network, and directing data transfers between the devices of all of the microcomputers over the bus structures of all of the microcomputers using packet switching protocol, thereby enabling said data transfers to be made within each of the microcomputers and between the microcomputers.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A switch schedules guaranteed-bandwidth, low-jitter-traffic characterized by a guaranteed rate table (GRT) method. A rate matrix generated from collected provisioning information is decomposed into schedule tables by a low jitter (LJ) decomposition method. The LJ decomposition method imposes a set of constraints for the schedule tables: schedule tables are partial permutation matrices, weighted sum of the partial permutation matrices is greater than or equal to the weighted sum of the rate matrix, and each entry in the rate matrix belongs to one element of the LJ decomposition schedule matrices. An integer LJ decomposition programming problem is employed to generate the schedule tables that are scheduled for each time slot of the period of the switch. Schedule tables are selected in turn based upon selecting eligible tables having the earliest finishing time. If necessary, the rate matrix is updated prior to decomposition for a subsequent period.

Abstract: A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adapted to select signals from the plurality of devices. A second multiplexer circuit may receive the selected signals from the first multiplexer circuit and transmit the selected signals to chosen ones of the plurality of devices.

Abstract: An apparatus is described that includes a plurality of queuing paths. Each of the queuing paths further comprises an input queue, an intermediate queue and an output queue. The input queue has an output coupled to an input of the intermediate queue and the input of the output queue. The intermediate queue has an output coupled to the input of the output queue. The intermediate queue receives data units from the input queue if a state of the input queue has reached a threshold. The output queue receives data units from the intermediate queue if the intermediate queue has data units. The output queue receives data units from the input queue if the intermediate queue does not have data units.

Abstract: The communication system includes multiple participating devices connected with each other by a data line. At least one connection device for connection to a corresponding participant device defined as associated with it is connected to the data line. The communication system is preferably an IP network and with respective connection devices defined as associated with corresponding participating devices, which are used to connect portable operating and display terminals with the participating devices. For definite identification of the corresponding participating device associated with the respective connection devices, the connection devices include readable means of identifying the corresponding participating device, e.g. including a stored IP address, which is readable by the connected interface device, i.e. the terminal.

Abstract: A system for servicing packet data transactions and input/output transactions includes an input port, an output port, a node controller, a packet manager, and a switching module. The input port is receives communications from a communicatively coupled processing device that include packet data transactions and input/output transactions. The output port transmits communications to a communicatively coupled processing device that include packet data transactions and input/output transactions. The node controller communicatively couples to a system bus of the processing device and services input/output transactions. The packet manager communicatively couples to the system bus of the processing device and services packet data transactions. A switching module communicatively couples to the input port, the output port, the node controller, and the packet manager and services the exchange of transaction cells among the input port, the output port, the node controller, and the packet manager.

Abstract: A broadband packet switch that handles all packets that arrive within the same frame time by simultaneously bit-pipelining the packets into different sections of the one-stop packet buffer through an input switch. Each packet remains in is selected section until its eventual exit from the buffer through an output switch. Access to the memory storage in which the packet buffer resides is not through a memory bus or buses, thereby engendering massive parallel access.

Abstract: In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of flow control and extended burst transfers are described.

Abstract: A system for servicing data transactions within a processing device using common data paths. The system is broadly comprised of: a plurality of source agents operable to transmit a plurality of data cells; a plurality of destination agents operable to of data cells; a plurality of virtual channels for transporting data cells between the source agents and the destination agents; and a switch. The switch is operable to connect predetermined combinations of the source agents and the destination agents for the transmission of data. The switch generates a plurality of switch processing cycles and processes a plurality of control signals during the switch processing cycles.

Abstract: The invention concerns the transmission of data packets in multicast mode, in which method the packets are sent from a sending end of a physical transmission medium and received by terminals at a receiving end of said medium. It finds a typical application in networks whose terminals cannot listen to each other, which is the case in satellite networks, for example, whereas management implies sending a query message to the terminals in order to determine the presence of an active group of terminals as a function of the reception of a response message from a terminal of said group. A signal is then sent to the terminals from the sending end, preferably the returned response, to indicate reception of a response message from a terminal of the group of terminals, so that terminals that have not sent a response message can act accordingly, in particular by interrupting their own process for sending a response.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: The present invention relates to a method and arrangement for controlling dataflow on a databus, especially for avoiding reception problems by a receiver unit. The databus connects at least one receiver unit to one or several transmitter units. The method comprises the steps of transmitting by the receiver unit on the databus a control data sequence to be received by the transmitting units, which alter transmission mode.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circuits each for controlling a command processing sequence performed with the corresponding device; a multi-control circuit for giving sequence execution permission to one of the plurality of command control circuits; and a packet processing circuit for generating a packet containing information output by the permission-given command control circuit and outputting the packet for transmission, and also outputting a received packet according to the analysis results output by the packet filter.

Abstract: A method and apparatus for processing data packets including generating an enqueue command specifying a queue descriptor associated with a new buffer. The queue descriptor is part of a cache of queue descriptors each having a head pointer pointing to a first buffer in a queue of buffers, and a tail pointer pointing to a last buffer in the queue. The first buffer having a buffer pointer pointing to next buffer in the queue. The buffer pointer associated with the last buffer and the tail pointer is set to point to the new buffer.

Abstract: A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers to hold the portion of the data packets exchanged with the corresponding medium access controller. Each data path controller has a selector that selects the buffer from which to exchange the portion of the data packets with the central shared memory and control logic that controls the selector to concurrently select the buffer corresponding to the same medium access controller.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: An information processing apparatus includes a CPU and a memory connected to an internal local bus, and includes a data transmission/reception unit transmitting and receiving data to and from a public network, a voice encoding/decoding unit encoding and decoding voice data, an image encoding/decoding unit encoding and decoding image data, an external input/output interface controller controlling an input/output interface with an external unit, and an input/output switching unit selectively forming a data bus among the data transmission/reception unit, the voice encoding/decoding unit, the image encoding/decoding unit and the external input/output interface controller.

Abstract: An apparatus and method for managing reliable datagram work queues, and associated completion queues, using head and tail pointers with end-to-end context error cache are provided. Reliable datagram (RD) queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a RD queue page table index and a RD queue page index for identifying a position within the RD queue. For RD work queues, in the channel interface, the tail pointer is used to identify a next position where a work queue entry may be written and the head pointer is used only to determine whether the work queue is full. In the host channel adapter, the head pointer is used to identify a next work queue entry for processing and the tail pointer is used to determine if the queue is empty.

Abstract: A data network provides independent transmission channels for transmitting high bandwidth and low latency information data packets between nodes. The data information packets are organized into at least two groups of data packets according to predetermined criteria. The predetermined criteria includes a latency budget of the data packets, the size of the data packets and the type of operation. The low latency channel is also coupled to transmit control information relating to network protocol.

Abstract: A first frame of carrier data can be communicated between a first carrier interface of a first radio base station node and a mobile switching center over a first carrier bus. In addition, a first frame of bus data can be communicated having a first number of dedicated control timeslots at a first bus interface of the first radio base station node over a first radio base station bus. Furthermore, a second frame of carrier data can be communicated between a second carrier interface of a second radio base station node and the mobile switching center over a second carrier bus. Finally, a second frame of bus data having a second number of dedicated control timeslots, different from the first number of dedicated control timeslots, can be communicated at a second bus interface of the second radio base station node over a second radio base station bus.

Abstract: A method for operation of a distributed computer system (SYS) comprising network nodes (NKN, NK1–NK6), each of which has at least one node controller (STR, ST1–ST6) and one communication controller (KK1–KK6), the communication controllers (KKK, KK1–KK6) being connected to each other via at least one communication channel (BUS), and provision being made between the communication controller (KK1–KK6) and the node controller (STR, ST1–ST6) of a network node (NKN, NK1–NK6) for a fault tolerance layer (FTS, FT1–FT6) that is set up to receive messages exchanged between the network nodes (NKN, NK1–NK6), the fault tolerance layer (FTS, FT1–FT6) deciding, based on information received pertaining to the status of at least one network node(NKN, NK1–NK6), about the functioning of the at least one network node (NK1–NK6) via a coordination procedure, and the coordination result being made available as an output signal (ASS, AS1–AS6), the at least one network node (NKN, NK1–NK6) being triggered as a function of the output s

Abstract: A method of processing packets in a switch. A first queue is selected from at least three queues based on the cycle number (C) of a cycle and flushed at the start of cycle C. At least one isochronous packet is received over a bus during the cycle. The packet is placed in a second queue based on the cycle number.

Abstract: The Spanning Tree Protocol (STP) chooses a root switch. Each of the other switches has a “root” port and one or more “designated ports(s)” chosen by STP. Packets are transmitted upstream toward the root switch through the root port, and packets designated for downstream switches from the root switch are received by the root port and transmitted through the designated ports. In the invention, an administrator of the core network identifies which switch ports in the core network are boundary ports to customer networks. The administrator designates the boundary ports as “root guard protected” ports (RG ports). The STP then executes as required by the ordinary STP protocol, and if a RG port is selected by the STP to be a root portm then the status of the port is set to “blocked,” and no packets are transmitted through the port.

Abstract: An information transport system includes a switching fabric that transfers information between network modules and between a host processor and the network modules. The switching fabric includes network module interfaces each associated with one or more network modules. The network module interfaces communicate with each other over a peer transaction bus to allow information to be transferred from one network module to another network module. The switching fabric also includes a processor interface associated with the host processor. The processor interface communicates with the network module interfaces over a host transaction bus to allow information transfer between the host processor and each network module. The peer transaction bus and the host transaction bus separately support routed packet data and peer to peer data transactions in order to prevent one type of transaction from blocking the other and avoid performance dependencies.

Abstract: A method and apparatus for digital subscriber line (xDSL) communications between one or more digital signal processors (DSPs) and analog front ends (AFEs) each coupled to corresponding subscriber line(s). The apparatus transports channels of data between subscribers and the DSP(s). The apparatus includes a bus for the transport of digital data, a DSP AFE interfaces. The DSP interfaces couples the DSP to the bus. The DSP interface accepts downstream channels of digital data from the DSP and transmits packets each associated with a corresponding one of the downstream channels to the bus. Each of the packets identifies a targeted AFEs coupled to a selected one of the subscriber lines. The AFE interfaces each couple an associated one of the AFEs to the bus. Each of the AFE interfaces transmits selected packets to a selected one of the subscriber lines for the transport to the subscriber.

Abstract: A timing output panel may include a rear portion and a front portion. The rear portion may include a number of network connectors respectively configured to connect to a number of network elements, and at least one timing connector connected to the number of network connectors and configured to connect to synchronization electronics. The front portion may include a number of equipment jacks corresponding to and electrically connected to the number of network connectors. The equipment jacks may facilitate temporary connection of cables for testing or patching signals to the network elements. The front portion also may include a number of timing jacks corresponding to and electrically connected to the at least one timing connector. The timing jacks may facilitate temporary connection of cables for testing the synchronization electronics or patching to the equipment jacks.

Abstract: The objective is to provide a data transfer control device and electronic equipment that are capable of reducing processing overheads, thus enabling high-speed data transfer within a compact hardware configuration. In a data transfer control device in accordance with IEEE 1394, a packet shaping circuit (160) shapes each packet that is transferred in from another node into a form that can be used by an upper layer, and a packet division circuit (180) writes the header of the thus-shaped packet into a header area in RAM and the data thereof into a data area. A data pointer that has been passed from the packet division circuit is appended to the header of the packet during packet shaping. Tags are used to divide packets. Information indicating broadcast information, error status information, and whether or not the packet was received during a self-ID period is appended to the trailer of the packet during the packet shaping.

Abstract: Methods and apparatus used in systems for communicating data (e.g., voice, video and alphanumeric data), including but not limited to telecommunications systems, computer systems, to efficiently utilize bandwidth by performing bit sensitive peer addressing. Apparatus (and related methods) for performing bit sensitive peer addressing include a parallel bus of data bits, a clock bit, a bid/busy bit, and an ack bit. The invention further includes a plurality of port devices coupled to the bus. Each port device includes bus interface circuitry, port control circuitry, and line interface circuitry. The clock signal is used to synchronize messages on the bus and to divide the time domain into timeslots (one timeslot being the reciprocal of the clock frequency). According to the invention, no frame reference is used and traffic on the bus is controlled using a protocol. Each port has an address which is one of the data bits of the bus.

Abstract: A communications system connected via a bus capable of transferring combinations of control signals and AV signals as packets while providing an environment which is the same as an environment where connections are made using analog signal lines. A register decided by an address is taken to be a virtual plug for each item of equipment. The plug enable for the input plug is set to 1 and a synchronous communication packet for the AV signal from the channel set by the channel number is received. The plug enable for the output plug is set to one and the synchronous communication packet for the information signal is sent to the channel set by the channel number at a transmission speed designated by the DR (Data Rate) at the bandwidth expressed by “Bandwidth”.

Abstract: A technique enables learning and switching of frames between line cards that are interconnected by a switch fabric of a distributed network switch. The network switch comprises a router and a plurality of forwarding engines, each having an associated forwarding table.

Abstract: A central route table design in a fiber channel switch for providing one location for D_ID and exit port combinations. The fiber channel switch has a plurality of ports, each are coupled to the central route look-up table.

Abstract: A method and apparatus are described for interfacing between a network interface and a bus. For the network interface-to-bus side, the method comprises (a) forming a network address of a message transferred via the network interface to the bus, and (b) mapping the network address to a bus address of the bus, the bus address being within an address space occupied by a bus device coupled to the bus. For the bus-to-network interface side, the method comprises (a) forming a bus index from a bus address of the bus where the bus address is within an address space occupied by a bus device coupled to the bus; and (b) mapping the bus index to a network address of a message transferred via the network interface to the bus.

Abstract: A network device includes a content addressable memory (CAM). The CAM may be accessed by a host processor. The host processor stores active device addresses in the CAM. Each device address is associated with one of the network switch ports. If the network switch receives a packet having a source address not presently stored in the CAM, the network switch adds the source address to the CAM. If the CAM is full of source addresses, the new source address replaces a selected one of the old source addresses.

Abstract: An improvement to the protocols used communication devices in data networks that require loop-free forwarding of data frames provides for rapid use of shared media links after changes in physical connectivity, for rapidly detecting the edge of the network so as to reduce interruptions of service by mechanisms that protect against loops, for preventing loops caused by one way connectivity, such as can occur if transmitter or receivers are broken or poorly connected to links, and for preventing loops caused by loop back. The improvement is applicable to the Bridged Local Area Networks and the spanning tree protocols specified in IEEE Standards 802.1D and 802.1Q and their amendments and revisions.

Abstract: A crossbar bus network of nodes is coupled to a crossbar switch circuit that operates as a communications hub routing messages simultaneously to and from the nodes over multiple links. The crossbar switch circuit includes a dedicated communications bus ring adapted to transmit data such as programmed input/output (PIO) messages between components of said crossbar switch circuit. The communications bus ring can be used for secondary high latency data communications thereby freeing switching matrix links of the crossbar switch circuit for simultaneous unimpeaded important low latency data communications to the same device.

Abstract: A switching system includes switches, each having a host processing unit and a switching unit, and a backbone link configured for transferring data packets between the switching units. One of the host processing units is configured as a master unit for generating a data frame having a destination address for a selected one of the switching units of a corresponding selected one of the other host processing units. The master unit outputs the data frame to the corresponding switching unit for transfer to the selected one switching unit via the backbone link. The selected one switching unit, in response to receiving the data frame having the corresponding destination address, forwards the data frame to the corresponding host processing unit for execution of a processing operation specified in the data frame. Hence, the switching system provides inter-processor communications using a preexisting backbone link, eliminating the necessity of a processor bus.

Abstract: A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adapted to select signals from the plurality of devices. A second multiplexer circuit may receive the selected signals from the first multiplexer circuit and transmit the selected signals to chosen ones of the plurality of devices.

Abstract: An I/O device that includes: an input port; an input buffer coupled to the input port; an internal port operable to store packets generated by the I/O device; an internal buffer coupled to the internal port; a plurality of packet ID arrival registers coupled to the input port and the internal port; autocorrelation logic coupled to the plurality of packet ID arrival registers; an arbiter coupled to the autocorrelation logic; a packet selector coupled to the arbiter, the input buffer and the internal buffer; and an output port coupled to the packet selector.

Abstract: An OCN that maximizes interconnect utilization between integrated processing elements, including ports, an interconnect, port interfaces, and an arbiter. Each port includes arbitration and data interfaces. The interconnect includes selectable data paths between the ports for packet datum transfer. Each port interface includes processing, source and destination interfaces. The source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. The destination interface receives packet datums via a number of available input buffers. Each transaction request includes a transaction size, a packet priority, and a destination port address. The arbiter includes a request queue and a buffer counter for each port and a datum counter for each acknowledged transaction.

Abstract: An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address.

Abstract: A network relaying apparatus and a network relaying method for securing a high communication quality (QoS), a high reliability and security. A transfer engine stores the packets received through at least a network interface in a packet buffer, and the header information in a header RAM. A search engine searches for the transfer control information such as the destination information and the action information based on the header information, and writes them in the header RAM. The transfer engine prepares an output packet based on the information stored in the packet buffer and the header RAM, and outputs the output packet to the destination. A switch switches the output packet to the routing processor of the destination. Each header RAM is asynchronously accessible independently of the packet buffer and suppresses the competition for access between the transfer engine and the search engine.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes a plurality of ports. Each port is configured to compare a corresponding incoming data packet with at least one template. Each template has min terms specifying a corresponding prescribed value that is to be compared with a corresponding selected byte of the incoming data packet by the port. The network switch also includes a manager module configured to supply a next location field to the corresponding port. The corresponding port determines a next corresponding selected byte of the incoming data packet from the next location field for a next comparison with a next corresponding prescribed value in response to a next location field request.