Abstract: A network relaying apparatus and method for high quality transfer of packets under stable quality-of-service (QoS) control. A transfer engine stores the packets received through a network interface, in a packet buffer, and the header information in a RAM. A search engine searches the transfer control information including the transfer destination information and the action information according to the header information and writes the resulting information in the header RAM. The transfer engine produces an output packet based on the information stored in the packet buffer and the header RAM and outputs it to the transfer destination. A switch operates to switch the output packet to the routing processor of the destination. The QoS control is performed at each of a plurality of points including the input-side routing processor, the output-side routing processor 10 and the switch.

Abstract: A method and apparatus are provided in which control data for a generator system is multiplexed onto a synchronisation signal.

Abstract: A route caching design in a fiber channel switch for providing quick access to recently used D_ID and exit port combinations. The fiber channel switch has a plurality of ports, each are coupled to a central route look-up table. A cache is coupled to each port for storing D_ID to exit port association information received from the central route look-up table.

Abstract: A multi-interface point-to-point switching system includes a plurality of I/O ports coupled to a plurality of respective devices, a switching fabric that selectively delivers each of a plurality of different signals from a selected one of the I/O ports coupled to a sending one of the devices to another selected one of the I/O ports coupled to a receiving one of the devices, to thereby establish respective connections between the sending and receiving devices, and a controller that determines the latency of all possible signal paths that are presently available for each connection to be established, selects the lowest-latency signal path for each connection that it determines is presently available, and then configures the switching fabric to establish the selected signal path for each connection. According to one aspect of the invention, the switching fabric provides a fixed, low latency signal path for each connection whereby the latency of that connection is deterministic and predictable.

Abstract: A route caching design in a fiber channel switch for providing quick access to recently used D_ID and exit port combinations. The fiber channel switch has a plurality of ports, each are coupled to a central route look-up table. A cache is coupled to each port for storing D_ID to exit port association information received from the central route look-up table.

Abstract: A central route table design in a fiber channel switch for providing one location for D_ID and exit port combinations. The fiber channel switch has a plurality of ports, each are coupled to the central route look-up table.

Abstract: A head of line (HOL) blocking count value, which is directly proportional to the committed traffic load for traffic flow through an output port within a multi-stage switch mesh, is computed for a path by adding the values associated with all output ports within the path. In selecting a route, all paths from the source to the destination are identified and sorted by head of line blocking count value. Rather than selecting a path based on traffic load, the path having the lowest head of line blocking count value and sufficient capacity for the requested traffic is selected, with selection between paths having equal head of line blocking count values being made based on traffic load.

Abstract: A crosspoint switch includes a large number of ports and a separate pass transistor linking each possible pair of ports. When a pass transistor is turned on or off, it makes or breaks a signal path between the pair of ports it links. Each port can process signals passing through the port in any one of several operating modes, with a current operating mode being selected by input mode control data. The crosspoint switch also includes a random access memory (RAM) having a separate addressable storage location corresponding to each port. Each RAM storage location stores routing data for controlling the pass transistors connected to a corresponding port and also stores mode control data controlling the mode of the corresponding port. A memory controller responds to a parallel command from a host computer by concurrently writing routing and mode control data to two storage location of the RAM, thereby quickly making and/or breaking a signal path between two ports and selecting the operating mode of both ports.

Abstract: A communication interface device includes a wireless Internet packet (IP) transceiver and a PCMCIA card electrically connected to the transceiver. Also, a universal serial bus (USB) connector is plugged into a hub that holds the PCMCIA card, with a cord extending from the USB connector and terminating in another USB connector. Accordingly, the device can be engaged with the PCMCIA bay of a user terminal or, if a user terminal has no PCMCIA bay, with a USB receptacle of the user terminal, to establish wireless communication between the terminal and a base station of a wireless LAN/WAN.

Abstract: A method and apparatus for managing the flow of data within a switching device is provided. The switching device includes network interface cards connected to a common backplane. Each interface card is configured to support the maximum transfer rate of the backplane by maintaining a “pending” queue to track data that has been received but for which the appropriate routing destination has not yet been determined. The switching device includes a switch controller that maintains a central card/port-to-address table. When an interface card receives data with a destination address that is not known to the interface card, the interface card performs a direct memory access over a bus that is separate from the backplane to read routing data directly from the central table in the switch controller.

Abstract: There is provided a converting processing block 3 for carrying out a processing to convert an arbitration signal into code data of 5 bits and for carrying out 4 bit/5 bit converting processing with respect to packet data to thereby carry out transmission/reception of arbitration signal and packet data as code data of 5 bits through transmitting blocks 6A, 6B and receiving blocks 7A, 7B. Thus, there is realized an interface apparatus for digital serial data which realizes extension of cable length between nodes in the digital serial data interface (e.g., IEEE 1394 high performance serial bus standard) adapted for carrying out arbitration of bus use right prior to transfer of data, thus to permit long distance transmission.

Abstract: A store-and-forward network switch uses an embedded dynamic-random-access memory (DRAM) packet memory. An input port controller receiving a packet writes the packet to the embedded packet memory. The input port controller then sends a message to the output port over an internal token bus. The message includes the row address in the embedded packet memory where the packet was written and its length. The output port reads the message and reads the packet from the embedded memory at the row address before transmitting the packet to external media. Packets are stored at row boundaries so that DRAM page-mode cycles predominate. Only one packet is written to each DRAM row or page. Thus the column address is not sent between ports with the message sent over the token bus. A routing table can also be included in the embedded DRAM.

Abstract: A data transmitting and receiving apparatus for transmitting and receiving data between an external device and a pertinent bus of a plurality of buses connected by a bridge, the external device forming one portion of the bridge is disclosed, that comprises a storing means for storing first information and second information, the first information representing whether the transmission source or the transmission destination of the data is the data transmitting and receiving apparatus, the second information representing whether or not to the data should be transmitted to the pertinent bus, a setting means for setting the first information and the second information stored in the storing means to a predetermined state corresponding to an external request, and a transmitting and receiving means for transmitting and receiving the data to/from the pertinent bus or the external device corresponding to the first information and the second information stored in the storing means.

Abstract: A transmission equipment decides in which, when a frame is received from each of networks, an output physical port corresponding to an output logical port decided by a path deciding section is decided by an output physical port deciding section, a transmitting frame is outputted to the output physical port, and when following received frames are successively transmitted, an output physical port number to which a transmitting frame is outputted by a port number increment section is incremented each time a frame is transmitted, and a destination to which a transmitting frame is outputted is switched among output physical ports.

Abstract: A system for transmitting data between circuit boards within a housing. The system includes a switch card placed within a housing having a plurality of slots for holding circuit boards. The switch card includes a five gigabit switching matrix having at least a first data port and a second data port for receiving data packets. A first data bus connects a first circuit board to the first data port of the switching matrix, and a second data bus connects a second circuit board to the second data port of the switching matrix. The first circuit board transmits data to the second circuit board by transmitting to the switching matrix a data packet that is addressed to the second circuit board and that contains the data.

Abstract: A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets therewith, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller via a separate and like portion of the data path to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers each connected to one of the medium access controllers to which the data path controller is connected, to hold the portion of the data packets exchanged with the corresponding medium access controller.

Abstract: A controlling apparatus, record medium, and method, which include the steps of (a) obtaining control information from the electronic devices, the control information allowing the electronic devices to be controlled, (b) determining whether or not the electronic devices have a time setting function corresponding to the control information obtained at the step (a), (c) obtaining time information, and (d) setting the time information obtained at the step (c) to each of the electronic devices determined as devices having the time setting function at the step (b). Thus, even if an electronic device connected to a network system does not have a function for obtaining time information through the network system, time corresponding to time information can be set to the electronic device.

Abstract: A SONET bus has a set of SONET mappers that transmit and receive facility signals on facility lines. Each facility line operates at a predetermined speed. Each SONET mapper generates a SONET signal by mapping the facility signals received by the SONET mapper into a predefined format for transmission. The predefined format includes timeslots associated with each received facility signal. Each SONET mapper receives a SONET signal and maps the received SONET signal into the facility signals transmitted by the SONET mapper on the facility lines. Each SONET signal includes an associated set of the facility signals. At least one counter outputs a timeslot count signal for synchronizing the timeslots of the facility signals. A set of bidirectional drivers has a mapper side and a system side. Each bidirectional driver receives the timeslot count signal.

Abstract: A broadband packet switch that handles all packets that arrive within the same frame time by simultaneously bit-pipelining the packets into different sections of the one-stop packet buffer through an input switch. Each packet remains in is selected section until its eventual exit from the buffer through an output switch. Access to the memory storage in which the packet buffer resides is not through a memory bus or buses, thereby engendering massive parallel access.

Abstract: A network switch has a plurality of mirror ports to which data is copied for purposes such as networking monitoring. Data flows are identified and copied to an appropriate mirror port in response to the type of flow, a mirroring policy set up by a network administrator, and a distribution mechanism. A monitoring device attached to each mirror port is able to monitor specific types of traffic. Because the data flows are distributed among a plurality of mirror ports and monitoring devices, the ports and devices are less likely to overflow and therefore are more likely to be able handle the copied data without dropping data packets. The mirror ports are collected into groups of such ports. A given port may only be a member of a single group at one time. The mirroring policy must identify the group to which a particular type of flow is copied.

Abstract: A method of incorporating allocations of network access in a DOCSIS 1.0 compliant cable network, wherein users compete for bandwidth, includes limiting bandwidth consumed by a cable modem of a user to a value representative of that user's bandwidth allocation for a time interval. Preferably, the method includes the steps of: (a) generating cable modem configuration files, each of which limits bandwidth consumption by a cable modem of a user to a bandwidth allowance of that user equaling to the respective bandwidth allocation; (b) sending the configuration files to a Trivial File Transfer Protocol (TFTP) Server of the DOC Network; and (c) sending a command either to each user's cable modem, or to a cable modem termination system to which each user's cable modem is connected, to cause the cable modem to implement the respective new configuration file.

Abstract: A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets therewith, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller via a separate and like portion of the data path to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers each connected to one of the medium access controllers to which the data path controller is connected, to hold the portion of the data packets exchanged with the corresponding medium access controller.

Abstract: In the 1394 communication, communication at a data rate of S100, S200, S400, S800, S1600, S3200 or at a faster speed in the future can be performed. When the 1394 communication is performed with an optical-fiber cable and a UTP cable, it is possible to cope with high-speed communication by arranging bits being not used at a low speed, on a data stream. Transmission of data rates is realized by sending speed-control symbols at a predetermined speed. As for a Tp bias signal, an equivalent object is achieved by sending predetermined control symbols.

Abstract: In a switching center having input and output lines, a switching matrix includes primary switching elements, bus structures for respectively connecting one subset of input lines to the primary switching elements, and at least three assemblies each having some of the primary switching elements and at least one output interface. The primary switching elements are supported by a common supporting element and are connected on their input side to the subset of input lines by a same common bus structure. The interface input side is connected to primary switching elements of at least two of the assemblies connected to different subsets of input lines. The output interfaces are respectively disposed at the assemblies between the primary switching elements and a subset of output lines. Each of the assemblies has one of the output interfaces connected on its input side to primary switching elements of at least two of the assemblies.

Abstract: A communications network including a server having multiple entry ports and a plurality of workstations dynamically balances inbound and outbound to/from the server thereby reducing network latency and increasing network throughput. Workstations send data packets including network destination addresses to a network switch. A header is prepended to the data packet, the header identifying a switch output or destination port for transmitting the data packet to the network destination address. The network switch transfers the data packet from the switch input port to the switch destination output port whereby whenever the switch receives a data packet with the server address, the data packet is routed to any available output port of the switch that is connected to a Network Interface Card in the server. The switch includes circuitry for removing the routing header prior to the data packet exiting the switch.

Abstract: The present invention is a fiber channel switch employing a distributed queuing algorithm for interconnecting a plurality of devices (workstations, supercomputer, peripherals) through their associated node ports (N_ports) and employs a fabric having a shared memory coupled to a plurality of fabric ports (F_ports) through a bi-directional bus over which memory addresses, frame data and communications commands are transmitted. Each F_port includes a port controller employing a distributed queuing algorithm associated with a control network for communicating commands between the ports related to when and where frame transfers should be made, wherein the bi-directional bus provides an independent data network for access to the shared memory such that frames can be transferred to and from the shared memory in response to port controller commands.

Abstract: A network switch including a plurality of network ports for receiving and transmitting data, where each port includes at least one statistics register for storing statistics information, such as Ethernet statistical and configuration information. The switch also includes a switch manager, which further includes a memory, retrieval logic for detecting a statistics request signal and for respondingly retrieving the statistics information for storage in the memory, and response logic for asserting a statistics response signal after the statistics information is stored. A processor is coupled to the switch manager through a bus, where the processor asserts the statistics request signal and then detects assertion of the statistics response signal. Upon detecting the response signal, the processor retrieves the statistics information from the memory.

Abstract: A local area network routing switch for routing data transmissions between buses includes a set of input buffers, each for receiving and storing successive data transmissions arriving via a corresponding one of the bus. The switch also includes a set of output buffers for forwarding data transmissions outward via a corresponding bus, and a routing system for selectively routing data transmissions from the input buffers to the output buffers in response to routing requests from the input buffers. The routing system sends STATUS data to each input buffer indicating which output buffers are busy receiving data transmissions and which output buffers are idle. An input buffer makes a routing request only when it stores a data transmission to be forwarded to an idle output port. If its longest-stored data transmission is destined for a busy output port, it may send a routing request for a more recently stored data transmission if that data transmission is to be forwarded to an idle output buffer.

Abstract: The present invention is directed to an apparatus and method for efficiently transferring asynchronous transfer mode (ATM) cells across a backplane in a network switch. The present invention is realized through an electrical apparatus that converts parallel data that is received on parallel data input ports to serial data that is transmitted on serial data output ports. The parallel data that is received on each parallel data input port is divided and transmitted from a corresponding pair of serial data output ports. The electrical apparatus also converts serial data that is received on serial data input ports to parallel data that is transmitted on parallel data output ports. The serial data that is received on a corresponding pair of serial data input ports is combined and transmitted from a parallel data output port.

Abstract: A distributed memory switching hub interconnecting heterogeneous local area networks operating at different transmission speeds for receiving, storing and forwarding frames of data. The distributed memory switching hub employs a distributed memory architecture in which memory storage for frames of data received and to be transmitted is located at each low speed LAN port of the distributed memory switching hub. A distributed memory architecture renders unnecessary the need for a central programmable processor or shared common memory to store and forward frames received by the distributed memory switching hub.

Abstract: A combination of one or more HMG-CoA reductase inhibitors (for example pravastatin, lovastatin, simvastatin, fluvastatin, rivastatin or atorvastatin) with one or more insulin sensitizers (for example troglitazone, pioglitazone, englitazone, BRL-49653, 5-(4-{2-[1-(4-2'-pyridylphenyl)ethylideneaminooxy]ethoxy}benzyl)thiazolidi ne-2,4-dione, 5-{4-(5-methoxy-3-methylimidazo[5,4-b]pyridin-2-ylmethoxy)benzyl}thiazolid ine-2,4-dione or its hydrochloride, 5-[4-(6-methoxy-1-methylbenzimidazol-2-ylmethoxy)benzyl]thiazolidine-2,4-d ione, 5-[4-(1-methylbenzimidazol-2-ylmethoxy)benzyl]thiazolidine-2,4-dione and 5-[4-(5-hydroxy-1,4,6,7-tetramethylbenzimidazol-2-ylmethoxy)benzyl]thiazol idine-2,4-dione) exhibits a synergistic effect and is significantly better at preventing and/or treating arteriosclerosis and/or xanthoma than is either of the components of the combination alone.

Abstract: A device for interconnecting Local Area Networks (LANs) includes ports for attaching LAN segments and port modules for connecting the ports to a switch fabric. Each of the port modules include a mechanism which searches the Routing Information (RI) field of a Received frame to detect at least two Triplets (a minimum configuration for a LAN segment) indicating a Source path from an originator user and a Destination path to a destination user. The Triplet (single or in combination) is used to access a database (tables) which identifies the Port of Exit (POE) through which the frame is to be routed.

Abstract: A method and arrangement for initiating forwarding of data from a device having multiple receive and transmit ports as a function of the data received at the device includes a plurality of ports for receiving and transmitting data. A port vector FIFO forwards a data identifier to initiate forwarding from at least one of the ports of a received set of data. A holding area is controlled by the port vector FIFO and receives data identifiers and holds these data identifiers until released by the port vector FIFO. The release of a data identifier initiates the forwarding of the data, and each data identifier uniquely identifies each set of data received at the device. The port vector FIFO, upon receiving a data identifier, uses the data identifier to determine the receive port that is receiving the set of data identified by the data identifier.

Abstract: A network switch including a separate cut-through buffer for facilitating cut-through mode of data transfer. The switch further includes a data bus coupled to each of the ports, a memory and a switch manager coupled to the data bus and to the memory for controlling data flow. The switch manager includes a receive buffer for handling data received by the switch, a transmit buffer for handling data to be transmitted by the switch, and a separate cut-through buffer for receiving data at any of the ports and for buffering the data to another one of the ports during cut-through mode of operation. The switch manager includes status memory, which includes programmable receive and transmit mode values for each of the ports, the modes selecting between cut-through and store-and-forward mode of operation for an indicated direction for each port.

Abstract: An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.

Abstract: A multiplex extender 26 for permitting discrete I/O devices 34, not individually equipped to decode multiplex channel addresses, to be multiplexed on a time division multiplexed control bus 10. The multiplex extender 26 is connected intermediate the time division multiplexed control bus 10 and a branch line 30 and includes a multiplex channel address decoder 78, a data disconnect switch 82 and a branch line controller 90. The multiplex channel address decoder 78 is selectively programmed to one of the multiplex channel addresses of the time division multiplexed control bus 10. The multiplex channel address decoder 78 produces one or more output signals, each being determined by the multiplex channel address which has most recently been decoded.

Abstract: A communication system is described which enables efficient delivery of asymmetrical bandwidth signals over a communication network. The system includes a virtual circuit switch having a space switch coupled thereto for distributing downstream signals from a backbone network to subscribers in a cost effective manner.

Abstract: A self-routing, modular, switching arrangement for distributing and concentrating input data packets that is comprised of a distribution section and a concentration section comprising N priority concentration sorters each having N inputs and L outputs, L being less than N. The sorters comprise means for ordering data packets according to priority information and for transferring only the L data packets from N inputs which have the highest relative priorities. A multiplicity of the switching arrangements can be interconnected to provide an expanded switching arrangement. The distribution network may be of a radix-r tree configuration in which multicast elements reference an extra cell header which identifies the output links of a multicast elements to which a data packet is to be transferred.

Abstract: The present invention teaches a variety of methods and apparatus. The steps of one method for wiring an electrical system having a first bus and a second bus are as follows. Routing a wire B between wires A and A' and a wire B' adjacent to wire A' within the first bus, the wire B intended to transmit a first signal, the wire B' intended to transmit a signal associated with the first signal, the wire A intended to transmit a second signal, and the wire A' intended to transmit a third signal associated with the second signal. Routing a wire D between wires C and C' and a wire D' adjacent to the wire C' within the second bus, the wire D intended to transmit a fourth signal, the wire D' intended to transmit a signal associated with the fourth signal, the wire C intended to transmit a fifth signal, and the wire C' intended to transmit a sixth signal associated with the fifth signal.

Abstract: A communications interface is used in a telecommunications network station which including a number of network elements, a controller for controlling the network elements and an internal bus interconnecting the controller and the network elements. The controller operates as a busmaster on the bus and each of the network elements operates as a slave on the bus. The communications interface has a pool of buffers for temporary message storage and a polling function for temporarily storing a message received from the bus in a buffer and/or for taking a message from a buffer for transmission over the bus. A binary sequence number is inverted for a reply if a received message is valid, otherwise it is not changed for the reply. A message is re-sent when the sequence number in a reply has not changed.

Abstract: A congestion management scheme for managing traffic in a data communication system having a plurality of port blocks at least one of which may be connected to a communication medium, the congestion management scheme including a structure for determining whether a sender is congested, a structure for determining whether a receiver is congested, and a structure for determining whether a RX FIFO is congested and a structure for determining a memory buffer, associated with at least one of the sender and the receiver, is congested. The congestion scheme further includes a structure for handling traffic by taking one of the preferred actions depending upon the congestion indicators.

Abstract: Disclosed is a telecommunication system that is both highly cost effective for small scale applications (for example, those having less than 80 lines), yet field upgrade-expandable to applications having a significant number of additional lines (for example, 30,000 lines). An integrated voice/data telecommunication system is utilized that is flexible enough to handle low bandwidth (for example 64 kbps mu-law) speech as well as high bandwidth multimedia data switching. The system may be configured as a low cost, standalone PACS system for "village telephony" or "PACS-on-POTS" applications, as an alternative to requirements for PACS infrastructure when appropriate wireless network facilities are unavailable.

Abstract: A high speed packet switch which is inherently non-blocking, requires a minimum amount of buffering, is modular and degrades gracefully with failures. The output destination buffers can each absorb data at the full switch rate to avoid contention and they are filled evenly to minimize buffer size. The architecture only requires few parts types (multiplexers, demultiplexers and crosspoint switches) to operate at high speeds. The output list offers considerable flexibility in the way the data is output, whether it is by priority and/or by time division multiplexed sub destinations.

Abstract: 057517104An efficient connection technique maximizes the rate at which data are transferred among source and destination network cards of a distributed network switch. Such maximum data rates are achieved by interconnecting the network cards through a mesh backplane comprising a novel arrangement of direct and indirect paths between the cards and thereafter transferring the data over those paths. In accordance with the invention, the indirect data path utilizes an additional network card of the switch as a 2-hop relay to provide transfer rate efficiency between the source and destination cards.

Abstract: A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data.

Abstract: A communication network (10) includes packet switching nodes (18) in which packets from high speed data links (20, 22) are switched onto a multiplicity of low speed data links (26). Each node (18) includes a bulk RAM (30) which has a section (32) dedicated to implementing a multiplicity of logically independent FIFO buffers. A routing controller (46) controls DMA transfers of packets into and out from appropriate FIFO buffers. Packets are transferred into respective FIFO buffers consecutively and transferred out from respective FIFO buffers interleaved together.