Abstract: A transmitting system inserts runt abort packets in an outgoing data stream during idle time inter-frame time fill. The runt abort packets cause the receiving system to synchronize itself to the transmitting system so that even if an error during inter-frame time fill causes the receiving system to go into an erroneous state, the receiving system will be synchronized with the transmitting system before receiving valid data. In one embodiment, the transmitting system transmits data in packets over SONET. The packet data is scrambled at the transmitting end and descrambled at the receiving end. Runt abort packets sent during inter-frame time fill resynchronize the descrambler. If there is an error in the inter-frame time fill bytes, causing the receiving end descrambler to no longer be synchronized with the transmitting end scrambler, the runt abort packets will cause the descrambler to resynchronize state with the transmitting scrambler.

Abstract: A remote control is operative to transmit a remote control signal composed of a first portion and a second portion. The first and second portions are typically a pulse and a space. The pulse has a pulse width of a given duration within a pulse width range, while the space has a space width of a given duration within a space width range. An interrupt signal provided to indicate the end of transmission of the remote control signal is disabled when a space portion requires a space width greater than the space width range. The interrupt signal signaling the end of the remote control transmission is then disabled for a predetermined period of time essentially equivalent to a length of time that the additional space exceeds the space width. During the predetermined period of time, the remote control thus transmits a space. The interrupt signal is then re-enabled after expiration of the predetermined period of time in order to allow for another remote control transmission.

Abstract: The present invention discloses a system which comprises two endpoints (1, 2) communicating with each other by means of a packet-switched network. The endpoints (1, 2) use adaptation algorithms for estimating jitter from packet arrival times and for modifying silence period lengths according to the latest estimate. According to the present invention, the endpoints (1, 2) are able to measure a response time (?) at a certain point of time and use it as a parameter in the adaptation algorithms.

Abstract: The present invention discloses a network system, in which data is transmitted in the form of transmission frames, the system including a network control unit (4) for controlling communication in the network and a terminal (2) for receiving and transmitting data from/to the network control unit (4). When the network control unit (4) receives a request for changing from a first user data rate to a second user data rate it adds/deletes fill data (FD) to/from a transmission frame corresponding to the requested change in the user data rate for transmitting data to the terminal (2) at the second user data rate. The terminal (2) detects the change in the amount of fill data (FD) and changes the user data rate transmitted to the network control unit (4) according to the detected change. In this system, it is possible to smoothly change the data rate without affecting the quality of service.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: The invention comprises a method and apparatus for reducing uncertainty in timing on the network. The uncertainty in receive buffers is removed by time stamping the arriving packets before sending the packets to the receive buffer. The uncertainty in the transmission buffer is removed by giving the packets a timestamp in the future, and holding the packets until precisely that time. Time precision is ensured by only releasing time packets at the host physical layer to network boundary at the time specified within the packet.

Abstract: The present invention provides a transceiver couplable to a communications network having a jitter control processor and methods of operating the same. In one aspect of the present invention, the jitter control processor of the transceiver includes a transmitter stage that controls a transmit signal. In one embodiment, the transmitter stage includes a transmit time error measurement system configured to generate a transmit time error signal as a function of timing synchronization associated with a communications network clock and a transceiver master clock, a transmit filter circuit configured to develop a filtered time error signal as a function of the transmit time error signal, and a stuffing control system configured to insert a stuffing control signal into the transmit signal as a function of the transmit time error signal and the filtered time error signal.

Abstract: In order to predictively time stamp isochronous data packets transmitted over an IEEE 1394-1995 serial bus network, an application, which is to send a stream of isochronous data packets to a receiving node, first transmits a number of dummy frames each consisting of a number of packets. Preferably, these isochronous data packets make up frames of video data. From these dummy packets, the application obtains the time stamp values within the common isochronous packet (CIP) header of each packet. Using these obtained time stamp values, the application calculates a presentation time value for each data frame to be transmitted. The obtained time stamp value from a transmitted video frame is used to calculate the presentation time for a video frame which is a number of frames ahead within the transmit queue.

Abstract: The invention relates to methods for encoding/decoding of a digital signal which is transmitted over a packet switched network. Prediction samples are generated at the transmitting and receiving end. The digital signal is lossless encoded at the transmitting end, and lossless decoded at the receiving end, based on the quantizations of generated prediction samples. During encoding, the generated prediction samples are quantized separately from the quantization of the digital samples. The predictions are used in the index domain in the form of quantized indices during encoding/decoding of the digital signal.

Abstract: The present invention is generally directed to a system and method for encoding a DSL information bit stream and decoding a corresponding encoded DSL symbol. In accordance with one embodiment, an apparatus for encoding a DSL information bit stream is provided having a switch with an input configured to receive a DSL information bit stream and at least two outputs. An encoder is provided and coupled to a first output of the switch. A serial to parallel converter is provided and coupled to both an output of the encoder and a second output of the switch. Finally, a mapper is provided and coupled to an output of the serial to parallel converter through multiple paths. Preferably, a first coupling path between the serial to parallel converter and the mapper is a direct path and a second coupling path includes a second encoder.

Abstract: A method and apparatus to provide encryption and authentication of a mini-packet in a multiplexed real time protocol (RTP) payload. Mini-packets are assembled into a payload wherein each mini-packet includes an associated mini-header for ensuring proper processing of each mini-packet. Padding is added to mini-packets when the mini-packets are encrypted to insure each mini-packet is an integral multiple of a predetermined block size. Padding for each mini-packet is determined according to p=n?k*floor((n?1)/k), wherein p is the amount of padding added to each mini-packet, n is the actual data size, and k is the block size. The padding added to the data for each packet comprises p?1 units of padding and a final padding unit for indicating the amount of padding. An authenticator may also be added to each mini-packet. A length indicator is set in each mini-header for indicating a total length of the mini-packet including the authenticator.

Abstract: A frame of digital data with L symbols is matched to a frame with N symbols by making that number of copies of the original L symbols that results in N symbols. In particular, M=floor(N/L) is computed. L2=N?ML is computed. (L1=L?L2 where L1 and L2 solve the simultaneous equations L1+L2=L and L1*M+L2*(M+1)=N). The frame is effectively divided into two mutually exclusive groups of symbols; one group (consisting of L1 symbols) is copied M times and the other group (consisting of L2 symbols) is copied M+1 times.

Abstract: A system transfers a data stream including data packets separated by non-packet words from a first clock domain to a second clock domain. It includes an elasticity buffer into which the data stream is written in a cyclic sequence under the control of the clock frequency in the first clock domain and from which the data stream is read out in a cyclic sequence under the control of the clock frequency in the second domain. The two sequences are monitored to provide an anticipatory signal indicating that the reading sequence approaches proximity to the writing sequence. A non-packet word is inserted into the data stream in the first domain. In the second clock domain the existence of the inserted non-packet word is detected and the buffer is caused to advance the reading cycle thereby to discard the said inserted non-packet word.

Abstract: A device for associating indexes to addresses chosen from among a greater number of values than the number of available indexes, including a memory containing indexes and respective check words corresponding to predetermined bits of the addresses associated with the indexes; a packing circuit receiving a current address and suppressing in this address bits determined by a pattern such that the suppressed bits correspond to bits of the check words, the packed address provided by the packing circuit being used to select in the read mode a memory location; and a comparator indicating that the current address corresponds to the selected memory location if the bits of the check word of the selected location are equal to the corresponding bits of the current address.

Abstract: A desynchronizer for smoothing gapped data signal and a gap clock signal extracted from a synchronous message is disclosed. A gap regulator module first re-maps the gapped data signal into a B-frame format and distributes the gaps in the data uniformly throughout the gapped data signal. A pointer leak logic module determines the bit leak rate as a function of received increment and decrement pointer adjustment signals. The pointer leak logic module determines the bit leak rate using separate algorithms. If the increment and decrement pointer adjustment signals are periodic in nature the bit leak rate is determined by dividing the periodic rate interval between two successive pointer adjustment signals by eight (8) and form a leak rate lookup table to account for any additional or missed pointer movements by looking up the incremental leak rate as a result.

Abstract: A bit-stream converter capable of converting a first synchronous compressed bit-stream of data at a first sampling rate to second synchronous compressed bit-stream frame of data at a second sampling rate is disclosed. The bit-stream converter architecture may include a payload length detector and a zero stuffing unit in signal communication with the payload length detector. The zero stuffing unit is capable of zero stuffing section responsive to the payload length detector detecting the payload length.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: A method and apparatus for audio compensation is disclosed. If audio input components and audio output components are not driven by a common clock (e.g., input and output systems are separated by a network, different clock signals in a single computer system), input and output sampling rates may differ. Also, network routing of the digital audio data may not be consistent. Both clock synchronization and routing considerations can affect the digital audio output. To compensate for the timing irregularities caused by clock synchronization differences and/or routing changes, the present invention adjusts periods of silence in the digital audio data being output. The present invention thereby provides an improved digital audio output.

Abstract: The present disclosure is generally directed to a system and method of measuring transport utilization of data that is to be multiplexed and transmitted over a digital transport facility. In a particular embodiment the method includes receiving at least one frame of a data channel at a time division multiplexing device, padding an unused portion of the frame with a number of stuff bits, determining a user traffic utilization measurement based on the number of stuff bits and based on the size of the data payload, and reporting the traffic utilization measurement. In this embodiment, the frame has a fixed data payload.

Abstract: A massive packet transmitter in a WAN (wide area network) . The transmitter includes: an encoder for segmenting packets for transmission through the WAN into messages having a predetermined length, encoding the respective segmented messages, adding a parity bit to each encoded message to make it into a codeword, and transmitting the codeword/ A decoder is used for receiving the codeword from the encoder through the WAN, correcting an error of the corresponding codeword, and removing a parity bit included in the corresponding codeword to recover the codeword to an original message. Errors generated when transmitting massive packets through the WAN are removed using a FEC method, and massive packets such as a IPv6 jumbogram can be used without errors in the WAN.

Abstract: In a frame synchronization circuit, which prevents the occurrence of synchronous error due to a data loss/insertion while restraining a false synchronization/out of synchronization based on typical code error in a conventional data transmission system, the frame synchronization circuit is provided with a frame synchronization code detector which detects a frame synchronization code from a received data sequence to output a frame position and outputs a checked result by checking a frame synchronization code detected and a correct frame synchronization code. The frame synchronization circuit is also provided with and a data loss and data insertion period judgment circuit which determines which presumes whether a data loss or data insertion has occurred in the received data sequence according to the checked result.

Abstract: In transmitting signals to an opposing terminal by introducing a system current from a terminal of this side, a dummy bit interpolator (105) is provided for inserting dummy bits among the fixed frame lengths of the transmission signals to adjust the length of the transmission data by using dummy bits in order to maintain synchronism in the sampling timings even when there does not hold a multiple relationship between the sampling frequency and the rate of transmission.

Abstract: The objective is to provide a data transfer control device and electronic equipment that implement bit insertion, encoding, decoding, and bit deletion at a slow clock frequency. A bit stuffing circuit and NRZI encoder are provided in a stage before a parallel-serial conversion circuit on the transmission side and an NRZI decoder and a bit unstuffing circuit are provided in a stage after a serial-parallel conversion circuit on the reception side, so that bit stuffing, NRZI encoding, NRZI decoding, and bit unstuffing are implemented on parallel data, not serial data. Any bits that have overflowed due to the bit insertion are carried forward to data for the next clock cycle and any deficiency of bits caused by bit deletion is moved up from the data of the next clock cycle. Insertion (or deletion) of bits is based on the thus calculated bit stuffing (or bit unstuffing) position and the range of parallel data to be output is based on the accumulated total of the number of bits that overflow (or contract).

Abstract: In order to predictively time stamp isochronous data packets transmitted over an IEEE 1394-1995 serial bus network, an application, which is to send a stream of isochronous data packets to a receiving node, first transmits a number of dummy frames each consisting of a number of packets. Preferably, these isochronous data packets make up frames of video data. From these dummy packets, the application obtains the time stamp values within the common isochronous packet (CIP) header of each packet. Using these obtained time stamp values, the application calculates a presentation time value for each data frame to be transmitted. The obtained time stamp value from a transmitted video frame is used to calculate the presentation time for a video frame which is a number of frames ahead within the transmit queue.

Abstract: A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are received due to the delays in the signal paths between the data requestor and the data source. Accordingly, the data requestor provides skewed clock and read request signals to its input sampling module to simulate the delays of the signal paths. Additionally, the data requestor provides process information associated with the requested data to a dual clock first in-first out (FIFO) buffer. When the input sampling module detects a read request using the skewed read request signal, the input sampling module can use this signal and the skewed clock signal to sample a data signal from the data source to obtain the requested data.

Abstract: In a transmission method and apparatus, low-speed SDH signals are multiplexed into a high-speed SDH frame, the high-speed SDH frame including at least an information payload, a line overhead and a section overhead, the section overhead being divided into a first section overhead SOH and a second section overhead SOH, the first SOH carrying regenerator SOH bytes and the second SOH carrying multiplex SOH bytes. The multiplex SOH bytes in the second SOH of the high-speed SDH frame are detected without changing the line overhead and the payload when the high-speed SDH frame reaches a receive-side high-level line terminating equipment. The multiplex SOH bytes in the second SOH of the high-speed SDH frame are generated without changing the line overhead and the payload before the high-speed SDH frame is transmitted by a transmit-side high-level line terminating equipment.

Abstract: The present invention discloses a method and device for bit stuffing for digital communication purposes. A method according to the present invention contains a process related to bit stuffing, comprising the steps of selecting n bits from a first queue forming a first-bit sequence, comparing the first bit sequence with prestored bit stuffing data and performing actions with the selected bit sequence and first queue according to data comprised in the prestored bit stuffing data. In a bit stuffing process according to the present invention a number of bits are added to a second queue and a number of bits are removed from the first queue, said bit sequences or number of bits are determined from the prestored bit stuffing data. The process of comparing the selected bit sequence with prestored data is possible to perform in all steps involved with bit stuffing, both in the transmitting process and in the receiving process, and in the during flag hunting as well as bit stuffing.

Abstract: A method in a code division multiple access communication system having network infrastructure and a plurality of mobile terminals, including transmitting (210) composite signal comprising a synchronization signal and another non-orthogonal signal from the network infrastructure, receiving (220) the composite signal at the plurality of mobile terminals of the code division multiple access communication system, and increasing forward link capacity of the code division multiple access communication system by canceling (230) the synchronization signal from at least some of the plurality of mobile terminals.

Abstract: In a clock signal reproducing circuit in a pulse stuffed synchronizing system, a destuffing circuit removes stuff pulses and unnecessary bits from a higher order group signal to output a lower order group signal, and outputs stuff data indicating existence or non-existence of positive stuff or negative stuff in the higher order group signal. A storage circuit stores the lower order group signal outputted from the destuffing circuit. A stuff rate determining circuit determines a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of the higher order group signal based on the stuff data outputted from the destuffing circuit. A variable frequency divider frequency-divides a clock signal of the higher order group signal based on the control signal outputted from the control circuit.

Abstract: A communication device for transmitting a sequence of data, which is transmitted thereto at a given transmission rate, at a desired transmission rate greater than the former transmission rate over a transmission line. The device comprises a mapping unit, in order to map the sequence of data into a plurality of frames in a predetermined form, each of which consists of a plurality of blocks, for assigning a predetermined amount of data to a data transmission area in each of the plurality of blocks included in each frame so that the sequence of data is nearly-uniformly arranged over the plurality of blocks included in each frame.

Abstract: A system and method for transporting telephony signals across an ATM network using AAL1 while eliminating the jitter associated with the AAL1 cells. The present invention uses starve/inspect techniques to dynamically buffer the ATM frames such that jitter associated with the cells can be reduced while avoiding unneeded buffering that would cause excessive delay.

Abstract: A parallel bit stuffing method acting on a stream of serial data is disclosed. First, an input data segment is segmented from said stream of serial data. Next, a carryover segment is appended to the input data segment to form an address field. The address field is used to correlate to an output field that includes a stuffed data portion and a carryover segment portion. The carryover segment portion is used in a next cycle as the carryover segment. Finally, the stuffed data portion is output as output data segments.

Abstract: Methods and apparatuses in which two or more types of attributes from an information stream are identified. Each of the identified attributes from the information stream is encoded. A time ordered indication is assigned with each of the identified attributes. Each of the identified attributes shares a common time reference measurement. A time ordered index of the identified attributes is generated.

Abstract: The present invention provides a receiver apparatus for receiving digital data in which stuff data have been inserted by stuffing synchronization. The receiver apparatus has a memory unit having a plurality of memory cells. The digital data other than the stuff data are written in the memory unit in synchronization with a write clock signal, and read from the memory cell in synchronization with a read clock signal. The cycle of the read clock signal is adjusted on the basis of an interval from a reading address to an writing address of the memory cell.

Abstract: A system and method for accelerating the reconfiguration of a field programmable radio frequency communication system having transmitter and receiver modes of operation, by outputting the data within the system at an accelerated rate (flush) when switching from a receive mode of operation to the transmit mode, or to another receive mode with another signaling scheme, and loading data to be transmitted into the system at an accelerated rate (queue) when switching into the transmit mode.

Abstract: A method and apparatus for performing bit stuffing operations for transmission signals are described. In an embodiment, a method includes receiving data for a number of channels of a signal. The method also includes recursively processing the data for the number of channels in an order. The processing of a channel of the number of channels includes retrieving a previous state for the channel upon determining that a timeslot for the channel is being processed. The previous state includes a history of values of a depth of a First In First Out (FIFO) for the channel. Moreover, the processing of the channel of the number of channels within the signal includes determining whether to make a bit stuffing decision for the channel upon determining whether the timeslot is associated with a bit stuffing opportunity for the channel. The bit stuffing decision is based on a current value and the history of the values of the depth of the FIFO for the channel.

Abstract: A clock smoothing circuit generates a smoothed clock signal from a gapped clock signal having unevenly spaced pulses separated by gaps that result from the removal of data bits and from a reference clock signal having evenly spaced pulses that create a predetermined reference frequency. A smoothing element is coupled to the input elements to receive the gapped clock signal and the reference clock signal. In one embodiment, the smoothing element generates a smoothed clock signal having one pulse for each of the pulses in the gapped clock signal and having a frequency that is greater than one-half of the predetermined reference frequency. Each pulse in the smoothed clock signal is synchronized with a pulse in the reference clock signal.

Abstract: An adjusting method for a synchronous signal in an optical storage device is disclosed. The optical storage device produces a predetermined synchronous signal, and the predetermined synchronous signal normally is matched with the data synchronous signal of the data on the optical disc. The predetermined synchronous signal includes a number of predetermined synchronous impulses, and the data synchronous signal includes a number of data synchronous impulses. In the method, when the data synchronous signal is not matched to the predetermined synchronous signal, it is searched that whether or not a data synchronous impulse is outside of the predetermined window and another consecutive data synchronous impulse detected later by a distance of an image frame is detected. Also and, according to the data synchronous impulse, the predetermined synchronous impulse is adjusted, so that the data synchronous impulse is matched with the predetermined synchronous impulse.

Abstract: The disclosure describes generation of HDLC (High-Level Data Link Control) frame bits by the application of an HDLC stuffing operation that operates on bits in parallel. The disclosure also describes parallel bit processing for destuffing bits of an HDLC (High-Level Data Link Control) frame.

Abstract: In connection with plesiochronous data transmission, data are input into an elastic memory on the basis of a first clock pulse and read out on the basis of a second clock pulse which runs asynchronously with the first. Stuff bits are inserted at the end of a data frame as needed. For this purpose, the phase difference between clock pulses within a data frame is first of all measured. This phase difference is then compared with a threshold and a certain number of stuff bits are correspondingly inserted. In accordance with the invention, a frequency difference existing between the clock pulses is measured and, depending upon in which of several specified segments it lies, a correspondingly predefined modulation curve is used as threshold. Preferably a numerically optimized curve with respect to jitter amplitudes is used for each segment.

Abstract: The desynchronizer of the present invention includes two FIFOs. The first FIFO has two address counters (write and read), an intermediate count register, circuitry for calculating the difference between the write and intermediate counts and the intermediate and read counts, a logic block for performing pointer leak and other arithmetic functions, and a digitally controlled oscillator (DCO). The second FIFO has read and write counters, a phase-frequency detector, and an internal VCO controlled by length measurements of the second FIFO. The desynchronizer receives data bits, pointer movement indications, and stuff indications from a DS-3/E3 demapper and, using the first FIFO, the address counters, etc., removes the low frequency components, including SONET/SDH systemic gapping in order to provide the second FIFO with a DS-3/E3 signal having a high frequency phase modulation. The second FIFO removes the remaining high frequency gapping jitter.

Abstract: A method of inserting a service channel in frames that are plesiochronous relative to the service channel, the method including the steps of transmitting a block clock between a transmitter and a receiver of the frame, and reserving at the transmitter at least one location in the frames for the purpose of conveying the service channel data.

Abstract: A parallel-to-serial-to-parallel circuit are disclosed, the circuit interfacing with a data bus, preferably with a processor for byte alignment and other operations. The parallel-to-serial-to-parallel circuit includes an input bit shift register having a predetermined number of register positions and an output bit shift register with the same number of register positions. The output of the input bit shift register is fed into the output bit shift register through a multiplexer. The input bit shift register may receive a bit write from a bit bus, a partial parallel write from a data bus with corresponding data validity data received on a shadow bus, and full parallel write from the data bus. The output bit shift register may transmit a bit read to the bit bus or a full parallel read to the data bus. Data received is shifted to the output bit shift register and compiled into full parallel data or read out as single bits. Offset bits may be introduced in the data stream for data alignment.

Abstract: A method to encode and decode frames of data used in the synchronous HDLC protocol operates on blocks of data, as opposed to bit-by-bit. A first reference (“lookup”) table is provided for zero insertion during the HDLC encoding process and a second reference table is provided for flag or abort signal detection and zero deletion during the HDLC decoding process.

Abstract: Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.

Abstract: A memory saving type time switching circuit of a synchronous super high speed transmission apparatus for saving required memory by switching data based on data properties being received by a synchronous super high speed transmission apparatus. A frame information signal generating portion receives data that is to be switched and generates count signals for data switching. A record control portion stores received data to a switching memory portion according to received data type using a predetermined rule. According to received data types and switching information from the central processing unit, a connection information generator reads the switching memory portion using a predetermined rule. According to read data types from the switching memory portion, an output time point compensation portion compensates an output point.

Abstract: A PLL circuit that causes an internal oscillation signal to lock to an external input clock signal, and is capable of suppressing jitter. The PLL circuit includes a frequency dividing circuit for frequency-dividing an input clock signal; a voltage-controlled oscillator; a missing-pulse clock signal creation circuit for creating, based on an output signal of the voltage-controlled oscillator, a missing-pulse clock signal having a higher speed than that of an output signal of the frequency dividing circuit and having a periodic missing-pulse portion; a phase comparator circuit for sampling the output signal of the frequency dividing circuit by using the missing-pulse clock signal; a shift register for storing a change in the output signal of the phase comparator circuit; and a digital signal processing circuit for converting a value stored in the shift register into a phase difference, and for controlling the input voltage to the voltage-controlled oscillator based on the phase difference.

Abstract: A data transmission frame containing payload data, preceded by a synchronization pattern (F), is essentially characterized in that it does not contain any payload data sequences that imitate the synchronization pattern. The payload data sequences that imitate the synchronization pattern are referred to as “forbidden” sequences. These forbidden sequences are replaced with “substitute” data (S0, S1, S2), thereby enabling the forbidden sequences to be re-inserted among the payload data upon reception.

Abstract: A control interface for the bit rate of digital data to be recorded as well as a control interface for the bit rate of digital data emanating from a reading device, particularly when the digital data constitutes a high bit rate uninterrupted data stream such as a video data stream in the MPEG II format. Each control interface comprises a memory circuit for storing the data to be recorded or to be read and a device for storing the data to be recorded or read in the memory circuit so as to fill the memory circuit to a predetermined level. The storing device includes a gauge for generating an information item giving the fill level of the memory.