Plural Synchronization Words Patents (Class 370/513)
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Patent number: 10984053Abstract: An operation assistance system receives selection of a first procedure in a procedure manual including a plurality of procedures relating to an operation of an operation target. The operation assistance system displays an estimation structure obtained by structuring at least part of the first procedure based on an abstraction structure obtained by structuring a second abstraction procedure included in a first abstraction procedure corresponding to the first procedure and the selected first procedure.Type: GrantFiled: June 5, 2017Date of Patent: April 20, 2021Assignee: HITACHI, LTD.Inventors: Katsunori Suzuki, Mineyoshi Masuda, Kiyomi Wada, Hironori Emaru
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Patent number: 10516436Abstract: A spread-spectrum-signal reception apparatus includes a controller to obtain a phase comparison value that is a phase of a spread code at a time at which initialization of a phase of the spread code is performed and which corresponds to a timing of a top of a frame of a received signal, and to output an initialization instruction including the phase comparison value when having determined that a current time is within a range of a time window; and a signal processor to demodulate the received signal in accordance with the spread code, to perform a frame synchronizing process on the demodulated signal to detect a frame timing, and to perform the initialization at a timing determined in accordance with a result of comparison between the phase comparison value included in the initialization instruction and a phase of the spread code at the frame timing.Type: GrantFiled: April 19, 2016Date of Patent: December 24, 2019Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Katsuyuki Motoyoshi
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Patent number: 8982998Abstract: A transmission apparatus includes a plurality of orthogonal frequency division multiplexing (OFDM) modulation signal generators, which generate a first OFDM modulation signal and a second OFDM modulation signal. The transmission apparatus also includes a transmitter that transmits the first OFDM modulation signal from a first antenna and the second OFDM modulation signal from a second antenna, in an identical frequency band.Type: GrantFiled: March 3, 2014Date of Patent: March 17, 2015Assignee: Panasonic Intellectual Property Corporation of AmericaInventors: Yutaka Murakami, Masayuki Orihashi, Akihiko Matsuoka
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Patent number: 8891349Abstract: A method of optimizing performance in a wireless communication system by transmitting a first parameter using a first channel before the optimization of one or more selected channels, wherein the first parameter comprises a modulation scheme used to optimize performance of one or more channels and a first schedule.Type: GrantFiled: December 22, 2004Date of Patent: November 18, 2014Assignee: QUALCOMM IncorporatedInventors: Edward Harrison Teague, Avneesh Agrawal
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Patent number: 8824612Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.Type: GrantFiled: April 10, 2012Date of Patent: September 2, 2014Assignee: Micron Technology, Inc.Inventor: Yantao Ma
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Patent number: 8804892Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.Type: GrantFiled: September 14, 2012Date of Patent: August 12, 2014Assignee: Vitesse Semiconductor CorporationInventor: Ian Kyles
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Patent number: 8730855Abstract: A method for detecting a channel in a mixed-mode communications system is presented. The channel contains a primary synchronization pattern in a predetermined location within the channel. The primary synchronization pattern is compared against different predetermined channel synchronization patterns to detect a channel. Upon detection of the channel, a look-back channel detector confirms the existence of the channel by using the location of the primary synchronization pattern. Detection and confirmation of the channel may be employed simultaneously to each channel of a multiple-channel direct mode of operation signal. Audio holes may be eliminated in a 2:1 TDMA direct mode operation where both time slots contain signals from two different originating communication devices and the signals have different priority.Type: GrantFiled: December 22, 2010Date of Patent: May 20, 2014Assignee: Motorola Solutions, Inc.Inventors: Hun Weng Khoo, Yueh Ching Chung, David G. Wiatrowski
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Patent number: 8717972Abstract: The present invention provides a method for range extension is wireless communication systems. One embodiment of the method includes determining whether a mobile unit is within a first range corresponding to a range of timing advances supported by a timing advance command. This embodiment also includes transmitting a plurality of timing advance commands to the mobile unit when the mobile unit is outside the first range so that the mobile unit can synchronize with the base station by combining information in the plurality of timing advance commands.Type: GrantFiled: October 21, 2010Date of Patent: May 6, 2014Assignee: Alcatel LucentInventors: Fang-Chen Cheng, Jung Ah Lee
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Patent number: 8711990Abstract: A system including a demodulation module, a metric generation module, and a preamble detection module. The demodulation module is configured to generate demodulated signals based on demodulating, in accordance with a differential demodulation scheme, signals received from a base station. The signals received from the base station include a plurality of symbols. The demodulated signals comprise a plurality of real parts each having a corresponding magnitude. The metric generation module is configured to generate a plurality of metrics for the plurality of symbols based on the corresponding magnitudes of the plurality of real parts of the demodulated signals. The preamble detection module is configured to detect, based on the plurality of metrics, whether the plurality of symbols in the signals received from the base station includes a preamble symbol.Type: GrantFiled: April 29, 2013Date of Patent: April 29, 2014Assignee: Marvell International Ltd.Inventors: Jungwon Lee, Qing Zhao
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Patent number: 8711836Abstract: Apparatus and methods relating to synchronization of communication equipment are disclosed. Synchronization information received from a bonded communication link can be used to synchronize local and/or remote communication equipment, such as femtocell sites coupled to nodes in a ring network. This may involve isolating a frequency reference signal from a DSL (Digital Subscriber Line) communication link which is a constituent link of a bonded communication link, for example. In a ring network, received synchronization information could be used in synchronizing a locally connected installation of communication equipment, and passed for transmission in the ring network for synchronizing other communication equipment. Such dropping and passing of an analog frequency reference signal could be applied in networks having other topologies as well. At least some embodiments of the invention are applicable to optical links.Type: GrantFiled: July 13, 2009Date of Patent: April 29, 2014Assignee: Genesis Technical Systems Corp.Inventors: Stephen P. Cooke, Tino Zottola
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Patent number: 8705656Abstract: A transmission apparatus includes a plurality of orthogonal frequency division multiplexing (OFDM) modulation signal generators, which generate a first OFDM modulation signal and a second OFDM modulation signal. The transmission apparatus also includes a transmitter that transmits the first OFDM modulation signal from a first antenna and the second OFDM modulation signal from a second antenna, in an identical frequency band.Type: GrantFiled: April 18, 2013Date of Patent: April 22, 2014Assignee: Panasonic CorporationInventors: Yutaka Murakami, Masayuki Orihashi, Akihiko Matsuoka
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Patent number: 8705579Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.Type: GrantFiled: June 2, 2004Date of Patent: April 22, 2014Assignee: QUALCOMM IncorporatedInventors: Jon James Anderson, Brian Steele, George Alan Wiley, Shashank Shekhar
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Patent number: 8681817Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.Type: GrantFiled: October 28, 2008Date of Patent: March 25, 2014Assignee: QUALCOMM IncorporatedInventors: Jon James Anderson, Brian Steele, George Alan Wiley, Shashank Shekhar
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Patent number: 8676363Abstract: An information processing apparatus includes a communication unit, an incoming data determining unit, and an audio processing command generator. The communication unit communicates with an external apparatus that splits outgoing audio data and sequentially sends transmission audio signals, each signal having a header and transmission audio data containing some of the split audio data with an appended first counter. The incoming data determining unit determines the existence of continuity-related errors in a received transmission audio signal, on the basis of the first counter, as well as a second counter contained in the header. The audio processing command generator selectively generates an audio processing command on the basis of the determination results in the incoming data determining unit, wherein the audio processing command stipulates audio data playback processing to be conducted in the event of an error.Type: GrantFiled: March 12, 2010Date of Patent: March 18, 2014Assignee: Sony CorporationInventors: Shigeru Inoue, Shinya Okada
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Patent number: 8649454Abstract: A detector receives detects a first known signal in a packet signal. An LTF correlation unit performs correlation processing on the packet signal received by a receiving unit. Upon detecting the arrival timing, an update correlation unit terminates a first window and performs correlation processing on the packet signal received by the receiving unit, in a second window. When correction timing is detected and when correction timing is more likely to be accurate than the arrival timing, an estimation unit changes the correction timing to the arrival timing; when the arrival timing is more likely to be accurate than the correction timing, the estimation unit maintains the arrival timing.Type: GrantFiled: February 20, 2013Date of Patent: February 11, 2014Assignee: Sanyo Electric Co., Ltd.Inventor: Keisuke Higuchi
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Patent number: 8619786Abstract: Methods and apparatuses are provided for facilitating distributed transmissions among a plurality of access terminals for a transmission sequence. An access point may assign a predecessor transmitter device for each of a plurality of access terminals, and may transmit to each access terminal an instruction to follow a respective preceding transmission by the predecessor transmitter. An access terminal may receive the transmission including the instruction, and may monitor for and detect the preceding transmission. The access terminal may then transmit a transmission after the completion of an interframe space that may follow the detected preceding transmission.Type: GrantFiled: October 20, 2010Date of Patent: December 31, 2013Assignee: QUALCOMM IncorporatedInventor: Maarten Menzo Wentink
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Patent number: 8615032Abstract: Sub-microsecond time transfer in a GPS/GNSS receiver using a weak GPS/GNSS signal is provided. The digitized complex baseband signal and the generated PN code are cross-correlated for each code period so as to output a complex correlation value at each code epoch of the generated PN code, where a sequence of the output correlation values form a data stream representing the navigation message. Bit synchronization generates bit sync pulses at bit boundaries. The location of a target segment having a known sequence at a known bit location in the navigation message is detected by searching through a plurality of subframes and accumulating search results for the plurality of subframes. Transmission time of the target segment is determined from the detected location of the target segment, with a certain time ambiguity. Accurate local time is determined by solving the time ambiguity using approximate time obtained from an external source.Type: GrantFiled: January 22, 2013Date of Patent: December 24, 2013Assignee: Magellan Systems Japan, Inc.Inventor: Lawrence R. Weill
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Patent number: 8605847Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.Type: GrantFiled: March 9, 2011Date of Patent: December 10, 2013Assignee: LSI CorporationInventors: Mohammad Mobin, Mark Trafford, Ye Liu, Vladimir Sindalovsky, Amaresh Malipatil
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Patent number: 8594152Abstract: A communications network and method thereof include a base station controller configured to provide a repetition period of a primary synchronization channel to be equal to a predetermined integer value times a scrambling code length of the scrambling code of a common pilot channel. A user equipment in the network is configured to search for a known sequence comprising the primary synchronization channel to select a cell and a corresponding sub-frame/symbol timing from the selected cell.Type: GrantFiled: January 6, 2012Date of Patent: November 26, 2013Assignee: Amosmet Investments LLCInventors: Ulo Parts, Anders Ostergaard Nielsen, Kaj Jansen
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Patent number: 8576754Abstract: A time division duplex (TDD) base station having a code group out of N code groups includes circuitry configured to transmit a primary synchronization code along with a plurality of secondary synchronization codes. The plurality of synchronization codes are quadrature phase shift keying modulated and number less than (log2 N)+1. The plurality of synchronization codes are used to identify the code group of the TDD base station.Type: GrantFiled: March 5, 2012Date of Patent: November 5, 2013Assignee: InterDigital Technology CorporationInventors: Nadir Sezgin, Fatih Ozluturk
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Patent number: 8576961Abstract: A method for determining an overlap and add length estimate comprises determining a plurality of correlation values of a plurality of ordered frequency domain samples obtained from a data frame; comparing the correlation values of a first subset of the samples to a first predetermined threshold to determine a first edge sample; comparing the correlation values of a second subset of the samples to a second predetermined threshold to determine a second edge sample; using the first and second edge samples to determine an overlap and add length estimate; and providing the overlap and add length estimate to an overlap and add circuit.Type: GrantFiled: June 15, 2009Date of Patent: November 5, 2013Assignee: Olympus CorporationInventors: Haidong Zhu, Dumitru Mihai Ionescu, Abu Amanullah
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Patent number: 8571150Abstract: According to one embodiment, a frequency offset compensation apparatus includes a first estimation unit, a second estimation unit, a setting unit, a synthesis unit and a compensation unit. The first estimation unit estimates a first rotation. The second estimation unit estimates a second rotation. The setting unit sets a weighting factor for the second rotation to a first value if a received power is less than a threshold value, and sets the weighting factor for the rotation to a second value being smaller than the first value if the received power is not less than the threshold value. The synthesis unit calculates a compensation value. The compensation unit compensates for a frequency offset.Type: GrantFiled: March 1, 2012Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Seiichiro Horikawa, Koichiro Ban
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Patent number: 8559576Abstract: Embodiments of a synchronization circuit are described. This synchronization circuit includes multiple selectively coupled synchronization stages which are configurable to synchronize data and control signals between a first time domain and a second time domain, where the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain. Additionally, the synchronization circuit includes control logic, coupled to the synchronization stages, which is configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during the synchronization.Type: GrantFiled: August 18, 2008Date of Patent: October 15, 2013Assignee: Oracle America, Inc.Inventors: Tarik Ono, Mark R. Greenstreet
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Patent number: 8532234Abstract: The disclosure aims to implement an automatic frequency offset compensation of the frequency between emitter and receiver equipments, in radio frequency modules, with a frequency offset that can be larger than that the receiver can allow, without time loss and extra consumption. To solve this problem, the disclosure provides an automatic frequency offset compensation device comprising a reception front end, at least a filter, an I/Q demodulator for obtaining the I (In Phase) and Q (Quadrature) parameter, an automatic frequency control AFC unit for comparison of a received frequency with the real frequency of the equipment, and a microcontroller and a frequency synthesizer. In this device, the frequency offset is calculated by the AFC unit from the information given by the I/Q demodulator.Type: GrantFiled: January 11, 2011Date of Patent: September 10, 2013Assignee: Coronis, SASInventors: Laurent Maleysson, Fabien Bonjour
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Patent number: 8526554Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.Type: GrantFiled: March 9, 2011Date of Patent: September 3, 2013Assignee: Analog Devices, Inc.Inventor: Michael Hennedy
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Patent number: 8520789Abstract: The present invention relates to the communication field and discloses a method and an apparatus for implementing pulse synchronization, so that the control on a single-chip multi-channel device can be simplified. A method for implementing pulse synchronization includes: when a cycle count value corresponding to a reference symbol port of the multiple ports reaches a length of a predetermined pulse cycle, obtaining, by a microprocessor, cycle count values corresponding to the multiple ports; obtaining lengths of temporary synchronization cycles of the multiple ports according to the length of the predetermined pulse cycle and the cycle count values corresponding to the multiple ports; and sending the lengths of the temporary synchronization cycles to logic circuits corresponding to the multiple ports. Embodiments of the present invention are mainly applied in communication systems to output pulse symbols synchronously.Type: GrantFiled: May 18, 2012Date of Patent: August 27, 2013Assignee: Huawei Technologies Co., Ltd.Inventors: Yang Li, Matthew Leung, Tin Yau Fung
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Patent number: 8520787Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.Type: GrantFiled: March 9, 2011Date of Patent: August 27, 2013Assignee: Analog Devices, Inc.Inventor: Michael Hennedy
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Patent number: 8514920Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.Type: GrantFiled: July 26, 2012Date of Patent: August 20, 2013Assignee: LSI CorporationInventors: Christopher J. Abel, Parag Parikh, Vladimir Sindalovsky
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Patent number: 8428206Abstract: A method and system of fine timing synchronization for an OFDM signal. The OFDM signal is coarse timing synchronized, generating a synchronization sequence and a CFR (Channel Frequency Response). The synchronization sequence is removed. A correlation coefficient of the correlation between the CFR applied to a number of carriers and the number of carriers with different window shifts is calculated. The largest window shift corresponding to a downsampling factor is indicated by the lowest correlation coefficient greater than a threshold. The CFR is downsampled by the downsampling factor, and an inverse FFT is performed on the downsampled CFR with a reduced number of calculations reduced by the downsampling factor, transforming the CFR into a CIR. A fine timing synchronization position is determined from the CIR and is utilized by an FFT unit within an OFDM receiver to accurately receive OFDM symbols of the OFDM signal.Type: GrantFiled: March 5, 2009Date of Patent: April 23, 2013Assignee: NXP B.V.Inventor: Yan Li
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Patent number: 8416902Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.Type: GrantFiled: January 14, 2010Date of Patent: April 9, 2013Inventors: Ian Kyles, Eugene Pahomsky
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Patent number: 8412250Abstract: Methods and systems for slow associated control channel signaling are disclosed. An example method for securing communications in a mobile network disclosed herein comprises transmitting a first variant of a message of a first type on a first slow associated control channel (SACCH) before ciphering is started on the first SACCH, and after ciphering is started on the first SACCH, transmitting a second variant of the message of the first type on the first SACCH, and subsequently transmitting the second variant of the message of the first type on the first SACCH, wherein the subsequently transmitted second variant of the message of the first type is the next transmitted message of the first type on the first SACCH.Type: GrantFiled: March 22, 2012Date of Patent: April 2, 2013Assignee: Research In Motion LimitedInventors: David Hole, Eswar Kalyan Vutukuri
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Patent number: 8406218Abstract: A method of and an apparatus therefor searching a cell in a mobile station of a communication system in which a plurality of cells are grouped into a plurality of cell groups, and each cell group includes at least two cells. The method includes detecting a primary synchronization signal and a secondary synchronization signal from a received signal, and identifying a cell based on a combination of the primary synchronization signal and the secondary synchronization signal. The secondary synchronization signal is related to the cell group to which the mobile station belongs and the primary synchronization signal is related to the cell to which the mobile station belongs within the cell group.Type: GrantFiled: September 14, 2012Date of Patent: March 26, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Il-Gyu Kim, Hyeong-Geun Park, Young-Jo Ko, Kapseok Chang, Hyoseok Yi, Young-Hoon Kim, Seung-Chan Bang
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Patent number: 8391341Abstract: Sub-microsecond time transfer in a GPS/GNSS receiver using a weak GPS/GNSS signal is provided. The digitized complex baseband signal and the generated PN code are cross-correlated for each code period so as to output a complex correlation value at each code epoch of the generated PN code, where a sequence of the output correlation values form a data stream representing the navigation message. Bit synchronization generates bit sync pulses at bit boundaries. The location of a target segment having a known sequence at a known bit location in the navigation message is detected by searching through a plurality of sub-frames and accumulating search results for the plurality of subframes. Transmission time of the target segment is determined from the detected location of the target segment, with a certain time ambiguity. Accurate local time is determined by solving the time ambiguity using approximate time obtained from an external source.Type: GrantFiled: December 12, 2008Date of Patent: March 5, 2013Assignee: Magellan Systems Japan, Inc.Inventor: Lawrence R. Weill
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Patent number: 8374229Abstract: A method for the generation of a signal including a minimum of disturbances and noise is provided. A method for the detection of a signal including a minimum of disturbances and noise is also provided. An element of the signal is functionally dependent on at least one further element of the signal.Type: GrantFiled: February 26, 2008Date of Patent: February 12, 2013Assignee: Siemens AktiengesellschaftInventor: Jaroslaw Kussyk
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Patent number: 8369386Abstract: A receiver includes a receiving unit that receives a signal from a satellite, a frequency conversion-discretization unit that converts the signal received in the receiving unit into an intermediate frequency signal of a frequency bandwidth including 0 Hz, and discretizes the frequency-converted intermediate frequency signal with a predetermined sampling frequency, a filter unit that filters the discretized signal, which is output from the frequency conversion-discretization unit, through a predetermined filter, a synchronization acquisition unit that acquires synchronization of a spreading code in the discretized signal filtered by the filter unit, and a synchronization holding unit that holds the synchronization of the spreading code, which is acquired by the synchronization acquisition unit.Type: GrantFiled: June 16, 2010Date of Patent: February 5, 2013Assignee: Sony CorporationInventors: Hideki Takahashi, Katsuyuki Tanaka
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Patent number: 8363681Abstract: According to various embodiments of the disclosure, systems, methods and apparatuses are provided for using ranging to improve network efficiency. In particular, various embodiments of the disclosure provide ranging to improve local clock time synchronization. According to one embodiment, a method for synchronizing a plurality of nodes on a communication network is provided, comprising: exchanging local clock times between a first node and a second node over the communication network; performing a ranging method between the first and second nodes based on the local clock times exchanged between the first and second nodes, wherein the ranging method results in an estimated propagation delay between the first and second nodes; and adjusting the local clock times of the first and second nodes based on the estimated propagation delay, thereby resulting in a synchronized local clock time at the first and second nodes.Type: GrantFiled: October 15, 2009Date of Patent: January 29, 2013Assignee: Entropic Communications, Inc.Inventor: Arndt Mueller
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Patent number: 8358726Abstract: A source synchronous signal synchronization system includes a differential signal receiver; a tunable input delay element coupled to the receiver; an input serializer/deserializer (ISerDes) coupled to the tunable input delay; an alignment unit coupled to the ISerDes; and a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit.Type: GrantFiled: June 11, 2010Date of Patent: January 22, 2013Assignee: NEC Laboratories America, Inc.Inventors: Junquiang Hu, Tyrone Kwok, Ting Wang
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Patent number: 8339298Abstract: A digital counting circuit with multiple outputs is used to clock interlaced 16-bit data words into separate digital-to-analog converters in the correct sequence for each of eight hydrophone channels. The circuit utilizes a programmable memory to detect a synchronizing bit pattern.Type: GrantFiled: August 26, 2010Date of Patent: December 25, 2012Assignee: The United States of America as represented by the Secretary of the NavyInventor: James D. Hagerty
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Patent number: 8320508Abstract: A system including an estimation module, a processing module, and a control module. The estimation module is configured to generate a first set of channel estimates for a plurality of subcarriers of a received signal. The processing module is configured to generate a second set of channel estimates for the plurality of subcarriers, in which the second set of channel estimates are generated based on the first set of channel estimates. The control module is configured to estimate a preamble sequence in the received signal based on each of (i) the first set of channel estimates and (ii) the second set of channel estimates.Type: GrantFiled: August 22, 2011Date of Patent: November 27, 2012Assignee: Marvell International Ltd.Inventors: Jungwon Lee, Hui-Ling Lou
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Patent number: 8320360Abstract: A method and apparatus for transmitting a primary and secondary synchronization channel is provided herein. During operation a transmitter will transmit a primary synchronization channel (P-SCH) in a subframe and a secondary synchronization channel (S-SCH) in the subframe. The S-SCH is modulated by a complex exponential wave and scrambled with a scrambling code. In certain embodiments of the present invention the P-SCH comprises a GCL sequence or a Zadoff-Chu sequence and the scrambling code is based on the GCL sequence index of the P-SCH.Type: GrantFiled: December 5, 2006Date of Patent: November 27, 2012Assignee: Motorola Mobility LLCInventors: Masaya Fukuta, Hidenori Akita
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Patent number: 8306070Abstract: Certain aspects of a method and system for speed negotiation for twisted pair links using intelligent elastic first-in-first-out (E-FIFO) in fiber channel systems are disclosed. Aspects of a method may include determination of a priority level based on amount of data in at least one elastic FIFO (E-FIFO) buffer communicatively coupled to at least one of the fiber channel host devices. The E-FIFO buffer may be modified either by insertion or deletion of IDLE words or words from an order set based on the determined priority level. The data may be synchronously communicated between fiber channel host devices communicatively coupled via the twisted pair link based on the modified elastic buffer.Type: GrantFiled: July 24, 2006Date of Patent: November 6, 2012Assignee: Broadcom CorporationInventor: Ali Ghiasi
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Patent number: 8295304Abstract: When a signal-to-noise ratio affecting radio communication becomes sufficiently low, then the data transmission rate is responsively decreased in compensation. The signal-to-noise ratio of the communication link is thereby increased. Data for multiple different services is transmitted in data packets between two radios. By allocating one part, or time slot, of the data packet's payload to one service, and allocating another part, or time slot, of the data packet's payload to another service, communications sessions for multiple services can be maintained concurrently. Services are prioritized relative to each other. In case the signal-to-noise ratio becomes too low, data packet portions that are related to lower-priority services can be omitted from some data packets before those data packets are transmitted. Data remaining in the packet can be sent at a reduced data transmission rate without causing the quality of service for the remaining packets to fall below the minimum required level.Type: GrantFiled: December 29, 2008Date of Patent: October 23, 2012Assignee: Exalt Communications IncorporatedInventor: Peter Smidth
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Patent number: 8290094Abstract: Some embodiments disclosed herein relate to a method. In the method, a duration of a first synchronization pulse is measured. A fixed, predetermined number of ticks are equally spaced at a first time interval over the first sync pulse, regardless of the duration of the first synchronization pulse. A duration of a first data pulse is then measured by periodically incrementing a tick count value at the first time interval during the entire duration of the first data pulse. The tick count value at an end of the first data pulse is then correlated to a first digital value encoded on the first data pulse.Type: GrantFiled: January 18, 2010Date of Patent: October 16, 2012Assignee: Infineon Technologies AGInventors: Andreas Kolof, Dietmar König
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Patent number: 8284888Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.Type: GrantFiled: January 14, 2010Date of Patent: October 9, 2012Inventor: Ian Kyles
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Patent number: 8284872Abstract: A burst mode receiver including a CDR circuit that does not perform bit synchronization determination at a wrong position even when a burst signal waveform containing a distortion is input is provided. The burst mode receiver includes a CDR circuit for reproducing clock and data from a received signal, a bit synchronization determination circuit for determining whether the CDR circuit is in an optimum phase, a waveform distortion determination circuit for determining from the received signal whether there is waveform distortion, and a CDR output enable determination circuit for determining whether an output of the CDR circuit is valid or invalid. The CDR output enable determination circuit performs CDR output enable determination based on a bit synchronization determination result and a waveform distortion determination result.Type: GrantFiled: January 14, 2010Date of Patent: October 9, 2012Assignee: Hitachi, Ltd.Inventors: Jun Sugawa, Hiroki Ikeda, Masayoshi Yagyu
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Patent number: 8279986Abstract: Provided are: plural circuit components including a circuit component which constitutes a receiving unit receiving a signal sequence which is arranged so that a desired signal and a signal different from the desired signal are lined up in time series, the desired signal indicating desired data which includes at least one of text data, sound data, image data, and a computer program product; and an operating parameter changing unit which changes an operating parameter of at least one of the plural circuit components, during a period in which the receiving unit receives the signal different from the desired signal.Type: GrantFiled: February 26, 2009Date of Patent: October 2, 2012Assignee: Sharp Kabushiki KaishaInventor: Nobuyoshi Kaiki
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Patent number: 8275025Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.Type: GrantFiled: February 27, 2009Date of Patent: September 25, 2012Assignee: LSI CorporationInventors: Christopher J. Abel, Parag Parikh, Vladimir Sindalovsky
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Patent number: 8270545Abstract: Certain embodiments of the present disclosure relate to a method for tracking of a carrier frequency offset. A soft combined frequency tracking discriminator is proposed as a part of the closed loop structure that can provide fast tracking of the frequency offset in an initial pull-in mode, and can also track small residual frequency variance in a fine-tracking mode.Type: GrantFiled: March 1, 2009Date of Patent: September 18, 2012Assignee: QUALCOMM IncorporatedInventors: Junqiang Li, Madihally J. Narasimha, Je Woo Kim
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Patent number: 8238490Abstract: A method for determining a Doppler shift of a first signal is provided. First, a plurality of Doppler frequency hypotheses is combined to obtain a joint Doppler signal. The first signal is the correlated according to the joint Doppler signal and a plurality of code signals with phases corresponding to a series of code phase hypotheses to obtain a series of correlation results which are then examined to determine whether the Doppler shift does lie in the Doppler hypotheses. A fine Doppler search is then performed to determine the Doppler shift when the Doppler shift lies in the Doppler hypotheses.Type: GrantFiled: February 25, 2009Date of Patent: August 7, 2012Assignee: Mediatek Inc.Inventors: Hsin-Chung Yeh, Kuan-I Li
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Patent number: 8229052Abstract: An apparatus and method for transmitting/receiving an S-SCH in an Institute of Electrical and Electronics Engineers (IEEE) 802.16m wireless communication system are provided. A method for transmitting, by a transmitter, a Secondary Synchronization CHannel (S-SCH) in a communication system includes generating a sequence depending on a cell IDentification (ID), determining a subcarrier set comprising subcarriers to map the generated sequence, based on a Fast Fourier Transform (FFT) size and a segment ID, and mapping the generated sequence to the subcarriers of the determined subcarrier set.Type: GrantFiled: January 7, 2010Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Eun Park, Jae-Weon Cho, Seung-Hoon Choi, Chi-Woo Lim, Song-Nam Hong