Abstract: An asynchronous transfer mode type multimedia radiocommunication system including a transmitter and a receiver connected to the transmitter via an asynchronous transfer mode network and wherein accesses to two channel data which communicate by radio and have different levels of communication quality, are performed by the asynchronous transfer mode network. A separator of a transmitter separates input data into L-bit main channel data and one-bit sub channel data. A convolutional coder convolutionally codes the data. Further, a mapper maps the resultant binary information onto crossed I and Q channel axes according to the data by switching for each L bit of the main channel data, thereby enabling transmission of additive information corresponding to data of 1/L the transfer rate. Thereafter, a viterbi decoder of a receiver decodes the information. Further, a sub channel having arbitrary communication quality can be provided by arbitrarily selecting the value (L.sub.min .ltoreq.L) of an L bit.

Abstract: A 1:N divider 40 divides an input high rate data signal into N (N being 2 or greater integer) division data signals. Data transmission rate converters 70.sub.1 -70.sub.N for converting the transmission rate of each of the N division data signals. The respective N division data signals are transmitted through N transmission lines 30.sub.1 -30.sub.n. A multiplier 50 multiplies the transmitted N division data signals into a single high rate data signal.

Abstract: The invention relates to a system for digital broadcasting by satellite and including a link sending digital information to the satellite, the satellite retransmitting a broadcast multiplex. According to the invention, the link includes a plurality of individual transmitters each of which transmits a transmission signal at a first rate corresponding to at least one program, and wherein the satellite includes an onboard multiplexer module combining the transmission signals to form the transmission multiplex at a second rate higher than the first rate.

Abstract: A transmitter for transmitting a plurality of digital signals through a plurality of channels, the channels having a predetermined total allocated bitrate, includes a plurality of encoders each associated with one channel, a multiplexer for receiving the encoded digital signals and for transmitting the encoded signals as a stream of data, and operable for adjusting the distribution of the bitrate allocation between and among the encoded signals, and a processing device for providing an indication of a target quality and an actual quality for each channel and for causing the multiplexer to repeatedly adjust the distribution of the bitrate allocation in response to differences between the indicated actual quality and the indicated target quality for each channel so as to equalize differences between the actual and target quality across at least some of the channels.

Abstract: A digital signal multiplexing method and apparatus include statistically multiplexing packet signals which are transferred through first transmission lines having a first speed to a second transmission line having a second speed, the second speed being higher than the first speed. The method includes the steps of dividing the signal transmitted to the second transmission line through a plurality of logical transmission paths, distributing the packet signals to the plurality of logical transmission paths and transmitting on a packet unit basis, distributing the multiplexed packet signals which are statistically multiplexed to the second transmission line through receiving logical transmission lines corresponding to the plurality of logical transmission lines, and generating the received packet signals from the receiving logical transmission lines; the received packet signals corresponds to the first transmission lines.

Abstract: A method and apparatus for processing a plurality of facility datalinks is provided. In particular, synchronizers (14 and 16) receive multiple facility datalinks and synchronize them. These synchronized signals are transmitted to FDL state machine (18). FDL state machine (18) separately stores each of the facility datalinks in a memory (20). A processor (22) accesses the facility datalinks stored within memory (20) and initiates responses based on the accessed facility datalinks.

Abstract: A method and a circuit arrangement for combining several data channels with a transmission channel in which the carrier signal has at least two digital data signals, each with a different frequency, superimposed on it in terms of time. The superimposed signal is transmitted and received by a receiving device. The receiving device decodes the digital data signals and can pass them on, separately, to corresponding devices for further processing. The method and circuit arrangement may be advantageously used for data transmission between a motor vehicle and a fixed beacon. The data to be transmitted may contain traffic guidance data, or data for billing road use fees, for example.

Abstract: An integrated method for congestion control uses access regulator to control the admission of information from a communication device into a network according to a predetermined function characterized by a set of parameters. A node within the network sends a signal indicating a level of congestion in the node to the access regulator, and at least one of the parameters is adjusted in response to the signal. The parameter may additionally be adjusted according to other parameters which are selected according to stability and transient response criteria.

Abstract: A signal multiplexing apparatus using multiconnection, comprising an input signal interface circuit for inputting a DS1 (or DS1E) signal, a video signal and an ATM cell signal, an input signal processing multiport RAM having a plurality of ports for receiving data from the input signal interface circuit, an input signal control circuit for controlling the input signal processing multiport RAM, and an output signal address generation/multiplexing circuit connected to the input signal processing multiport RAM. The output signal address generation/multiplexing circuit reads data from the input signal processing multiport RAM and multiplexes the read data into a desired format.