Abstract: A remote enclosure houses multiple subsystems. A first subsystem is coupled to a central office over a high-speed communication channel such as an OC-3 channel. The first subsystem extracts a downstream message from a first embedded operations channel included in the high-speed communication channel. The first subsystem also, when the downstream message is targeted to a first unit included in the first subsystem, forwards the message to a unit that processes the message for the first unit. When the message is not targeted to any unit included in the first subsystem, the first subsystem forwards the downstream message to another subsystem housed within the remote enclosure via a second embedded operations channel included in a second communication channel. The second subsystem is subtended from the first subsystem and is connected thereto by the second communication channel.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: A method for the transmission of data in a synchronous digital hierarchy (SDH) network comprising the steps of transmitting to a node of the network a form of data signal from outside the network, converting the signal into a virtually concatenated information structure and transporting the signal through the network in the virtually concatenated information structure; means for carrying out the method and tributary cards arranged and configured to process signals received in contiguously concatenated form to convert them into virtually concatenated form for transfer across the network; thus providing for data transmitted in high-bandwidth, contiguously concatenated signals (ie VC-4-4c) to be transported across a SDH network, not itself capable of carrying contiguously concatenated signals.

Abstract: Systems and methods for hierarchical link aggregation are disclosed. A system for hierarchical link aggregation may include a network interface having a plurality of physical ports. A first plurality of the physical ports may be configured as member ports of a first link aggregation group (LAG). A second plurality of the physical ports may be configured as member ports of a second LAG. The first LAG and second LAG may be configured as member logical ports of a third LAG.

Abstract: A method of applying an order N fast Hadamard transform (FHT) of a vector U using a mixed radix FHT in a receiver of a communication system, the N a positive integer, when receiving signals from a transmitter over a channel and generating the vector U. The method includes, in an FHT module of a decoder in the receiver, planning n stages of the mixed radix FHT, where the n is a positive integer, each stage defined by corresponding logic, decomposing the order N FHT into n low order FHTs, such that N=KnKn?1 . . . K1 and U=UKnKn?1 . . . K1, where the K is a positive integer, calculating, via the corresponding logic, each low order FHT at each stage, wherein input vectors of a subsequent stage are calculated in a proceeding stage, and reconstructing, by the decoder, calculated results of the each low order FHT to form an output vector output the decoder.

Abstract: A mobile device receives RF signals from base stations in a location scanning region. Each of the base stations includes a plurality of distributed transceivers and each distributed transceiver includes an independently configurable antenna array. The mobile device generates and communicates channel measurements for the received radio frequency signals to a remote location server (RLS). The RLS configures, utilizing one or more channel transmit settings, the independently configurable antenna array for the distributed transceivers in the location scanning region, to transmit the RF signals. The RLS determines a coarse position estimate for the mobile device for the sub-regions within the location scanning region and applies different signature functions to the determined coarse position estimate for the sub-regions to generate corresponding sub-regions position estimates.

Abstract: A mobile device receives RF signals from base stations in a location scanning region. Each base station includes a plurality of distributed transceivers and each distributed transceiver includes an independently configurable antenna array. The mobile device generates and communicates channel measurements for the received radio frequency signals to a remote location server (RLS). The RLS configures, utilizing one or more channel transmit settings, the antenna array for the distributed transceivers to transmit the RF signals. The remote location server selects a subset of the communicated channel measurements for determining a position estimate for the mobile device having a desired resolution. The mobile device may receive the determined position estimate from the remote location server. The location scanning region may be determined based on GPS and/or WLAN positioning.

Abstract: A mobile device receives RF signals from base stations each having a plurality of distributed transceivers. Each distributed transceiver comprises an independently configurable antenna array for transmitting the radio frequency signals to the mobile device. The mobile device determines channel characteristics for the received RF signals, generates channel measurements for the received RF signals, and receives a position estimate for the mobile device from a remote location server (RLS). The corresponding transmit diversity configurations are determined by the RLS and applied to the base stations for the (1) channel measurements for mobile device and (2) channel measurements at scanned locations in a location scanning region, which are both calculated by the RLS. The RLS weights the generated channel measurements utilizing one or more scaling factors, which are utilized to determine a relative reliability and contribution of the generated channel measurements.

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: A mobile device receives signals from base stations each with multiple distributed transceivers. Each distributed transceiver may operate at different carrier frequencies. Each distributed transceiver is equipped with an independently configurable antenna array handling transmissions of the radio frequency signals to the mobile device. The mobile device generates channel measurements for the received signals, and subsequently receives a position estimate from a remote location server. The location server determines corresponding transmit diversity configurations applied to the base stations for conducting the channel measurements for the mobile device, and channel measurements at scanned locations in a location scanning region. The location server selects and utilize a signature function to calculate the position estimate for the mobile device over the transmit diversity configurations.

Abstract: A method for generating a frame signal includes monitoring a first frame signal and obtaining a first parameter based on the monitoring result; setting a second parameter based on the type of the first frame signal; when the first frame signal is being input, generating a second frame signal with a bit rate different from that of the first frame signal by determining data and stuff byte positions based on the first parameter and performing frame processing on data and stuff bytes corresponding to the first frame signal based on the determined data and stuff byte positions; and when the first frame signal is not being input, generating the second frame signal by determining the data and stuff byte positions based on the second parameter and performing the frame processing on data and stuff bytes corresponding to a maintenance signal based on the determined data and stuff byte positions.

Abstract: A data processing method for a wireless communication system with a plurality of terminals, an intermediate device and a service network, the method comprising: sending a plurality of machine type communication (MTC) data flows from the plurality of terminals to the intermediate device; performing a data multiplexing operation by the intermediate device on the plurality of machine type communication data flows to generate a multiplexed data flow; and the service network receiving the multiplexed data flow.

Abstract: Systems and methods for de-combining a single combined data stream into a plurality of original data streams, where each original data stream has its own timing information, and passing respective original data steams to, e.g., one or more DVB-T modulators for broadcast into, e.g., a single frequency network. The original data streams and the single combined data stream may be, e.g., MPEG-compliant data streams.

Abstract: A transmitting system, a receiving system, and a method of processing broadcast signals are disclosed.

Abstract: A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.

Abstract: A new process called a vector approximation graph (VA-graph) leverages a tree based vector quantizer to quickly learn the topological structure of the data. It then uses the learned topology to enhance the performance of the vector quantizer. A method for analyzing data comprises receiving data, partitioning the data and generating a tree based on the partitions, learning a topology of a distribution of the data, and finding a best matching unit in the data using the learned topology.

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: Described herein is technology for, among other things, natural network coding in a wireless mesh network. The technology involves wireless mesh network systems, methods and devices based on the natural network coding. By encoding signals in their natural forms using their channel strengths, more efficient transmission of signals is possible in the wireless mesh network.

Abstract: Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The system maps a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and based on at least one rate associated with a node not in the set. The packets are processed in one or more processor cores including the mapped processor core according to the hierarchy.

Abstract: In accordance with an aspect of the present invention, a corresponding list of muxes is maintained for each combination of a peripheral and a mux option. The list is then retrieved to program the required muxes to connect the communication paths from a peripheral on the corresponding mux option, based on which the list is retrieved. In an embodiment, the information is maintained in the form of a table, with each entry storing the data corresponding to a mux and mux option. The entries are linked by appropriate pointers to form the linked list.

Abstract: A transmitter/receiver system for high data transfer in a wireless communication system includes a physical layer processor that comprises an FEC coder, a demultiplexer and a plurality of modem processors. The FEC coder applies error correction codes to the high data rate signal. Thereafter, the demultiplexer distributes portions of the coded high data rate signal to the modem processors. Each modem processor processes its respective portion of the coded signal for transmission in an independent channel.

Abstract: Network management information (NMI) contained in a first set of byte locations of a received frame is relocated to a second set of byte locations of another frame. The NMI is then transported through network elements using the second set of byte locations until the NMI is to be transported to a compatible network element, which can understand the NMI. At which time, the NMI is relocated back to the first set of byte locations of frames destined for the compatible network element. The relocation of the NMI from a first set of byte locations to a second set of byte locations allows the NMI to be transparently transported through incompatible network elements.

Abstract: A method for the transmission of data in a synchronous digital hierarchy (SDH) network comprising the steps of transmitting to a node of the network a form of data signal from outside the network, converting the signal into a virtually concatenated information structure and transporting the signal through the network in the virtually concatenated information structure; means for carrying out the method and tributary cards arranged and configured to process signals received in contiguously concatenated form to convert them into virtually concatenated form for transfer across the network; thus providing for data transmitted in high-bandwidth, contiguosly concatenated signals (ie VC-4-4c) to be transported across a SDH network, not itself capable of carrying contiguously concatenated signals.

Abstract: A method, apparatus and system for employing an enhanced port multiplier are provided. In one embodiment, a network host is configured to be coupled with a port multiplier in a network. The port multiplier is configured into being cascaded into being coupled with a plurality of port multipliers and a plurality of network devices.

Abstract: Multiplexers are basic components widely used in VLSI designs. Switching activities of a multiplexer are one of the most important factors of power consumption. A multiplexer may have some sub-multiplexers. An extra dynamic controller is applied in the present invention to reconfigure control signals for decreasing switching activities of the composed sub-multiplexers. Thus, the power consumption of the multiplexer is reduced to achieve higher power efficiency.

Abstract: A process to transfer a Time division Multiplexing (TDM) frame (1) over a MPLS network (2), the frame including a plurality of time slots (TS1, TS2, TS3) with specific bandwidths, including—identifying the corresponding bandwidth of the time slots of the frame (1);—creating and reserving into the MPLS network (2) for each time slot (TS1,TS2,TS3) of the frame a corresponding label switched path (LSP1, LSP2, LSP3) having a bandwidth substantially identical to the bandwidth of the time slot;—and routing each time slot (TS1, TS2, TS3) over the MPLS network (2) through a corresponding label switched path (LSP1, LSP2, LSP3).

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: An overhead processor processes overhead bytes in a stream of Synchronous Optical Network (SONET) frames in multiple levels. In one embodiment, the overhead processor includes three stages. A first stage provides access for external processing of a first set of overhead bytes in the stream of SONET frames. A second stage is programmable to process a second set of overhead bytes in the stream of SONET frames. A third stage processes a third set of overhead bytes in each frame in the stream of SONET frames.

Abstract: A method for multiplexing digital data, wherein a packet of digital data is simultaneously sent from front to rear and from rear to front. Additionally, a method for multiplexing digital data, wherein a packet of digital data is simultaneously sent from the beginning of the packet towards the end and from the end towards the beginning. Additionally, a method for multiplexing digital data, wherein simultaneously a packet of digital data is sent and the same packet is sent backwards.

Abstract: A network interface includes N input lanes that receive data symbols and idle symbols. A substitutor module periodically replaces an idle symbol on each input lane with a corresponding alignment symbol to form an alignment group. M interleaver modules each interleave a portion of the data symbols and alignment symbols onto a corresponding transmit lane based on an interleaving pattern that provides each transmit lane with N/M alignment symbols from the alignment group. M is an integer greater than 1 and N is greater than M. In some features the substitutor module periodically replaces successive idle symbols on each lane with alignment symbols to form corresponding alignment groups. An interleaver module interleaves the data symbols and alignment groups onto M transmit lanes according to an interleaving pattern that provides each transmit lane with one of the alignment groups.

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract: A method and system for interconnecting multiple distributed components in a communication network is provided. The design includes a multiple order cross connection fabric employed to interconnect multiple orders of data with at least one distributed component in the communication network. The design may further include at least one order of path termination and adaptation connection, where the at least one order of path termination and adaptation connection providing an interface between the multiple order cross connection fabric and a data management system. The design may be implemented in a SONET/SDH environment.

Abstract: Network management information (NMI) contained in a first set of byte locations of a received frame is relocated to a second set of byte locations of another frame. The NMI is then transported through network elements using the second set of byte locations until the NMI is to be transported to a compatible network element, which can understand the NMI. At which time, the NMI is relocated back to the first set of byte locations of frames destined for the compatible network element. The relocation of the NMI from a first set of byte locations to a second set of byte locations allows the NMI to be transparently transported through incompatible network elements.

Abstract: To achieve coordination during generation of a plurality of mixed media streams, there is suggested a method of generating a mixed media stream (62-64) from input media streams (40-50) having payload data elements and related identifiers. The method comprises the step (S12) of aligning the input media streams (40-50) according to a pre-specified relation between identifiers in different input media streams (40-50) before generating the mixed media stream.

Abstract: The invention relates to a system and method for the generation of television channels and which allows the generation of the same by the processing and selection of designated packets of data from multiple data transport streams, which each transport stream including numerous packets of data. In each transport stream the packet of data is identified by the allocations of a packet identification code (PID) and each is held in the transport packet which is transmitted as part of each transport stream. In accordance with the invention, and in order to prevent errors and inaccurate packet selection, a Transport Stream Identification Code (TSID) is allocated to each of the transport streams of data received. Typically the TSID is located in the transport packet for each transport stream of data. In the selection of a packet of data, the appropriate TSID is referred to identify the appropriate transport stream and the PID then referred to identify the packet of data from that transport stream.

Abstract: In one embodiment, a 10 Giga-bit Ethernet conversion system is provided that is operable to be inserted in 10 Gigabit optical fiber Ethernet systems, wherein each optical fiber Ethernet system includes an electrical-to-optical interface presenting electrical signals to an optical interface for converting the electrical signals to optical signals, the electrical signals being organized into a plurality of channels, wherein each channel carries Ethernet idle characters between data frame transmissions.

Abstract: A switching arrangement and method allow signals received by a communications platform to be directed to an appropriate interface depending on the type of signal received by an input signal line. A switch element having a switch is responsive to a logic control system that is itself responsive to signals that the input signal line receives. The logic control system may be responsive to any detectable identification, property or quality of the received signal. When the input signal line receives an analog signal, the logic control system detects that the signal is analog and causes the switch element to connect the input signal line to the analog interface with the switch. When the input signal line receives a digital signal, the logic control system detects that the signal is digital and causes the switch element to connect the input signal line to the digital interface with the switch.

Abstract: An apparatus defines interleave-processing segments to be interleaved in a backward direction relative to a flow direction of bit streams. The segments are defined every time the segments, ILVU-BR, -CR, -DR are successfully set for each of the respective bit streams, VOB-B-VOB-D. In setting the segments for each of the respective bit streams, the segment of one bit stream is set to follow the set segment of other bit stream. When an amount of data of the rest of the bit streams is insufficient to form the final segment, the rest data is distributed among the segments that have been already defined. The defined segments are arranged in the flow direction of the bit streams.

Abstract: An overhead processor processes overhead bytes in a stream of Synchronous Optical Network (SONET) frames in multiple levels. In one embodiment, the overhead processor includes three stages. A first stage provides access for external processing of a first set of overhead bytes in the stream of SONET frames. A second stage is programmable to process a second set of overhead bytes in the stream of SONET frames. A third stage processes a third set of overhead bytes in each frame in the stream of SONET frames.

Abstract: A multi-stage bit stream multiplexer that divides multiplexing functions between two or more integrated circuits. The first integrated circuit receives 16 bit streams to produce 4 output bits streams with a nominal data rate of 10 GBPS. A second integrated circuit multiplexes the 4 streams and to a bit stream with a data rate of 40 GBPS. The first IC is made in a standard CMOS process while the second IC is made using processes that support higher switching rates. The first IC produces a source-centered double data rate forward transmit clock from a reference clock selectable from either a crystal oscillator, a voltage controlled oscillator using a loop clock from the receive side of the bit stream multiplexer or a reverse clock generated by the second IC. The reverse clock can be selected as the source of the reference either by default, or in response to a specific condition.

Abstract: A wireless communications system includes a shared TDM data channel for communications in different time slots with respective mobile stations (MSs), as well as dedicated channels. A first medium access control (MAC) multiplexing sublayer, provided in a base station controller, maps information of logical channels for communications services to the communications channels. A second MAC multiplexing sublayer maps information, mapped to the shared data channel in the first MAC multiplexing sublayer, to respective data units for communication in respective TDM time slots of the shared channel. The second MAC multiplexing sublayer handles scheduling, adaptive modulation and coding, and automatic retransmission of information on the shared data channel, as well as shared control channels for the shared data channel and channel quality feedback and data acknowledgement channels from the MSs.

Abstract: A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adapted to select signals from the plurality of devices. A second multiplexer circuit may receive the selected signals from the first multiplexer circuit and transmit the selected signals to chosen ones of the plurality of devices.

Abstract: A system for intercommunicating data traffic provides the capability to connect external interfaces that use one third or less of the OC3 bandwidth capacity in a reduced bandwidth mode that reduces system cost, while automatically switching to the full bandwidth mode to allow connection to external interfaces that utilize the full OC3 bandwidth capacity.

Abstract: The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: A flexible and expandable system bus for connecting traffic mapping devices to SONET/SDH framing devices. The system bus passes control signals generated by a master device to multiple tributaries to orient them relative to a SONET/SDH frame. These control signals obviate the need for each tributary to perform its own SONET/SDH reconstruction and framing using the A1/A2 bytes. The control signals synchronize the tributaries to a common clock cycle, indicate during which clock cycles the tributary can add or drop data relative to the system bus, and an interface identification signal that transmits values on the system bus. The tributaries monitor the values on the system bus, and when the value associated with each tributary appears on the bus, and the system bus indicates that the current clock cycle is within the SPE portion of the SONET/SDH frame, the tributary adds or drops data relative to the system bus.

Abstract: A method for the transmission of data in a synchronous digital hierarchy (SDH) network comprising the steps of transmitting to a node of the network a form of data signal from outside the network, converting the signal into a to a virtually concatenated information structure and transporting the signal through the network in the virtually concatenated information structure; means for carrying out the method and tributary cards arranged and configured to process signals received in contiguously concatenated form to convert them into virtually concatenated form for transfer across the network; thus providing for data transmitted in high-bandwidth, contiguously concatenated signals (ie VC-4-4c) to be transported across a SDH network, not itself capable of carrying contiguously concatenated signals.

Abstract: The present invention provides methods and apparatus for statistical multiplexing of a large number of data streams. A plurality of encoders are associated with each first stage multiplexer. Bandwidth allocation among all encoders is controlled by a second stage multiplexer. A bandwidth request message is communicated from each the encoders to the second stage multiplexer. The second stage multiplexer allocates available bandwidth based on the bandwidth request messages. The second stage multiplexer then communicates an allocated bandwidth message to each encoder. Each encoder encodes a data stream in accordance with its allocated bandwidth to provide an encoded data stream. A plurality of the encoded data streams are multiplexed at each first stage multiplexer to provide a multiplexed data stream at a constant data rate. The second stage multiplexer mutiplexes the multiplexed data streams from the first stage multiplexers to provide a multiplexed transport stream.

Abstract: A data transmission apparatus using a virtual concatenated path in an SDH transmission system is capable of engaging one or more extra paths by an automated sequence execution to meet a traffic requirement that is higher than usual but up to a maximum speed of a user who is usually assigned virtual concatenated paths in a number smaller than capable of transmitting the maximum traffic.

Abstract: Systems and methods, consistent with the present invention, provide a high-speed line interface for networking devices. Such an interface may be used in networking devices, such as routers and switches, for receiving data from, and transmitting data to, high-speed links, such as those lines carrying data at rates of 2.5 Gbit/sec, 10 Gbit/sec, and 40 Gbit/sec and more. In a preferred embodiment, the interface deserializes data from an incoming data stream onto a multi-line bus so that the data may be processed at a lower clock speed. Packets are extracted from the data on the multi-line bus and distributed among a plurality of switching/forwarding modules for processing.

Abstract: A method and system for interconnecting multiple distributed components in a communication network is provided. The design includes a multiple order cross connection fabric employed to interconnect multiple orders of data with at least one distributed component in the communication network. The design may further include at least one order of path termination and adaptation connection, where the at least one order of path termination and adaptation connection providing an interface between the multiple order cross connection fabric and a data management system. The design may be implemented in a SONET/SDH environment.