Abstract: This application relates to display panels, methods of driving the same, and display devices. The display panel includes: a first pixel circuit and a demultiplexing circuit. The first pixel circuit includes a first reset circuit, a first data writing circuit, and a first drive circuit. A first terminal of the first reset circuit is connected to a first terminal of the first drive circuit. A second terminal of the first reset circuit is connected to a first multiplexing signal line. A control terminal of the first drive circuit is connected to a first terminal of the first data writing circuit. A second terminal of the first data writing circuit is connected to the first multiplexing signal line. The demultiplexing circuit includes a first control circuit and a second control circuit. A first terminal of the first control circuit is connected to the first multiplexing signal line. A second terminal of the first control circuit is used for receiving a reset signal.

Abstract: A display device includes a substrate including a display area and a peripheral area, a pixel area, a data driver, a data divider, and coupling lines that couple the data driver to the data divider. The pixel area includes first pixel lines in a first area of the display area and coupled to first area data lines, and second pixel lines disposed in a second area of the display area and coupled to second area data lines. The data driver outputs data signals corresponding to the first and second pixel lines. The data divider includes first selectors that transfer the data signals corresponding to the first pixel lines to the first area data lines, and second selectors that transfer the data signals corresponding to the second pixel lines to the second area data lines. A distance between adjacent second selectors is shorter than a distance between adjacent first selectors.

Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.

Abstract: An ethernet-based communication system is provided. The communication system comprises: a first unit configured to generate a reference clock signal by using an input first ethernet signal, multiplex the first ethernet signal and a second ethernet signal in response to the reference clock signal, and output the multiplexed ethernet signals; a second unit configured to generate the reference clock signal by using the multiplexed ethernet signals, separate the second ethernet signal from the multiplexed ethernet signals in response to the reference clock signal, and output the first ethernet signal; and a transmission medium for connecting the first and second units and transmitting the multiplexed ethernet signals from the first unit to the second unit.

Abstract: An extended wireless access point may have many distributed radio units connected to associated processing units via a radio transmission network comprising commodity switches controlled by one or more network controllers. The one or more network controllers may use a load balancing algorithm to select a processing unit to process a signal received by a distributed radio unit. The radio units may receive a wireless signal, and generate compressed samples of the wireless signal for transport via the radio transmission network and processing by a selected processing unit. Similarly, a processing unit may generate and transmit via the radio transmission network compressed samples for decompression and transmission by a radio unit.

Abstract: A plurality of intelligent device systems for use with a wideband signal distribution network, and methods for transmitting digital information and receiving digital and non-digital information onto and off of an RF carrier through a wideband signal distribution network, are disclosed. The intelligent device systems provide networks of intelligent devices that modulate and demodulate digital video, IP video/data/voice and digital wireless onto, and off of, a wideband signal distribution system, such as an analog carrier system, using existing EIA/TIA 568 standard wiring infrastructure. The methods modulate and demodulate digital video, IP video/data/voice and digital wireless onto, and off of, a wideband distribution system, such as an analog carrier system, and separate IP portions from non-IP portions.

Abstract: A plurality of intelligent device systems for use with a wideband signal distribution network, and methods for transmitting digital information and receiving digital and non-digital information onto and off of an RF carrier through a wideband signal distribution network, are disclosed. The intelligent device systems provide networks of intelligent devices that modulate and demodulate digital video, IP video/data/voice and digital wireless onto, and off of, a wideband signal distribution system, such as an analog carrier system, using existing EIA/TTA 568 standard wiring infrastructure. The methods modulate and demodulate digital video, IP video/data/voice and digital wireless onto, and off of, a wideband distribution system, such as an analog carrier system, and separate IP portions from non-IP portions.

Abstract: Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined signal. In an aspect, the aggregation component is additionally configured for reformatting and/or combining the plurality of first signals and at least one second signal to generate the combined signal. In another aspect, a receiver component is configured for generating a pseudo signal at a data rate of the combined signal. In yet another aspect, a de-aggregation component is configured for recovering the plurality of first signals and/or the at least one second signal from the pseudo signal.

Abstract: Circuits comprising an asynchronous programmable interconnect with fan out support that include a multi-port switch and a first and second buffer-switch circuit, and methods of forming such circuits, are provided. Additional circuits and methods are disclosed.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract: An Ethernet physical layer (PHY) module is provided with a method for transceiving between a 10GBASE-R client interface and a 100G attachment interface. On each of ten client interface logical lanes a 10GBASE-R signal is accepted. Each 10GBASE-R logical lane is demultiplexed into two 5 gigabit per second (Gbps) pseudo 100GBASE-R logical lanes, creating a total of twenty pseudo 100GBASE-R logical lanes. The pseudo 100GBASE-R logical lanes are arranged into n groups of 20/n pseudo 100GBASE-R logical lanes. Further, the pseudo 100GBASE-R logical lanes from each group are arranged into a 100G attachment logical lane. Finally, a 100G attachment logical lane is transmitted at an attachment interface on each of n physical lanes. In the reverse direction, each of n physical lanes accepts a 100G attachment logical lane at the attachment interface, and a de-aggregation process supplies a 10GBASE-R signal on each of ten client interface logical lanes.

Abstract: A user equipment (UE) performs a transform domain (DFT) based method to detect the cyclic prefix (CP) length that is being used by a base station for cellular communications. The detected CP length is then used to reduce the amount of time required to complete the synchronization and cell search procedures. In particular, the UE uses the detected CP length information to obtain Cell Identification parameters (NID1, NID2) along with information including a Maximum energy Tap location and a reference signal receive power (RSRP) while completing the synchronization and cell search procedures.

Abstract: A system and method for receiving a plurality of pilot tones, generating an analytic signal in a frequency domain, the analytic signal including frequency components that when converted to a time domain include a preamble having a first half containing only non-zero data and a second half containing only zero data, converting the analytic signal from the frequency domain to the time domain, resulting in the preamble having the first half containing only non-zero data and the second half containing only zero data, generating a cyclic prefix based on the second half of the preamble, and attaching the cyclic prefix to the preamble to form a pilot signal, the cyclic prefix including only zero data.

Abstract: A method for adapting the rates of a certain number of asynchronous HDLC channels (15) to a single clock domain suited for interfacing with an HDLC processor (13) through a synchronous pseudo-TDM interface (14) in which the HDLC channels are multiplexed in time and vice versa in the opposite direction. In one direction the algorithm is based on the writing of the HDLC channels in a dedicated buffer (17) and in reading these buffers with a common synchronous clock just above the expected maximum HDLC rate. The under-run condition is avoided by inserting neutral information between the end byte and the start byte of the HDLC packets when this is suggested by the buffer fill monitoring function. A simple function to locate the first and last bytes of each HDLC packet read by the buffer is hence used in combination with the buffer fill monitoring function.

Abstract: A method and system for multiplexing data signals is provided. A first circuit is operable to generate a plurality of serialized data signals and is operable to adjust a phase of at least one of the serialized data signals to adjust bit and byte alignment. A second circuit is coupled to the first circuit to receive the plurality of serialized data signals from the first circuit. The second circuit has a multiplexer operable to generate a multiplexed output signal from the received serialized data signals. The first circuit is further coupled to the second circuit by a back channel operable to carry information regarding bit alignment and byte alignment of the received serialized data signals.

Abstract: Systems and methods for de-combining a single combined data stream into a plurality of original data streams, where each original data stream has its own timing information, and passing respective original data steams to, e.g., one or more DVB-T modulators for broadcast into, e.g., a single frequency network. The original data streams and the single combined data stream may be, e.g., MPEG-compliant data streams.

Abstract: A transmitting system, a receiving system, and a method of processing broadcast signals are disclosed.

Abstract: This document describes tools useful in relaying a data stream from a data device to a network tunnel, such as by injecting in-band control messages without impacting a data rate. For example, the tools may receive data packets on a first link and then relay the data packets to a data device on a second link. While doing so, the tools may periodically free an amount of link time by reducing the length of the relayed data packets by reducing the length of a header of each data packet. The tools may then consume the freed link time by sending a control message on the second link to the data device.

Abstract: A network terminal includes an operating system on which a plurality of user environments can run in parallel, a plurality of calling units corresponding to the plurality of user environments respectively, and a plurality of cooperative units corresponding to the plurality of user environments respectively. Priorities different from one another is assigned to the plurality of user environments respectively. Each calling unit is configured to convert a first telephone signal received from an interface and a second telephone signal received from an IP telephone terminal so that an IP telephone communication is performed between the interface device and the IP telephone terminal. Each cooperative unit is configured to communicate the interface with the corresponding calling unit in response to a calling request received from the IP telephone terminal.

Abstract: A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.

Abstract: A plurality of intelligent device systems for use with a wideband signal distribution network, and methods for transmitting digital information and receiving digital and non-digital information onto and off of an RF carrier through a wideband signal distribution network, are disclosed. The intelligent device systems provide networks of intelligent devices that modulate and demodulate digital video, IP video/data/voice and digital wireless onto, and off of, a wideband signal distribution system, such as an analog carrier system, using existing EIA/TIA 568 standard wiring infrastructure. The methods modulate and demodulate digital video, IP video/data/voice and digital wireless onto, and off of, a wideband distribution system, such as an analog carrier system, and separate IP portions from non-IP portions.

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: A telephony system and method is provided that reduces delay and provides better utilization of upstream bandwidth in delivering packet telephony services to a plurality of subscriber lines via a cable modem system. An exemplary system includes a plurality of voice processing modules, a host processor, and a buffer. Each voice processing module receives digital voice signals from a separate set of subscriber lines, compresses the digital voice signals to generate a voice packet, and transfers the voice packet to the buffer. The host processor then assembles a packet by concatenating the voice packets and transmits the assembled packet for delivery over a data network. Because the plurality of voice processing modules process the voice packets in parallel, delay is reduced in the assembly and transmission of the assembled packet.

Abstract: A subscriber platform according to various aspects of the present invention, includes an antenna and a receiver coupled to the antenna. The subscriber platform is operated by a subscriber. A method performed by the subscriber platform includes, in any practical order: (a) receiving non-redundant information on several channels, each channel associated with a direction of the antenna and a frequency for receiving information; (b) aggregating the information into a sequence; and (c) displaying a presentation in accordance with the sequence.

Abstract: First and second transmission links are established with a remote station. An information signal is encoded to provide an encoded information signal having more bits than the information signal. First and second transmission signals are provided wherein each transmission signal has bits selected from the encoded information signal. Each of the first and second transmission signals is transmitted to the remote station by way of a respective one of the first and second transmission links. The remote station receives and combines the first and second transmission signals transmitted by the remote station to provide a combined encoded signal. The combined encoded signal is decoded by the remote station to provide the information signal. The first and second transmission links can be formed between the remote station and a single base station or between the remote station and two separate base stations.

Abstract: In a packet transmission device and control method thereof which can improve the transmission rate of a packet without adding a high speed user data-conversion card, when packet data is inputted through a single arbitrary channel among a plurality of channels, from among a predetermined number of low speed user data-conversion cards provided common to the plurality of channels, the low speed user data-conversion cards by a number corresponding to a ratio between an output transmission rate of the low speed user data-conversion card and an input transmission rate of the packet data are extracted. The packet data is sequentially and cyclically distributed to the low speed user data-conversion cards extracted. Predetermined length user data outputted from the low speed user data-conversion cards are converted into a frame of HSDPA (High Speed Downlink Packet Access) system and multiplexed into a single channel HS-DSCH (High Speed Downlink Shared Channel) to be outputted.

Abstract: An integrated apparatus is disclosed that can directly connect to a portable digital video camera and can record uncompressed video and audio data, along with associated metadata, in the field and elsewhere. Most preferably, the integrated apparatus includes a removable, recordable, reusable digital magazine that may be mounted. Most preferably, the integrated apparatus also supports a variety of input and output formats, and the apparatus may be easily connected to other computing systems, either directly or through network connections, wired or wireless. The digital magazine can be mounted in a variety of docking stations and can be directly connected to a network, allowing the video and audio data to be easily stored and transferred.

Abstract: System and methods are provided for multiplexing digital data. In accordance with certain implementations, a method is provided that includes coordinating transmission of digital data elements of a packet including digital data elements arranged 1 . . . n. The coordinating step may include transmitting a first stream of data elements stored in memory, starting with data element 1 of the packet and proceeding upward through the data elements of the packet in sequential order, and transmitting a second stream of data elements stored in the memory, starting with data element n of the packet and proceeding downward through the data elements of the packet in sequential order, wherein transmitting of the first stream and the second stream is attempted to be performed during the same time. The method may also include terminating any sending of the first and second streams of data elements when the entire packet has been received.

Abstract: A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmission from among the multiple scheduled USB transmissions. A programmable storage element controls the selector to select the one arbiter. In one embodiment, at least a first arbiter prioritizes header/data packets higher than link commands, and at least a second arbiter prioritizes link commands higher than header/data packets. In one embodiment, at least one arbiter prioritizes flow control and power management link commands higher than header/data packets. In one embodiment, at least a first of the arbiters prioritizes USB LGO_Ux link commands higher than USB LAU/LXU link commands, and at least a second arbiter prioritizes USB LAU/LXU link commands higher than USB LGO_Ux link commands.

Abstract: Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator (VCO) connected to the PSC generates a clock signal. The clock signal controls the frequency of the signal. The CDR circuit also includes a phase adjustment signal generator connected to the PSC for generating a phase adjustment signal. The phase adjustment signal controls the phase of the signal.

Abstract: Systems and methods for conveying multiple low-bit-rate data streams over a data transport medium which is configured to transport data in a single, high-bit-rate data stream. In one embodiment, a plurality of low-bit-rate signals are received and a corresponding data rate is determined. Each of the signals is formatted in frames comprising a payload and overhead data. The high-bit-rate signal is also formatted in frames comprising a payload and overhead data, but the frames (including payload and overhead) contain more bits than those of the low-bit-rate frames. The payloads of the low-bit-rate frames are mapped into the payloads of the high-bit-rate frames. The overhead and timing data of the low-bit-rate frames are mapped into the unused portion of the overhead of the high-bit-rate frames. After the high-bit-rate signal is transported, the payload, overhead and timing data of each of the low-bit-rate signals is extracted, and the corresponding signals are reproduced.

Abstract: Multiplexers are basic components widely used in VLSI designs. Switching activities of a multiplexer are one of the most important factors of power consumption. A multiplexer may have some sub-multiplexers. An extra dynamic controller is applied in the present invention to reconfigure control signals for decreasing switching activities of the composed sub-multiplexers. Thus, the power consumption of the multiplexer is reduced to achieve higher power efficiency.

Abstract: A serial interface circuit includes a plurality of serial transmitters for a plurality of channels, respectively; and a plurality of serial receivers provided for said plurality of channels and connected with said plurality of serial transmitters, respectively. Each of said plurality of serial transmitters transmits a serial signal. Each of said plurality of serial receivers includes a receiver circuit configured to convert the serial signal into a data sequence; n (n is an integer more than 1) register groups configured to shift the data sequence; a data processing circuit configured to perform a data process on said data sequence based on n outputs of said n register groups and a detection result; and a header detecting circuit configured to detect a header of the data sequence when said b register groups from a first register group to a bth register group among said n register groups shift the data sequence, and to output the detecting result to said data processing circuit.

Abstract: A system and method for allocating sources to channels is provided. Multiple sources provide input signals to be transferred to the channels. Storage units associated with the channels store source identification information for each of the sources that transfer input signals to the channels. Selection circuit selectively pass one of the plurality of input signals from a respective one of the plurality of sources according to a state of a respective control input to the selection circuit, the control input for each selection circuit being determined based on the source identification information of a source associated with the selection circuit. A checking circuit checks outputs of the selection circuits and forwards passed input signals to the channel, such that the input channels are forwarded to the channel according to the priorities associated with the sources. The invention for allocating multiple sources to multiple channels can be applied to a direct memory access (DMA) controller.

Abstract: A method and system for multiplexing a plurality of serialized data signals in which a first integrated circuit device generates a plurality of serialized data signals. A second integrated circuit device is in electrical communication with the first integrated circuit device. The second integrated circuit device includes a multiplexer operable to generate a multiplexed output signal from the plurality of serialized data signals received from the first integrated circuit. A phase data and byte snapshot back channel is transmitted from the second integrated circuit device to the first integrated circuit device. The phase data and byte snapshot back channel carries phase data and periodic snapshots of the serialized data signals. The phase data and byte snapshot back channel is used by the first integrated circuit device to adjust the phase of each of the plurality of serialized data signals to preserve bit and byte alignment. Such a method and system can be implemented as a 4×10 Gbit/Sec.

Abstract: A method for multiplexing digital data, wherein a packet of digital data is simultaneously sent from front to rear and from rear to front. Additionally, a method for multiplexing digital data, wherein a packet of digital data is simultaneously sent from the beginning of the packet towards the end and from the end towards the beginning. Additionally, a method for multiplexing digital data, wherein simultaneously a packet of digital data is sent and the same packet is sent backwards.

Abstract: A network interface includes N input lanes that receive data symbols and idle symbols. A substitutor module periodically replaces an idle symbol on each input lane with a corresponding alignment symbol to form an alignment group. M interleaver modules each interleave a portion of the data symbols and alignment symbols onto a corresponding transmit lane based on an interleaving pattern that provides each transmit lane with N/M alignment symbols from the alignment group. M is an integer greater than 1 and N is greater than M. In some features the substitutor module periodically replaces successive idle symbols on each lane with alignment symbols to form corresponding alignment groups. An interleaver module interleaves the data symbols and alignment groups onto M transmit lanes according to an interleaving pattern that provides each transmit lane with one of the alignment groups.

Abstract: An optical packet switch switches optical packets according to bit-rates at which the optical packets are provided. For example, optical packets that are received at similar bit-rates may be routed to a destination at separate time slots over a single channel wavelength, and optical packets that are received at different bit-rates may be routed to the destination over separate channel wavelengths. When optical packets are provided at different bit-rates on a plurality of input paths, optical packets provided at low bit-rates may be compacted before switching to the destination. Alternatively or additionally, the bit-rates of the optical packets may be balanced before switching to the destination. Bandwidth contention among optical packets may be resolved by polarizing optical packets originating from separate input paths in different polarization directions, and merging optical packets having different polarization directions onto a single switched channel wavelength.

Abstract: A concentrator multiplexes network data from different links in a network and carried on a plurality of lower speed lines into multiplexed network data carried on a higher speed line. A line interface module demultiplexes the multiplexed network data carried on the higher speed line, assembles the demultiplexed network data into cells, and reassembles cells into packets for analysis. A single distributed network analyzer analyzes the reassembled network data.

Abstract: An acoustic transducer arrangement and system and method utilizing the same are presented. The acoustic transducer arrangement includes: an acoustic transmitter assembly including an array of transmitter elements operable to generate together a multi-frequency acoustic signal; and a control unit preprogrammed to operate the acoustic transmitter assembly in accordance with digital data stream indicative of a received signal to generate the multi-frequency acoustic signal indicative of the received signal.

Abstract: A high data rate switch is disclosed. The switch may include fiber optic channels where a plurality of switching elements necessarily operate at a significantly lower data rate providing routing of variable or fixed size data packets from a plurality of source ports to a plurality of destination ports via a single serial link. This is may be provided by storing the high rate data temporarily in memory in each of the source ports and then downloading it at a lower rate in a complete data packet to a designated switching element, almost immediately distributing the next data packet that has been received by the source port to a next switching element. The switching element configuration provides automatic redundancy and a minimum amount of frame overhead while sustaining throughput at the high data rate.

Abstract: A method and a device for combining at least two data signals having a first data rate into a single data stream having a second data rate higher than the first data rate for transmission on a shared medium or vice versa. The device has at least one port for receiving at least two data signals and a port addressing unit for extracting data from the data signals received by the ports. The port addressing unit is configured to place the extracted data at predetermined positions in the single data stream to be transmitted on the shared medium and at least one control data insertion unit is provided for placing control data in the single data stream.

Abstract: The invention relates to a multiplexing device comprising a data compressor. The compressed data block leaving said compressor occupies a particular bandwidth. According to the invention, a bandwidth prediction unit calculates said bandwidth and deduces from it the available bandwidth for conveyance in a time space dedicated to Internet traffic. The invention also relates to a multiplexing device and a multiplexing/demultiplexing system. Particular application in a satellite telecommunication system.

Abstract: The invention relates to a system and method for the generation of television channels and which allows the generation of the same by the processing and selection of designated packets of data from multiple data transport streams, which each transport stream including numerous packets of data. In each transport stream the packet of data is identified by the allocations of a packet identification code (PID) and each is held in the transport packet which is transmitted as part of each transport stream. In accordance with the invention, and in order to prevent errors and inaccurate packet selection, a Transport Stream Identification Code (TSID) is allocated to each of the transport streams of data received. Typically the TSID is located in the transport packet for each transport stream of data. In the selection of a packet of data, the appropriate TSID is referred to identify the appropriate transport stream and the PID then referred to identify the packet of data from that transport stream.

Abstract: A switching arrangement and method allow signals received by a communications platform to be directed to an appropriate interface depending on the type of signal received by an input signal line. A switch element having a switch is responsive to a logic control system that is itself responsive to signals that the input signal line receives. The logic control system may be responsive to any detectable identification, property or quality of the received signal. When the input signal line receives an analog signal, the logic control system detects that the signal is analog and causes the switch element to connect the input signal line to the analog interface with the switch. When the input signal line receives a digital signal, the logic control system detects that the signal is digital and causes the switch element to connect the input signal line to the digital interface with the switch.

Abstract: Provided are an apparatus for multiplexing Gigabit Ethernet frames and an apparatus for demultiplexing 10-Gigabit Ethernet frames. The apparatus for multiplexing Gigabit Ethernet frames includes at least one pre-processing unit, a multiplexing unit, an SDR/DDR conversion unit, and a control unit. The at least one pre-processing unit receives Gigabit Ethernet frames, converts the Gigabit Ethernet frames into 10-Gigabit Ethernet frames, and outputs the 10-Gigabit Ethernet frames. The multiplexing unit receives the 10-Gigabit Ethernet frames, time division multiplexes the 10-Gigabit Ethernet frames in frame units, and outputs the time division multiplexed 10-Gigabit Ethernet frames as first data. The SDR/DDR conversion unit, which converts the first data into second data having two 32-bit bus structures and outputs the second data. The control unit outputs a first control signal in response to an output request of the pre-processing unit.

Abstract: In the face of data loss on connections between a content source and a content consumer, additional connections therebetween are opened. These additional connections are preferably opened between the content source and a proxy disposed between the content source and the content consumer. The proxy may then seam together data streams received from the content source across the additional connections in a recording on a computer-readable medium. The seamed stream may be constructed by filling in information gaps in any of the data streams received from the content source with content derived from others of the data streams received from the content source. This derivation may be made on the basis of identifying characteristics (e.g., packet contents) of packets from each of the data streams received from the content source.

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: Systems and methods for conveying multiple low-bit-rate data streams over a data transport medium which is configured to transport data in a single, high-bit-rate data stream. In one embodiment, a plurality of low-bit-rate signals are received and a corresponding data rate is determined. Each of the signals is formatted in frames comprising a payload and overhead data. The high-bit-rate signal is also formatted in frames comprising a payload and overhead data, but the frames (including payload and overhead) contain more bits than those of the low-bit-rate frames. The payloads of the low-bit-rate frames are mapped into the payloads of the high-bit-rate frames. The overhead and timing data of the low-bit-rate frames are mapped into the unused portion of the overhead of the high-bit-rate frames. After the high-bit-rate signal is transported, the payload, overhead and timing data of each of the low-bit-rate signals is extracted, and the corresponding signals are reproduced.