Abstract: A communications system is organized into a two or more levels of multiplexing modules. Each multiplexing module has a plurality of inputs from next level multiplexing modules, with the exception of the last level multiplexing modules. The last level multiplexing modules have a plurality of inputs from sensor modules outputting data. A default condition is set up to allow transmission of address information from the computer to all the multiplexing modules to allow the programming of each multiplexing module to select one of its inputs. At the appropriate time, timing circuitry in the multiplexing modules reverse the direction of communication of the multiplexing modules to allow a single sensor module to transmit its data to the computer, in accordance with the address information.

Abstract: A data buffer includes a number of storing elements, a tree shaped structure of multiplexer elements, a write address generator, and a read address generator. The data storing elements have data inputs connected in parallel to an input for a data stream from a sending clock domain. The tree shaped structure of multiplexer elements is arranged for receiving data from the data storing elements, and emits on an output a data stream to a receiving clock domain. The write address generator generates, controlled by a write clock signal from the clock of the sending clock domain, write addresses for entering data from the sending clock domain into the data storing elements, one at a time. The read address generator generates, controlled by a read clock signal from the clock generator of the receiving clock domain, read addresses for reading out data storing elements in the same order as they were read in.

Abstract: This invention relates to methods and apparatus for extracting data of a channel from and for inserting low speed input data into a channel of time division bit multiplex. An optical data transmission system is used for distribution of video signals or information services. A variable frequency divider generates a timing signal by frequency dividing a clock signal by N. The resulting timing signal is phase shifted by M clock periods by inserting one cycle of 1/(N+M) frequency dividing in accordance with a synchronous command signal. With the timing signal, data of a channel is extracted from the time division multiplexed data of N channels by an extracting circuit, such as a D-type flip-flop. With a synchronous signal generated from the timing signal having the same pulse width of the multiplexed data, a low speed input data is inserted into a channel of the multiplexed data of N channels by a selector.

Abstract: Disclosed is a synchronous ring network system, which has a plurality of nodes, each of the nodes has: switching means for conducting a protection switching processing in response to a trouble; higher-order path misconnection search means for searching a misconnection of the AU signal caused by the switching processing; means for instructing the higher-order path squelch means to squelch an AU signal from the result of the higher-order path misconnection searching; lower-order path misconnection search means for searching a misconnection of the TU signal caused by the switching processing: means for instructing the lower-order path squelch means to squelch a TU signal from the result of the lower-order path misconnection searching; means for instructing the release of the higher-order path squelch after squelching by the lower-order path squelch means; and means for instructing the higher-order path overhead processing means to stop the termination as to a predetermined byte of each byte for composing the hig

Abstract: A high speed time multiplexed switch (TMS) fabric unit for use in a telecommunications system having relatively low speed TMS access links. To receive signals from the low speed access links, the TMS fabric unit of the invention consists of a plurality of programmable multiplexers where each programmable multiplexer is connected to a predetermined number, J, of the access links. Each access link carries M time slots where M is a relatively large number, i.e. 100. The programmable multiplexers put the content of the access links onto two high speed links. The speed of the high speed links is at least J times the speed of the access links such that for each time slot on the access links there is a fixed group of at least J time slots on each high speed link. Each of the two high speed links deliver the signals to at least one high speed TMS fabric where the speed of the high speed links is matched to the reconfiguration rate of the high speed TMS fabric.