Abstract: There is disclosed a wired-AND bus emulator circuit that allows any node to prevent propagation of information through the node. A controller can command all other controllers on the bus to break the bus thereby allowing the controller to determine the topology and possibly dynamically program the address of each controller on the bus. By allowing a controller to determine the bus topology, and possibly program the address of each other controller, the bus designer can configure the bus in a topology that is physically convenient. Additionally, the installer is not required to program each node with a unique address.

Abstract: A system and method of implementing a high performance digital bus interface. Digital signals present on a plurality of digital bus signal lines are amplitude encoded into a single signal and coupled to a transmission medium. The encoded signal is received and decoded by a complimentary decoder. The amplitude levels are discriminated and converted into digital symbols, each having a plurality of bits, which are coupled to a second digital bus. Digital signals are amplitude encoded at levels related by powers of two so that no encoding ambiguity is created. In wide data bus implementations, a plurality of encoder/decoders can be used. Bi-directional bus implementations are also taught.

Abstract: The invention provides a method and apparatus for efficiently regenerating an incoming data signal at a sampling point which is continually optimized independently of the regeneration process. While the incoming data signal is being regenerated in a regeneration unit, the invention uses a monitoring unit for concurrently optimizing the slicing threshold and sampling phase used in the regeneration unit without disturbing the on-going data regeneration. The invention uses a master-slave arrangement to regenerate the incoming data signal whereby the regenerating unit is updated with a new slicing threshold and sampling phase only after the new slicing threshold and sampling phase are fully optimized by the monitoring unit. In this way, the data regeneration can proceed unaffected by the optimization of the slicing threshold and sampling phase which, as a result can be continuously optimized without inducing any errors into the regenerated data.

Abstract: The invention includes methods and systems for use in a wireless communications system, such as a CDMA mobile communications system. A communications device transmits a wireless signal. A repeater system receives a first version of the wireless signal using a first receiver system and receives a second version of the wireless signal using a second receiver system. The repeater system switches between the first version of the wireless signal and the second version of the wireless signal to generate a third version of the wireless signal. The repeater system transmits the third version of the wireless signal and a base station system receives the third version of the wireless signal. In some embodiments of the invention, the wireless signals are Code Division Multiple Access (CDMA) signals. In some embodiments of the invention, the switching occurs at a rate of 4 MHz.

Abstract: The invention includes methods and systems to improve the signal diversity between a repeater and a base station in a wireless communication system. A communications device transmits a wireless signal. The repeater receives two versions of the wireless signal using a first receiver system and a second receiver system. The repeater transmits two versions of the wireless signal that correspond to the two received versions. The repeater transmits the two versions with different signal polarizations so they can be isolated from one another at the base station. The base station receives the two versions from the repeater and isolates each version based on the difference in polarization. The base station processes the two diverse versions to produce a high-quality signal. The use of different polarizations to provide diverse signals between the repeater and the base station lowers signal power requirements and increases the capacity of CDMA systems.

Abstract: The invention discloses a method and apparatus for supporting increased capacity on a backhaul communications link carrier frequency of a wireless communication system the uses a repeater station. Uplink RF carrier signals from a plurality of mobile units each having a first modulation scheme, are received at a serving repeater station. These uplink signals containing traffic and control information are demodulated and then re-modulated by a second modulation scheme having a higher-order modulation than the first modulation scheme. The re-modulated signal containing a plurality of uplink carrier signals within a single RF carrier signal is then transmitted over an uplink channel of a backhaul communication link. Additionally, the invention discloses a method for aggregating data on the uplink channel of a backhaul communications link. A plurality of uplink RF carrier signals from a plurality of mobile units are each received at a repeater station.

Abstract: A single frequency relay station receives a signal from a master station, and retransmits it. Before retransmitting the signal, the relay station uses a digital filter to subtract from the signal components which arise from multipath interference and coupling interference. The coefficients used by the digital filter are derived from characteristics of the multipath interference and the overall transfer function of the relay station. These are derived by turning off the retransmission, so that the multipath interference can be estimated from the received signal, and commencing the retransmission again, to determine the transfer function. A simplified inverse fast Fourier transform is used to simplify the calculations.

Abstract: A method for optimizing production from a rod-pumping system includes the steps of providing a well having a rod-pumping system for pumping a fluid from a downhole location of the well to a surface location of the well; providing a mathematical model for determining a dynagraph relationship for the well from power consumption of the rod pumping system; measuring power consumption per cycle of the rod pumping system; determining a downhole dynagraph relationship from the power consumption per cycle and the model; measuring real time values of wellhead pressure and preferably wellhead temperature; and determining an optimum operating condition for the rod-pumping system from the downhole dynagraph relationship and the real time values.

Abstract: A data processor 1 converts serial data in an STM-16 to parallel data that is based on eight bytes (64 bits) . A transparent information detector 10 detects the position of the data (transparent data) as a candidate for transparent processing in the parallel data and transparent processors 30a through 30e serially connected in five stages converts the transparent data and rearranges the processed data based on the detected information. Thus, the data processor 1 can perform transparent processing easily via a relatively low-speed general-purpose device, by converting high-speed serial data in the STM-16 to every 8-byte parallel data for further processing.

Abstract: The present invention discloses a much higher speed interface apparatus which comprises a data driving means for decoding two-bit data signals using them as inputs to output four-level data signals; a reference voltage generating means for generating three-level reference voltages to discriminate the voltage levels of the four-level data signals; and a receiver means for comparing the four-level data signals and the three-level reference voltage signals using them as inputs and for encoding the resulting signals to output two data signals.

Abstract: Disclosed is a clock extraction circuit for extracting a clock signal which furnishes timing for discriminating a data signal, from the data signal. The clock extraction circuit has a timing extraction unit for extracting the clock signal from the data signal, and a filter, which is provided in front of the timing extraction unit, having an upper limited frequency sufficiently lower than the bit rate of the data. The data signal is input to the timing extraction unit via the filter.

Abstract: The invention provides a method and apparatus for efficiently regenerating an incoming data signal at a sampling point which is continually optimized independently of the regeneration process. While the incoming data signal is being regenerated in a regeneration unit, the invention uses a monitoring unit for concurrently optimizing the slicing threshold and sampling phase used in the regeneration unit without disturbing the on-going data regeneration. The invention uses a master-slave arrangement to regenerate the incoming data signal whereby the regenerating unit is updated with a new slicing threshold and sampling phase only after the new slicing threshold and sampling phase are fully optimized by the monitoring unit. In this way, the data regeneration can proceed unaffected by the optimization of the slicing threshold and sampling phase which, as a result can be continuously optimized without inducing any errors into the regenerated data.

Abstract: Digital signals provided by a repeater connected to a plurality of clients by unshielded twisted wire pairs, are converted to analog signals which become degraded during transmission through the wires. Clients convert the degraded analog signals to digital signals. Digital signal phases are coarsely adjusted to have assumed zero crossing times coincide in-time with a clock signal zero crossing. Signal polarity, and the polarity of any change, is determined at the assumed zero crossing times of the digital signals. Pre-cursor and post-cursor responses, resulting from signal degradation, are respectively inhibited by a feed forward and a decision feedback equalizer. The time duration of post-cursor response is further inhibited by a high pass filter and a tail canceller. Phase adjustments are made, after response inhibition, by determining the polarity, and the polarity of any change, at the assumed zero crossing times.

Abstract: The present invention discloses a much higher speed interface apparatus which comprises a data driving means for decoding two-bit data signals using them as inputs to output four-level data signals; a reference voltage generating means for generating three-level reference voltages to discriminate the voltage levels of the four-level data signals; and a receiver means for comparing the four-level data signals and the three-level reference voltage signals using them as inputs and for encoding the resulting signals to output two data signals.

Abstract: A transmission apparatus capable of transferring data between a transmitting and a receiving device using a small-scale, low-cost hardware implementation for high-speed data transmission, the apparatus being conducive to reducing the amount of system design work on a target system. The transmitting device sends to the receiving device both data and a reference signal generated by a reference signal generation circuit. On the receiving side, a phase adjustment circuit delays the reference signal and a phase determination/phase amount control circuit brings the delayed signal into phase with a receiving-side clock signal. A data signal group is given the same amount of delay as the reference signal. The scheme allows data signals to be received directly in keeping with the receiving-side clock signal, eliminating the need for strict clock skew management, massive detours of data transmission lines or a wasteful wait time required for signal values to be established.

Abstract: A pilot signal is generated and added to a modulated carrier in a transmitter. The pilot signal is identical to an unmodulated carrier and has a level higher than a modulated signal to be transmitted. The pilot signal, transmitted together with the modulated carrier, is extracted at a diversity receiver and is correlated with the transmitted signals appearing at a plurality of diversity paths in the receiver in order to generate respective correlation coefficients. Subsequently, the received signals are respectively compensated for, using the correlation coefficients, in terms of levels and phases and then applied to a combiner. The pilot signal included in the output of the combiner is removed before the output of the maximum-ratio combiner is demodulated.

Abstract: The present invention provides improved compatibility between optical transmitters of various data rates and WDM optical communication systems. In the present invention, optical remodulators are configured to receive an optical signal, separate the information from that optical signal into N information streams (where N is a whole number greater than or equal to 2), and place the information onto N optical channels within the channel plan of a WDM optical system. Alternatively, the present invention provides optical remodulators configured to receive N optical signals, combine the information from the N optical signals, and place the information onto a single output optical channel having a wavelength within the channel plan of a WDM optical system.

Abstract: A radio relay apparatus complying with SDH is provided which permits the value of B2 bytes received from a transmitting-side terminal station to be sent to a receiving-side terminal station even in the case where resetting of a pointer value is performed. B2 sampling means of the radio relay apparatus samples B2 byte information, and B2 recomputing means again performs B2 parity computation of received transmission information which has been subjected to the pointer value resetting. Adding means adds bit by bit the data sampled by the B2 sampling means to the data obtained by the B2 recomputing means, and transmitting means transmits the sum obtained by the adding means to a subsequent radio relay apparatus. Based on the sum transmitted from the transmitting means, the subsequent radio relay apparatus judges that data which is a subject of B2 parity computation and which corresponds to a bit having the value "1" is erroneous.

Abstract: A bus signal detector for a signal transmitted via a bus (12) has an edge detector (14) which supplies a signal (S.sub.F1) indicating the occurrence of a signal edge (F1) when the voltage on the bus (12) suddenly changes by at least a predetermined relative threshold (.DELTA.U.sub.s) in relation to a reference voltage (V.sub.ref) continuously adapted to the quiescent voltage of the bus (.sub.12). An evaluating circuit following the edge detector (14) uses the signal (S.sub.F1) supplied by the edge detector (14) to produce an output signal indicating a bus signal.

Abstract: A repeater for use with Time Division Duplex (TDD) communications such as CT2 delivered over mains electricity cables. The repeater is coupled to a mains cable via a branch (the cable is not broken) and in alternate TDD phases converts signals from f.sub.1 .fwdarw.f.sub.2 or f.sub.2 .fwdarw.f.sub.1 and amplifies them. A clock signal to control timing of the conversion step is derived from a dedicated channel, a tone, or a call in progress. A regenerator function may be combined with the repeater.

Abstract: A method and apparatus for improving data regeneration in an asynchronous communication network is described where data is received on a two wire connection bus at a node in a communication network and is immediately retransmitted to another node therein. Incoming serial data is sampled at the time center of the serial data bit and is then immediately retransmitted based on the sampled data. The delay associated with buffering one full byte of data is reduced by a factor of 20 since the improved data regeneration technique of the present invention immediately retransmits the regenerated data one-half bit after it is received. Therefore, the network throughput is increased by a factor of 2000% and the network transmission media length is increased by a factor corresponding to the number of network nodes.

Abstract: An IR interface device is connected over a wired port to a host computer, so as to provide an IR communication link between the host computer and another computing device capable of IR communication. Such an IR interface device may also include a coupling to a printer device. An IR conference device allows communication between devices using different IR communication protocols by providing individual IR communication links to each of the communicating devices and passing data between the individual IR communication links. An IR transceiver integrated circuit with automatic gain control is provided.

Abstract: A signal regenerator for binary signals includes a signal equalizer having an input filter and an integrator. An amplitude detector and a period detector are arranged to receive the output signal of the equalizer. A high pass filter is included in a feedback loop to feed the output signal of one of the detectors back to the equalizer.

Abstract: A parallel processing computer system having an improved architecture for communication of information between nodes. The computer system of the present invention comprises at least three nodes; each of the three nodes for processing information. Each of the nodes comprises a routing means for routing information between nodes. The routing means allow reservation of a route through the network of nodes. Messages may then be transmitted from an origin node to a destination node over the reserved route. Use of a route reservation system reduces requirements for buffering of information at intermediate nodes on a route, improves message passing latency and increases node-to-node bandwidth. The present invention teaches communication of messages between nodes in a synchronous manner using a common strobe signal. The strobe signal is modified by regenerating alternate edges of the signal in order to eliminate pulse shrinkage of the strobe signal.

Abstract: A wide-band high-frequency analog amplifier is provided in the signal path between an input cable connector and an integrated-circuit based cable equalizer. The amplifier is preferably a common base transistor amplifier. The amplifier serves multiple purposes, including providing additional gain to compensate for losses incurred in the equalizer, increasing return loss on the input line, and allowing different gain levels in the input stage and operating stages of the equalizer.

Abstract: A discrete integrated repeater device and port MAU/AUI functions shares resources among its several ports. The device includes a single multi-bit free running counter providing preselected timing intervals to a plurality of latches. A signal undergoing measurement clears the latch while a preselected timing signal sets the latch. Receipt of a timing signal at a set latch indicates success or failure of some particular condition under test. The device satisfies an IEEE 802.3 specification for execution of a link integrity test. The device is also able to selectively disable or enable the link integrity test function for particular ports. A plurality of latches, one associated with each port, is set upon carrier sense detection at the particular port. A token passing mechanism implemented with a daisy chained line coupled to each latch enables a polling of each latch to provide carrier sense information about each port in a serial format.

Abstract: A method and apparatus for implementing a zero latency synchronizer that permits the reliable transfer of data between clock domains by placing a metastability delay in the clock path. The zero latency synchronizer for synchronizing a signal from a first clock domain to a second clock domain is formed from a clock regenerator circuit and input and output master slave flip flops. The clock regenerator receives a first clock from the first clock domain and a second clock from the second clock domain and generates first and second regenerated clock signals. The first and second regenerated clock signals are formed in a manner that guarantees that the first and second regenerated clocks, in conjunction with the first and second clocks, can be used to control the input and output master slave flip flops and thereby pass data reliably from one clock domain to the other without delay.

Abstract: This transmission system for transmitting data by a link comprising intermediate equipments (I.sub.1 to I.sub.N) is provided for connecting a transmitting side of a first user equipment (TE) with a receiving side of a second user equipment (TR). In the intermediate equipment situated on the receiving side, thus the most downstream equipment, there is provided a disturbance circuit (30) which disturbs bits at its output as a function of an error information signal that represents the quality of the received information signals in the intermediate equipments.

Abstract: A communications station (10) couples a bidirectional input-output signal path (16') to two unidirectional signal paths; a transmit signal path (12') and a receive signal path (14'), using a controllable hybrid (20). A feedback control system in the station minimizes the amount of transmit signal appearing at the receive output port (24) of the hybrid (20). The control system spreads the spectrum of a pilot signal (40) by means of a biphase modulator (46) and a pseudorandom generator (42) to produce a spread-spectrum pilot, which is added, in a summer 30, to the transmit signal. The spread-spectrum pilot signal covers the bandwidth of the information signal, and is reflected in an amount and with a phase which depends upon the relative impedance presented to the hybrid (20) by the bidirectional signal path (16').

Abstract: A transmission system for an auxiliary signal which is extracted from/inserted into a terminal office and for an IF repeater office for digital multiplexing microwave communications. The auxiliary signal transmission system multiplexes the frequencies of primary signals, and performs a communications operation between a terminal office pair and repeater offices that are located between the pair of terminal offices for extraction/insertion of auxiliary signals. In this system, the frequencies of the auxiliary signals are provided in the vacant areas in the frequency bands of the primary signals, and the auxiliary signals are transmitted from the repeater offices in a time-sharing manner.

Abstract: In a bit clock generation circuitry, a T/2 pulse generator includes a monostable multivibrator triggered by an edge of an input PCM data signal and controlled by a time constant adjusting signal so as to generate a pulse signal having its pulse width adjusted in accordance with the time constant adjusting signal. In response to a pulse signal generated by the monostable multivibrator, a D-type flipflop latches the input PCM data signal for generating a delayed data signal delayed from the input PCM data signal by T/2. An exclusive-OR means receives the input PCM data signal and the delayed data signal for generating a T/2 pulse signal.

Abstract: The present invention discloses a method and a device for conversion of an optical data signal from a multimode fibre (1), which except for normal data signals may contain interruptions and an overmodulated low frequency signal, to a corresponding signal which is transmitted further into a single mode fibre (8) by a laser (7). An electric signal from an optical receiver (2) partly directly and partly through a low pass filter (4) is coupled to a comparator (5) the output of which modulates the laser (7). Upon detection of an optical interruption the low pass filter (4) is influenced such that its output signal is stored in a memory device, and the laser is influenced by diversion of the laser current, simultaneously as an analogue value in the control loop of the laser is stored. When the interruption ends both the laser transmitter (7) and the low pass filter (4) continue to operate as before on the basis of their stored analogue values.

Abstract: A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. The system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. The arriving data is de-multiplexed at the hub into separate channels for handling the separate streams by appropriate hardware. When no calls are in progress, a low power mode enables two ends of a network link to reduce power consumption by transmitting a single pulse once every 125 microseconds in lieu of transmitting an entire cycle template. Synchronization while in low power mode allows circuitry at both ends of a network link to remain synchronized to a single reference clock.

Abstract: There is disclosed a wireless communication apparatus for constituting a multi-station communication system, capable of preventing the interference to other communications and the deterioration in the quality of channel. The apparatus has a receiving unit and a transmitting unit, and prohibits the transmission by the transmitting unit according to the magnitude of the received output of the receiving unit.

Abstract: A repeater device in a communication network within a transmission line segment receives a distorted signal from the transmission line and retransmits a modified signal. The repeater includes a detector for activating the device in response to the input of the signal and a logic control in order for directing the signal to the modifying portion of the device. To minimize bit error which may occur as the signal is being transmitted over the network or as the signal is being received by the modifying portion of the repeater, the repeater replaces the leading bit of the signal prior to being retransmitted back to the network.