Abstract: A method for measuring the performance of decoding in a telecommunication system comprising a decoder and a testing apparatus for supplying test data to the decoder. A test data comprising channel coded speech parameters and an inband data field in a frame format is generated in the testing apparatus and transmitted to the decoder for decoding. The decoder extracts at least a part of the inband data field from the decoded test data and transmits at least the part of the inband data field back to the testing apparatus. The performance of decoding is measured by comparing the transmitted inband data field and the received inband data field in the test apparatus.

Abstract: A remote test unit (RTU) and method of operation are provided for utilizes the ability of an access matrix ability to route signals. The RTU can emulate a central Digital Subscriber Line Modem (DSLM-C) for testing customer premises equipment containing a remote Digital Subscriber Line Modem (DSLM-R). The RTU can also emulate a DSLM-R for testing central offices equipment including a digital subscriber line access multiplexer (DSLAM) containing a DSLM-C. The RTU can also emulate a concentrator connected to the DSLAM, a router connected to the concentrator, an Internet service provider (ISP) connected to the router, and a web site connected to the ISP over the Internet. The RTU can further test, using emulation, ISO/OSI layers defined in the ISO/OSI reference model which are connected to the DSLAM.

Abstract: The invention relates to a method of phase controlling a data signal transmitted from a data source to a data sink using a counter clock approach, wherein the phase of a data sink clock is compared with the phase of a reference signal at the data sink and the phase of a counter clock is adjusted at the data sink in dependency to said phase comparing. It relates also to a counter clock circuit arrangement and interface device for performing the method according to the invention.

Abstract: Methods, apparatus, and systems for mode assignment and mode adaptation to channel conditions are provided which are based on estimations of real signal-to-noise ratios (SNR) for each frequency carrier bearing information during a data transmission session. The invention utilizes two principal procedures: signal-to-noise ratio (SNR) estimation, and a corresponding mode assignment. SNR estimation is obtained by an averaging of squared Euclidean distances between normalized received signals and reference signals corresponding to either current hard decisions from the output of a demodulator or soft decisions provided by a decoder, for each frequency carrier bearing random information. Using the SNR estimations, various algorithms for determining mode assignment are provided.

Abstract: An automated test system (20) for testing a high-speed communications integrated circuit (10), such as a serializer/deserializer, is disclosed. The system (20) is able to test the parameters of receiver jitter tolerance and receiver sensitivity in a loopback connection arrangement, in which serial output terminals (SERTX) of the integrated circuit (10) are connected to serial input terminals (SERRX) of the integrated circuit (10). An attenuator (26), which in the disclosed embodiment includes programmable attenuators (30P, 30N) and a fixed attenuator (32), one of which is selected, is disposed in the loopback path. A deterministic jitter injector (28) is also in the loopback path, and may be implemented by way of variable length trace blocks (35P, 35N) on the test board (30).

Abstract: The present invention provides a solution that eliminates both the voltage-controlled oscillator (“VXCO” 105) and its associated D/A converter (120) from the timing recovery scheme, thereby significantly reducing manufacturing costs for modems, such as asymmetric digital subscriber loop (“ADSL”) modems. The present invention also enables tracking of a wider frequency offset. The present invention provides this with a novel timing recovery scheme implemented entirely in the digital domain. The present invention includes a free running clock (205) as the sampling clock for the A/D (110) and D/A (115) converters, and interpolators (210, 220, 615 and 635) to correct timing errors for both the receive and transmit samples. The desired sample can be obtained based on its timing offset and its neighboring samples.

Abstract: A communication circuit includes a near end replication transmitter and a hybrid having an input in communication with an output of the near end transmitter. A high pass filter is responsive to the near end replication transmitter. A subtractor subtracts an output of the high pass filter from the output of the near end transmitter and an output of the hybrid. A near end receiver is responsive to an output of the subtractor. The near end replication transmitter is adjustable and includes a current generator in communication with an adjustable load.

Abstract: Method and apparatus for playing analog audio in an electronic audio system having multiple audio codecs, only one of which has a direct hardware connection to the analog audio source. First analog audio data is received from the analog audio source at a first audio codec, and converted to digital audio data using the first audio codec. The digital audio data is stored in a memory, and read back from the memory, transferred to a second audio codec. The digital audio data is then converted to second analog audio data using the second audio codec, and output from the second audio codec. An audio controller may be used to store the digital audio data in a loopback buffer within the memory, read the digital audio data from the loopback buffer, and may further be programmed to operate in a prepare loopback state, a loopback running state, and a recording state.

Abstract: A method is provided for time control of data transmission from a first module to a further module. An electronic system also is provided having a first module from which data is sent via a connecting line to a further module, which has a reference signal line via which a reference signal is transmitted from the further module to the first module, which reference signal is chosen as a function of the timing of the data received by the further module, with respect to a clock signal received by the further module. The reference signal has a bit sequence which corresponds to a bit sequence which was received by the further module via the connecting line from the first module.

Abstract: A method is presented comprising receiving a broadband signal at a receiver in accordance with a first modulation technique, tuning the receiver to a channel within the broadband signal, and modifying one or more operational parameters of the receiver to demodulate the channel in accordance with a second modulation technique to determine whether the channel is a data channel.

Abstract: A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Abstract: Method and circuitry for performing a line loop back test includes a receiver, a deserializer, and a low speed parallel loop back data multiplexer selects either the low speed parallel data from the deserializer when in loop back mode or low speed parallel input data when in normal mode. The deserializer produces a low speed clock output signal that is fed to a low speed loop back reference clock multiplexer and also to a low speed loop back clock multiplexer. Both the loop back reference clock multiplexer and the loop back clock multiplexer select the low speed clock output signal from the deserializer when in line loop back mode. A clock multiplying unit converts the output of the low speed loop back reference clock multiplexer into a high speed clock signal. The serializer generates the high speed serial transmitter data in synchronization with the high speed clock signal received from a clock multiplying unit.

Abstract: A transmitter and a receiver share a maximum number of transmission bits per symbol as a parameter. The transmitter modulates an encoded and interleaved transmission signal in accordance with a modulation scheme which enables the transmission of one bit or more per symbol, while the receiver demodulates a received signal based on a channel quality in accordance with a modulation scheme which has a higher modulation level as the channel quality is higher. When the number of demodulated bits per symbol is smaller than the maximum number of transmission bits per symbol, the receiver deinterleaves and decodes a received signal after the demodulation on the assumption that the received signal has likelihoods of zero as much as the number of missing bits.

Abstract: A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received.

Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.

Abstract: A repeater for HDSL transmission is presented. The repeater replaces the regenerator commonly used in HDSL by utilizing the activation/deactivation process in the HDSL specification. The repeater is adjusted to detect an activation/deactivation sequence, whereby a flip-flop in the repeater is alternated. A first state of the flip-flop allows transmission passing through the repeater to the terminating point, e.g. a network terminal, and a second state loops transmission back to the originating point, e.g. a line terminal. The looping may then be utilized for maintenance and error detection and recovery. By use of one of the free bit in the overhead channel in the HDSL transmission as an origin bit, wherein “1” is set in the upstream direction, and “0” is set in the downstream direction, it is possible to detect at the line terminal whether there is a loop in the repeater.

Abstract: A truly random sequence of bits is transmitted from a transmitter, such that a receiver can receive and store a portion of the transmission for the duration of time that the receiver is within range of the transmitter. Thereafter, the stored sequence in the receiver is compared to a stored copy of the continuous transmission to determine the time that the stored sequence was transmitted. If the sequence of bits is truly random, the security of the system is assured.

Abstract: A method of disabling at least a portion of one of a plurality of channels in a digital audio radio system includes the steps of receiving (702) a digitally encoded bit stream over-the-air on the plurality of channels and decoding (704) a selected channel among the plurality of channels. The method further comprises the steps of selectively tagging (706) an undesired type of content on the selected channel, analyzing (708) for an indication of content of the undesired type among the plurality of channels, and selectively disabling (710) at least the portion of the selected channel containing the undesired type of content.

Abstract: In order to enable high speed, high bandwidth data transfer between two ASIC devices, for example in a backplane, a wide parallel input data word is divided into a smaller number of words, and each smaller word is converted to serial form and then transmitted over a respective sub-link at a high clock rate relative to the system clock. At the receiving side, the clock is recovered from the serial words, and the serial words are converted back to parallel form. An alignment process is then carried out, firstly involving detecting the positions of the bits of the words and then storing the words in a buffer FIFO register. The words are clocked out of the FIFO register in synchronism under control of the system clock once it is detected that valid words are received in the FIFO registers.

Abstract: A voice and data communication system whereby a line card digitizes and packetizes voice communications signals upon the failure of Customer Premises Equipment (CPE). The system comprises a line card for coupling the CPE with a network. Furthermore, the invention provides a system that can direct the voice signals to either or both of a voice network and a data network.

Abstract: A distortion compensating device provided in a receiver for compensating distortion which is added to a signal in a transmission path. The signal is generated in a multi-level modulator of a transmitter in which a digital signal is mapped to one of a plurality of specified signal points in a signal space diagram. The device includes a signal-point-position averaging circuit for producing an average signal point for each of a plurality of distributions of received signal points in the signal space diagram. A discrimination circuit in the device discriminates the average signal point closest to a received signal point from other average signal points in the signal space diagram.

Abstract: A data transceiver including a self-test data generator for generating test data, which includes a first pseudo-random number generator programmable so as to allow the operator to input the test data values. The data transceiver further includes a transmitter section coupled to the self-test data generator, a receiver section coupled to the transmitter section, and a test data analyzer coupled to the receiver section, wherein the test data analyzer includes a second pseudo-random number generator, which allows the operator to input the data value via a data bus coupled to the test data analyzer. Both the self-test data generator and the test data analyzer are independently controllable.

Abstract: An on-chip parallel data generator, including a Built In Self Test (BIST) generator, is integrated into a laser driver array of a parallel optical communication transmitter so that all optical outputs switch simultaneously. The BIST generator requires only one clock input which clocks the BIST generator for all channels. The optical outputs respond to either the on-chip BIST generator or the electrical inputs if a valid signal is present on the inputs.

Abstract: Digital circuitry is tested through effecting a paired data loop-back from a first buffered output to a first buffered input whilst within the circuitry executing at least part of the test through using a Built-In-Self-Test methodology. In particular, the loop-back is effected from the first buffered data output to a buffered control input, from a buffered control output to the first buffered data input, or both. Advantageously, the buffering is associated to executing a conversion between a digital full swing internal signal and an analog low swing external signal with respect to core circuitry of the digital circuitry.

Abstract: A method is presented for increasing data throughput in a communications channel comprising the steps of selecting a first data packet from a queue of data packets to be transmitted over a communications channel, modulating said first data packet using a first modulation scheme, selecting a second data packet from a queue of data packets to be transmitted over the communications channel, modulating the second data packet using a second modulation scheme overlaying the first data packet on a symbol by symbol basis, transmitting the first data packet overlaid with second data packet over the communications channel, determining whether the first data packet was received by monitoring using the first modulation scheme for an acknowledgment for the first data packet before expiration of a timeout period, determining whether the second data packet was received by monitoring using the first modulation scheme for an acknowledgment for the second data packet before expiration of the timeout period and repeating the st

Abstract: A wireless communication system with feedback and a method therefore, wherein the wireless communication system, which has a plurality of transmitting antennas and a plurality of receiving antennas through which signals are transmitted and received, respectively, includes: a transmitter that restores feedback information from a predetermined feedback signal, weights an information signal with the restored feedback information, and converts the weighted information signal to a radio frequency signal in order to transmit the radio frequency signal; and a receiver that receives the radio frequency signal to estimate the state of a channel, through which the radio frequency signal is transmitted, calculates a weight of a dimensionality corresponding to the number of the transmitting antennas, approximates the weight as lower-dimensional one to extract feedback information, and converts the feedback information into a radio frequency signal to send the radio frequency signal to the transmitter.

Abstract: A system is provided for testing a physical layer device, or various network portions connected to that physical layer device. The test system includes a random bit generator that, during use, produces a random pattern of bits clocked in parallel onto the transmit portion of the physical device. The parallel-fed information can then be serialized and selectably fed back to the receive input of the same physical device. The receive portion of the physical device can then deserialize the random pattern of bits, and present those bits to logic within the test system. The test system can, therefore, compare each of the random pattern of bits presented to the physical device with corresponding bits derived from the deserializer. If each bit within the random pattern of m bits forwarded to the serializer does not compare with each corresponding m bits forwarded from the deserializer, then the physical device is known to be a failure.

Abstract: A semiconductor integrated circuit device includes a transmitting circuit capable of converting first parallel signals to a first serial signal, a receiving circuit capable of converting a second serial signal to second parallel signals, a test signal generating circuit, and an operation judging circuit, all of which are formed on a single semiconductor chip. The test signal generating circuit and the operation judging circuit are formed so as to operate in accordance with a clock having a frequency corresponding to a transfer rate of the first or second parallel signals.

Abstract: A transmission unit which transports digital signals between different network systems, effectively converting the signals to resolve their differences in the specifications. A first signal interface transmits and receives first network signals. A second signal interface transmits and receives second network signals. A downward converter produces lower-level signals by converting received first and second network signals to a lower hierarchical level at which the first and second network systems are compatible with each other in terms of logical signal structure. An upward converter produces a higher-level signal by converting each given lower-level signal to an upper hierarchical level which complies with the first or second network system. A loopback unit provides loopback paths to route the lower-level signals from the downward converter to the upward converter, so that the first and second network signal will be converted in both directions.

Abstract: A line driver selectively drives one of two transmission lines. The line driver includes a differential amplifier connected to first and second differential switches. The first differential switch is connected between an output of the differential amplifier and a first of two transmission lines. The second differential switch is connected to the output of the differential amplifier and to the second of two transmission lines. The first and second differential switches are controlled by respective first and second control signals. The output of the differential amplifier is connected to either the first or the second transmission line in response to the first and second control signals. The differential switches include loopback protection to an prevent an incoming signal from passing from one transmission line to another during power down mode.

Abstract: Test circuitry for a transceiver is described which allows tests to be conducted on a transmission loop without requiring decoding by rake fingers. According to one embodiment, a receiver for receiving a test signal includes a detecting circuit set up in accordance with a test spreading code for detecting whether or not signals received by the receiver include the test signal incorporating the test spreading code. In the embodiment, a matched filter set up according to the test spreading code is utilized as the detecting circuit. According to another embodiment, circuitry for adjusting the power level of a test signal is described in which power control information is transferred between first and second storage locations at the transceiver to allow otherwise normal control circuits to implement the power control.

Abstract: Systems and methods are described for digital subscriber loop repeaters. A method of transforming a digital subscriber loop signals includes increasing a gain with a digital subscriber loop repeater including: isolating an upstream signal band by passing an upstream signal through an upstream pass filter; amplifying the isolated upstream signal with an upstream amplifier; isolating a downstream signal band by passing a downstream signal through a downstream pass filter; and amplifying the isolated downstream signal with a downstream amplifier. The systems and methods provide advantages because DSL can be provided over long loops and/or over coil loaded loops.

Abstract: A loopback processing method includes detecting a loopback at a first entity in a wide area network. The detection is accomplished by recognizing that a “memorized” frame has returned on the same communications interface within a given period of time. The time interval between sending the frame and detecting it returning at the same port may be recorded and sent to an operator to provide information on the relative location of the loopback in the network. A loopback detect sequence is sent from the first entity to a second entity on the communications interface in loopback. Because of the loopback, both entities receive the loopback detect sequence. Either or both entities may inform a network operator of the loopback. The first entity has stopped using the link in loopback for real data, instead sending the loopback detect sequence. The second entity, upon detecting the loopback detect sequence, also stops using the link for real data.

Abstract: Method and apparatus for combining high data rate traffic and low data rate traffic on a common transmission medium while maximizing efficient use of available spectrum. Since spectrum is an economically valuable resource and transport of data generates revenue, the present invention directly leads to more profitable network operation. The disclosed systems are applicable to both wired and wireless transmission media. In one embodiment, a bandwidth reservation scheme provides that data rate may be varied so that when a particular data communication device is allocated a frame, it is also assigned a data rate for use in that frame. Because bandwidth usage varies with data rate, the division of available spectrum into channels for use by individual data communication devices may also vary among frames.

Abstract: A signal transmit-receive device that reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group and for running a loopback test on a signal transmit-receive device for signal communication, and reduces installation costs and power consumption. The new loopback test circuit uses an error detecting circuit within the transmitting circuit IC, a test signal producing circuit within the receiving circuit IC, and a wiring for transmitting error information from the transmitting circuit to the receiving circuit. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern to detect errors. The test signal producing circuit produces a test signal pattern defined in advance by the first communication device, and can invert any bits of the test signal pattern, based on error information.

Abstract: The invention is a communication system having a series of output modules that provide continuous synchronization output signals. Each output module has a driver assembly has a driver output and a backup selector output that is capable of driving a failed next driver assembly. A sensor detects the failure of the driver output and generates a select signal in the failure state. A selector receives the driver output, a backup driver output, the select signal, and a select signal from the next driver assembly. The selector normally selects the driver output, but in response to a failure state from the select signal, isolates the failed driver output. The previous driver assembly transmits a backup selector output to the failed driver assembly to maintain a continuous driver output. The transformers are preferably placed on a separate card to reduce the thermal degradation of nearby electronics. As transformers rarely fail, replacing them when a card fails is wasteful.

Abstract: A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

Abstract: The invention relates notably to a method for controlling the transmitter part of a radio transceiver, the transmitter part comprising an IQ modulator, the radio receiver further comprising a receiver part comprising an IQ demodulator, the radio transceiver being dedicated to transmit modulated information signal over an air interface. According to the invention, the method consists in: storing an IQ modulation vector obtained at IQ modulator and associated to a portion of the information signal; looping the portion of information signal to the receiver part, the information signal having crossed a simulated radio interface between the transmitter part and the receiver part; estimating an error vector by comparing the IQ modulation vector to an IQ demodulation vector obtained by demodulation of the portion of information signal at IQ demodulator; and modifying transmitter part parameters according to the error vector.

Abstract: The amount of data transmitted in a primary data channel is increased by modulating a reference clock signal of the primary data channel with secondary data to form a separate secondary data channel. Primary data is formed into a primary data signal using the modulated reference clock signal, and a transmitter transmits the primary data signal to a receiver. The receiver recovers the primary data and modulated reference clock signal from the primary data signal, and then recovers the secondary data from the recovered modulated reference clock signal.

Abstract: An apparatus (200) checks voice quality when in a vocoder bypass mode. If the voice quality level is beyond an acceptable range, the apparatus (200) ends the vocoder bypass mode and returns to tandem vocoding. For example, a vocoder bypass controller (206) includes a speech quality detector (225) that determines the speech quality level of speech information based on at least one of detected volume level, echo level and noise level of the speech information. The vocoder bypass controller (206) with the speech quality detector (225) outputs a speech quality-based vocoder bypass control signal (236) to selectively activate or deactivate a vocoder bypass operation in response to the speech quality-based vocoder bypass control signal (236). In another embodiment, a network element for communicating speech packets includes an incoming decoder (512) and a speech quality detector (514) operative to determine the speech quality level of incoming speech packets.

Abstract: When the average received signal level falls below a given threshold level, a received level detecting/monitoring section informs a microprocessor of it. The microprocessor then collects information of the arrival direction and received power of desired radiation from each terminal station and the arrival direction and received power of undesired radiation from each source of undesired radiation and recalculates amplitude and phase weight values. The microprocessor rewrites weight values already entered into a weight value table by the recalculated weight values to thereby alter amplitude and phase weight values for antenna elements of an array antenna. Thereby, the directivity of the array antenna is subjected to optimum control according to variations in electromagnetic radiation propagation environment, allowing good radio communications at all times.

Abstract: A new scheme to transfer bidirectional data streams between a digital display and a computer is disclosed. This bidirectional data transfer can make several I/O devices attach to a display. Existing digital display interfaces are usually unidirectional from a computing to a display. Due to the nature of the existing clocking scheme, backward data transfer from the display side to the computer requires a backward clock. This invention discloses a scheme to send data bidirectionally without sending the additional backward clock. This invention also discloses a scheme to tolerate jitters from the clock source. With this approach, this new interface can make a digital display an I/O concentrator.

Abstract: Testing of analog-to-digital and digital-to-analog converters formed in integrated circuits. In one embodiment, a method of testing an analog-to-digital (A/D) converter comprises applying an analog test signal of a first frequency to an input of the A/D converter. Sampling digital byte samples from an output of the A/D converter at a second sampling frequency and comparing select digital byte samples with each other. When the select digital byte samples match, storing a verify bit in a memory to verify the A/D converter is working. In another embodiment, a method of testing a digital-to-analog (D/A) comprises creating repeating digital byte samples with a logic circuit formed in the integrated circuit. Converting the repeating digital byte samples into an analog test signal with the D/A converter. Comparing the frequency of the analog test signal with the frequency of an expected analog signal to determine if the D/A converter is working.

Abstract: A method for optimizing a bit-to-symbol mapping operation. The method has steps of (a) determining a most probable symbol selection error made during a space-time decoding operation; and (b) selecting a bits-to-symbol mapper such that a bit-to-symbol mapping step results in a most probable symbol selection error, made during a space-time decoding operation, causes a minimal number of bit errors. The bits-to-symbol mapping step can be carried out so as to minimize an average number of bit errors resulting from an occurrence of the most probable symbol selection error, as well as from an occurrence of at least a second most probable symbol selection error, during the space-time decoding operation. A space-time coded communications system that operates in accordance with the method is also disclosed.

Abstract: A method and apparatus for reducing processing requests of a pool of soft modems is disclosed. In one embodiment, a remote access concentrator comprises a memory, a processor, an interface bus, and a host interface. In one embodiment, the processor is coupled to the memory to operate a pool of soft modems in parallel with a common retrain handler, the common retrain handler includes a queue to store retrain requests, a request management block to retrieve the retrain requests and to identify modems that correspond to the retrain requests within a period of time, and a retrain engine to perform retrain procedures in accordance with modem standards.

Abstract: An adaptive DMT modem determines, as part of a startup sequence, subscriber loop conditions. One or more loop condition adaptation operations are then performed to reduce the complexity of the filters employed in the modem, to reduce the power dissipated in the modem, to optimize performance of the modem or to reduce the likelihood of EMI being radiated into the premises of a subscriber.

Abstract: A method and apparatus for performing an operability test on a communications system device such as a cable modem is provided. The testing method comprises the steps of providing a set of output test data to the communications system device being tested, and generating an output signal with the device in a manner that is responsive to the output test data. In the case of a cable modem, the output signal is generated by the modem's modulator. The output signal is then provided as an input to a reflective mixer which generates a reflected signal in response to the output signal and directs it back into the communications system device being tested. The communications device can then use the reflected signal to generate a set of input test data that can be compared to the output test data to check the accuracy of the device's operation.

Abstract: A technique for detecting and responding to a loopback condition on an ISDN PRI of a telecommunications switching system. The technique involves storing the Call Reference Value of the most recently transmitted call SETUP command as the Last Sent CRV. An incoming call SETUP command is considered to have looped back when it is assigned a Call Reference Value identical to the Last Sent CRV, and it requests a PRI channel that is occupied. The PRI is considered to be in a loopback condition after a predetermined number of call SETUP commands have looped back. The PRI can be removed from service while the loopback condition persists.

Abstract: Analog modems are enabled to better learn the slicing levels employed at the interface to a digital transmission network by reducing the effects of the various noise sources. Initially a training sequence is received to preliminarily adjust the analog modem's equalizer. Thereafter, a special training sequence, protected against intersymbol interference, is employed to collect samples of each slicing level, to ascertain the least mean squared value of each slicing level from the received samples and to obtain the channel's impulse response at each slicing level. Depending on the means squared error (MSE) between the input and the output of the slicer, the slicer tables continue to be updated, and the feed-forward and feed-backward equalizer filters are selectively adjusted in accordance with the channel impulse response ascertained at each of the slicing levels.

Abstract: A communication system that includes a first modem and a second modem that establishes a communication link between the first modem and the second modem. The communication link has a first set of communication characteristics including a first communication channel or group of communication channels through which at least data is exchanged and a second communication channel through which no data is exchanged. Either the first modem or the second modem is configured to signal for a change, via the second communication channel, in the first set of communication characteristics.