Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: Methods and systems are described for analyzing signal impairments using a test and measurement instrument. A method may include decomposing aggregate signal impairments into signal impairments that are correlated and uncorrelated to an acquired data pattern. The uncorrelated signal impairments may be further decomposed into periodic signal impairments (e.g., PJ) and non-periodic uncorrelated signal impairments. A PDF of the non-periodic uncorrelated signal impairments may be mathematically integrated, thereby producing an estimated cumulative distribution function (CDF) curve. Random signal impairments may be estimated as an unbound Gaussian distribution. The CDF curve of the non-periodic uncorrelated signal impairments and the unbound Gaussian distribution may be plotted in Q-space on a display device. Non-periodic bounded uncorrelated signal impairments (e.g., NP-BUJ) PDF may then be isolated. Bounded uncorrelated signal impairments PDF may then be synthesized.

Abstract: A transmitting device can suppress degradation of the video quality and determine a proper transmission rate, and include a transmitting unit that transmits a communication packet to a receiving device, a receiving unit that receives a feedback packet, which is a response signal corresponding to the communication packet, from the receiving device, a detecting unit that detects a change of a reception interval of the feedback packet, and a transmission rate determining unit that decreases a transmission rate at which the transmitting unit transmits the communication packet in the case where the change of the reception interval is detected, and increases the transmission rate on the basis of an amount of change of a travelling speed of at least either the transmitting device or the receiving device before and after the decrease in the transmission rate.

Abstract: A portable hand-held battery powered eye pattern analyzer is provided that can analyze signal quality of a high speed digital communication network. The system is 10 times smaller in volume and 4 times lighter than the bench-top equivalent instruments. The system includes a housing containing a display, keypad, power supply, battery pack, and RF sampler board along with connections for electrical inputs, optical inputs, clock signal inputs, and clock recovery signal inputs. The sampler circuit board can support connections, such as a USB plug for attachment to a personal computer. The RF sampler board contains the following elements: (1) A dual sampler for two-channel electrical inputs. (2) An Optical-to-Electrical O/E conversion module. (3) A clock recovery unit (CRU) module to recover the clock from the electrical or optical pulse pattern signal. (4) A trigger circuit that accepts an input clock and uses that clock to trigger the sampling of the data signal.

Abstract: The apparatus corrects multi-phase signals for detecting a position of an object and obtains a phase corresponding to the position of the object. The apparatus includes a correcting unit correcting the multi-phase signals with error coefficients, respectively, a phase calculating unit performing calculation for the corrected multi-phase signals to obtain the phase, a regression unit performing regression for the calculated phases to obtain reference phases, a Fourier transform unit respectively performing Fourier transform for the corrected multi-phase signals whose phases having been respectively changed into the reference phases, and an updating unit updating, using Fourier coefficients obtained by the Fourier transform unit, the error coefficients respectively corresponding to the Fourier coefficients. The updating unit updates the error coefficients if a regression error in the regression performed by the regression unit satisfies a predetermined condition.

Abstract: The present invention discloses a method for adjusting a tunable compensation filter within a communication device. The method includes the following steps: generating at least a detecting signal according to at least a pole of the tunable compensation filter; generating a transmitted signal according to the detecting signal; receiving the transmitted signal via a loop switch; generating a filtered signal by filtering the transmitted signal; generating a received signal by compensating the filtered signal; generating at least an indicating signal by comparing the detecting signal with the received signal; and determining whether to adjust at least a coefficient of the tunable compensation filter or not according to the indicating signal.

Abstract: Methods and apparatus for maintaining the maximum achievable data rate on a DSL line, up to and including a rate to which a user subscribes is described. Performance monitoring is conducted on the DSL line on an ongoing basis to determine noise margins in each direction. Each noise margin is compared against pre-determined decreasing/increasing thresholds to determine whether the line characteristics dictate a data rate change without loss of synchronization. The invention supports dynamic provisioning changes including application driven service level change requests, e.g., new bandwidth-on demand services. In some embodiments, a combination of existing and new embedded operations channel (EOC) messages are used to implement the modem data rate changes. New EOC messages may be implemented using some of the reserved and/or vendor proprietary Opcodes currently permitted. Modem assigned data rate changes are implemented without a disruption of service, e.g.

Abstract: An FFT unit subjects a P-times oversampling output of an AD converter to Fourier transform into a frequency domain signal. A distortion estimation unit estimates a distortion characteristic from a difference between the frequency domain signal and a reference signal. A correction coefficient calculation unit calculates a correction coefficient of a distortion characteristic. A correction unit corrects the frequency domain signal by using the correction coefficient. An IFFT unit subjects the corrected frequency domain signal to inverse Fourier into a time domain signal having the same sampling speed as a symbol speed, and outputs a partial time series.

Abstract: A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit.

Abstract: In order to improve precision for estimating carrier frequency offset and reduce computing load, the present invention provides a method for estimating carrier frequency offset, which comprises steps of calculating a plurality of corresponding intermediate CFOs, respectively, based on one received sync sequence and one prestored sync sequences stored sync sequence through multi-step calculation, wherein, in each step, one corresponding intermediate CFO is calculated based on said received sync sequence and said pre-stored sync sequence; and weighting said plurality of intermediate CFOs in accordance with channel quality of a channel transmitting said received sync sequence to generate one final CFO. Each of the selected sequence segments may have a length and a mutual distance which are both, at its maximum, the full length of the sync sequence minus 1 so as to improve precision for the intermediate CFOs.

Abstract: A method for extracting a parameter of a communication channel from a channel estimate that characterises the communication channel in terms of a frequency response over time. The method includes generating a set of feature identifiers that characterise features of the channel, for example energy peaks or troughs and determining the parameter, for example time delay of a multipath signal or frequency offset of a multipath signal, dependent on the feature identifiers. Methods using the parameter are also described including methods to estimate the environment.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: A Voice over Internet Protocol (VoIP) terminal has a Quality of Service (QoS) monitoring function and uses a QoS monitoring method. In a VoIP system performing real-time voice communication over an IP network, a packet loss value and a time-axis index value are detected, and are calculated from a real-time transport protocol (RTP) packet and an RTP control protocol (RTCP) packet, a QoS state value of the network is obtained in real time, the detected QoS state value is compared to a preset QoS state table, and thus a QoS state of the IP network is displayed for users.

Abstract: The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that controls the characteristics of acquisition and tracking of digital PLL loop, Voltage/Numerically Controlled Oscillator (VCO/NCO) that adjusts the sampling instant and phase, A/D converter that samples a continuous VSB input signal, and a interpolating squared root raised cosine filter that performs both matched filtering and a compensation of constant timing offset of quarter symbol caused by the invented TED. The timing error detector in this invention comprises an envelope detector, band pass filter, squaring block, high pass filter, and decimator.

Abstract: Apparatus and methods of providing a selected sample rate for sensor measurements are provided, which in one aspect may include a circuit configured to receive sensor signals as a first series of count rates corresponding to sensor the sensor measurements, each count rate representing a value of a parameter of interest, at least two accumulators configured to alternately accumulate the count rates in the series of count rates over a time period that corresponds to a selected sample rate and a controller configured to control the time periods for the at least two accumulators.

Abstract: An apparatus for rapidly measuring jitter transfer characteristics is provided. A modulation signal generator generates a modulation signal M including a plurality of sinusoidal components having known amplitudes m1 to mn and different frequencies f1 to fn, and outputs the modulation signal M to a jitter generator. A clock signal C phase-modulated by the modulation signal M is input to a data signal generator, a data signal D synchronized with the clock signal C is provided to a measurement object, a data signal D? output from the measurement object is input to a clock recovery unit to recover a clock signal component C?, and the clock signal component C? is phase-detected by a phase detector.

Abstract: A method in a mixed-signal system to prevent overlapping of clock edges of one or more digital clock signals and clock edges of one or more analog clock signals where the digital clock signals and the analog clock signals are digitally controlled includes generating one or more timing window pulses that are centered around the clock edges of one of the digital clock signals or the analog clock signals; combining the timing window pulses to generate a gating signal, the gating signal having an active logical level at each of the timing window pulses; and applying the gating signal to gate or delay clock edges of the other one of the digital clock signals or the analog clock signals.

Abstract: A receiver circuit includes a unit configured to determine filter coefficients based on a sampling time error of a received signal and a phase error of the received signal, as well as a filter configured to filter a signal, which is based on the received signal, based on the filter coefficients.

Abstract: A method and system of fine timing synchronization for an OFDM signal. The OFDM signal is coarse timing synchronized, generating a synchronization sequence and a CFR (Channel Frequency Response). The synchronization sequence is removed. A correlation coefficient of the correlation between the CFR applied to a number of carriers and the number of carriers with different window shifts is calculated. The largest window shift corresponding to a downsampling factor is indicated by the lowest correlation coefficient greater than a threshold. The CFR is downsampled by the downsampling factor, and an inverse FFT is performed on the downsampled CFR with a reduced number of calculations reduced by the downsampling factor, transforming the CFR into a CIR. A fine timing synchronization position is determined from the CIR and is utilized by an FFT unit within an OFDM receiver to accurately receive OFDM symbols of the OFDM signal.

Abstract: A communication apparatus including: a receiver to receive signals including reference signals at each of a plurality of different reception intervals; and a processor to estimate phase differences between the signals based on the reference signals, to determine a plurality of phase difference candidates for each of the reception intervals based on the phase differences, to select, from among a plurality of combinations of the phase difference candidates for the reception intervals, a combination of the phase difference candidates between the signals, and to estimate a frequency deviation of the signals based on the phase difference candidates included in the combination.

Abstract: According to an aspect of the embodiment, a signal transmission apparatus includes a sine wave output unit that outputs a sine wave to a transmission path, network analyzers and that analyze signals on the transmission path, an S parameter measurement unit that measures S parameters based on the analysis, a selection unit that selects a plurality of combinations of an amplitude, an emphasis characteristic, and an equalization characteristic based on the S parameters, measurement units that measure a BER or an eye opening of the transmission path for the plurality of combinations, and a setting unit that extracts single combination based on the measurement and that sets the amplitude, the emphasis characteristic, and the equalization characteristic to a transmission unit and a reception unit.

Abstract: The present invention provides a method for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The present invention provides a method for generating jitter test patterns by disabling the transmitter data scrambler of the second device; clearing the port_error register of the device under test; and sending a test pattern to said device under test. The present invention provides for a method for generating supply noise test patterns comprising: transmitting a test pattern to the DUT comprising a maximum length asynchronous packet containing alternate 0016 and FF16 bytes.

Abstract: A sampling phase calibrating method, comprising: transmitting a second command signal from a storage device controller, to read content in a storage device; transmitting a first command signal and a third data signal with a third sampling phase from the storage device controller to the storage device, according to the content; and determining if data transmitting from the storage device controller to the storage device has error, according to responding information that the storage device responds to the storage device controller corresponding to the first command signal and the third data signal, to determine if the third sampling phase is suitable; wherein the second command signal is transmitted via a second clock, the first command signal is transmitted via a first clock, where the second clock is slower than the first clock.

Abstract: A method for characterizing jitter of an internal clock signal of a circuit may include generating a series of samples of the internal clock signal by a reference clock signal, comparing the word formed by the N most recent samples of the series to an N-bit pattern, where N is an integer greater than, or equal to 2, and incrementing a first counter if the word complies with the pattern. The method may also include incrementing a second counter when the count of the first counter reaches a first threshold X1, and incrementing a third counter when the count of the first counter reaches a second threshold different from the first. The method may include calculating an average p and a standard deviation ? of a Gaussian density curve as a function of the counts reached in the second and third counters.

Abstract: A high-sensitivity receiver may be made by using multiple demodulators to demodulate a given signal. For example, the receiver may use a first demodulator to demodulate an input signal into a first sequence of soft bits and a second demodulator to demodulate the same input signal into a second sequence of soft bits. The two sequences of soft bits may then be compared and combined to create a sequence of hard bits. For example, in some embodiments, a soft bit combiner may combine the two sequences of soft bits into a third sequence of soft bits, which may then be input into a decoder to produce the final decoded hard bits. The secondary demodulator may be less complex, less expensive, demand less power, and/or require fewer computational resources when operating, than the first demodulator.

Abstract: Disclosed herein is a reception apparatus, including an acquisition section adapted to receive a signal which includes at least one of a first signal and a second signal which have different structures from each other except that the first and second signals have a preamble signal and acquire the preamble signal from the received signal; a detection section adapted to detect a value for correcting the signal using the signal; and a correction section adapted to correct, if it is decided based on the preamble signal acquired by the acquisition section that the signal is the first signal, the signal using the value detected by the detection section.

Abstract: A digital differential signal transmitter circuit for a low supply voltage. A phase correction circuit for correcting digital signals transmitted through two signal paths in such a way as to have a phase relationship of differential signals and duty cycle correction circuits for correcting the digital signals in such a way as to maintain signal integrity in spite of changes in process, supply voltage and temperature are installed on the two signal paths so that the distortion of digital differential signals is compensated for. Power consumption at a final output section of the transmitter circuit is reduced. Impedances of the transmitter circuit and transmission lines are matched so that the transmitter circuit can operate insensitively with respect to operation circumstances.

Abstract: Systems and methods for performing phase tracking scheme for an Analog to Digital converter based tuner. In many embodiments, a phase tracking scheme is used that includes a phase locked loop that corrects the phase of the output signals and an amplitude modulation compensator that modulates the amplitude of the output digital signals to compensate for phase noise based upon the received output digital signals.

Abstract: A wireless communication modem (2) receives data (10) sent from a host device (4) in a nonprocedural manner, then subjects the received data (10) to protocol conversion, and transmits the converted data to a server (8) via a wireless communication network (6). The wireless communication modem (2) has an on-request transmission mode in which the data (10) is transmitted to the server (8) only when a connection from the server (8) to the wireless communication modem (2) is established.

Abstract: A method and system for the transmission of digital data (210) over existing analog radio frequencies (230) is presented, wherein the digital data may include audio data, visual data or audio-visual data for presentation either with analog broadcast data or at a selectable time. The digital data may be transmitted over a plurality of sub-channels that have varying degrees or reliability (250). A “quality-of-service” process manages the transmission of digital data over various sub-channels based on the reliability of the sub-channel, the amount of digital data and the type of digital data to be transmitted. The digital data may further be encrypted and authenticated.

Abstract: A system and method for determining a propagation delay between nodes in a packet network are provided. The system and method include sending a ping packet from a source node to a destination node, determining an intermediate node delay of the ping packet at an intermediate node and recording the intermediate node delay in the ping packet and determining the propagation delay at the destination node by using the intermediate node delay.

Abstract: A stochastic signal generation circuit includes a signal output circuit and a signal processing circuit connected with the signal output circuit. The signal output circuit includes two matching semiconductor components, wherein the signal output circuit detects a slight mismatch between the two matching semiconductor components, converts the detected slight mismatch into a corresponding electric signal, amplifies the electric signal, and outputs an analog voltage signal. The signal processing circuit converts the analog voltage signal into a stochastic digital signal. Also, a method for generating a stochastic signal is provided. The present invention decreases the cost of the integrated circuit, and better ensures the information security of the electronic products.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Abstract: One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.

Abstract: Techniques for sending hierarchical feedback of channel state information are described. In one design, a user equipment (UE) determines channel gain information for multiple cells selectable to transmit data to the UE. The UE also determines intra-cell relative phase information for at least one cell among the multiple cells. The UE reports the channel gain information and the intra-cell relative phase information. The channel gain information may include multiple quantized channel vectors for each of the multiple cells. The intra-cell relative phase information may indicate phase errors in the quantized channel vectors for each of the at least one cell. The UE may also determine and report other information. The UE may receive data from one or more cells among the plurality of cells. Each cell may transmit data based on at least one transmit vector determined based on the channel gain information and the intra-cell relative phase information.

Abstract: Precise operation of an accelerator operating member (7) is more difficult to perform in a reversing operation of a vehicle (1) as compared with an advancing operation. Therefore, behavior of the vehicle (1) is not smooth and thus tends to be unnatural. In the reversing operation of the vehicle (1), driving force output from an internal combustion engine (2) is limited in accordance with vehicle acceleration (D). At this time, it is possible to regulate the driving force of the vehicle (1) in conformity to the actual operation of the accelerator operating member (7) by the driver. In addition, limitation of the driving force is not executed in the advancing operation of the vehicle (1). At this time, the vehicle (1) can be driven in a state in which the driving force is comparatively small. Therefore, it is possible to prevent the behavior of the vehicle (1) from being unnatural.

Abstract: Signal processing and/or signal modulation includes tracking a phase parameter; determining a discontinuity; and compensating for the discontinuity.

Abstract: Disclosed herein is a signal processing apparatus, including: a computation device operable to perform transform computation adapted to Fourier-transform a time domain OFDM i.e., Orthogonal Frequency Division Multiplexing signal into a frequency domain OFDM signal; a processing device operable to perform carrier frequency offset detection adapted to detect an estimated carrier frequency offset that is an error of a carrier used for demodulation of the OFDM signal; and a carrier frequency offset correction device operable to perform carrier frequency offset correction adapted to correct the carrier frequency offset of the frequency domain OFDM signal in accordance with the estimated carrier frequency offset.

Abstract: A source synchronous signal synchronization system includes a differential signal receiver; a tunable input delay element coupled to the receiver; an input serializer/deserializer (ISerDes) coupled to the tunable input delay; an alignment unit coupled to the ISerDes; and a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit.

Abstract: In accordance with a representative embodiment, a method for reducing the effect of jitter in a sampled signal is described. The method comprises: obtaining a frequency-domain data set representing the sampled signal; obtaining an average sideband amplitude distribution generated by jitter around one or more principal frequencies of the signal; estimating the jitter phases for sidebands generated by jitter in the frequency-domain data set; subtracting a jitter contribution characterized by the average sideband amplitude distribution and the estimated jitter phases from the data record.

Abstract: A clock generating device includes: a DDS circuit that generates a periodic signal; and a comparator that compares an input signal and a reference signal and outputs a binary signal. The clock generating device includes a rate-of-change correcting unit that applies correction for increasing a rate of change at a crossing point with the reference signal to the periodic signal generated by the DDS circuit.

Abstract: A method and apparatus for measuring parameters of a receiver having a mixer for generating an I signal and a Q signal using an input signal, an I channel circuit for processing the I signal, and a Q channel circuit for processing the Q signal. The method includes feeding the receiver a first testing signal before the mixer. The method includes feeding the receiver a second testing signal on the I channel circuit. The method includes feeding the receiver a third testing signal on the Q channel circuit. The method includes measuring I/Q quadrature deviation and I/Q delay imbalance of the receiver using the first, the second, and the third testing signals. This separates the I/Q quadrature deviation and I/Q delay imbalance.

Abstract: The present invention discloses a clock dejitter method comprising: a data sending adapter module inputting data with a system clock and using a sending clock to send data; a clock dejitter module associating the system clock with the sending clock of the data sending adapter module using; and the clock dejitter module tracking variations in the system clock and a data enable signal reflecting data sending state by referring to the system clock, and dynamically generating the sending clock varying with the data sending state. The present invention also discloses a clock dejitter apparatus and a data transmission system. The present invention greatly improves the free scheduling processing ability of services and reduces the bit error rate of data transmission while increasing efficiency of large capacity data switch transmission by dynamically adjusting the sending clock.

Abstract: A method and an apparatus for measuring a phase shift between a first and a second signal, comprising the steps of shifting the first signal in frequency by an offset frequency, superposing the frequency-shifted first signal and the second signal, determining an envelope signal of the superposed signal, and measuring a phase shift of the envelope signal at the offset frequency, or a multiple thereof, with respect to the phase of the offset frequency, wherein the phase shift is measured by determining a Fourier coefficient of the envelope signal at the offset frequency and extracting its phase. The invention further relates to an apparatus implementing the method.

Abstract: According to an aspect of the embodiment, According to an aspect of the invention, a signal transmission apparatus transmits a first signal to a transmission line. The apparatus measures a reflection characteristic of the transmission line based on a signal resulting from reflection of the first signal, and measures a transmission characteristic of the transmission line based on a signal resulting from transmission of the first signal through the transmission line. The apparatus determines a transmission clock frequency and a multi-value number based on the reflection characteristic and the transmission characteristic, and modulates information using the transmission clock frequency and the multi-value number to transmit a second signal resulting from the modulation to the transmission line. The apparatus receives the second signal through the transmission line and demodulates the received second signal.

Abstract: A device for determination of the frequency discrepancy (105) between a mobile radio and a base station which is transmitting a sequence of symbols, having a unit (6-11) for calculation of terms, with one term being formed from two symbols in the sequence received by the mobile radio, and in which case the phase difference of the two symbols can be determined from the term, a unit (14, 15) for formation of groups from the terms, with one term being assigned to one group on the basis of features of the symbols on which it is based, and a unit (39) for calculation of the discrepancy (105) on the basis of a group.

Abstract: Waveform data of selected bits having jitter or noise is generated wherein the waveform date represents a serial digital signal. A signal generator displays a jitter/noise setting area and a bit selection area on a display device where jitter or noise is set and the jitter or noise settings are applied to only the bit selected with the bit selection area. The bit is selected through various ways. A user may directly input a bit pattern to be selected. Box objects corresponding to the respective bits in the digital signal may be displayed and one or more of the bits can be selected by selecting one of the box objects. Frequently used bit patterns may be stored and provided using a menu-driven interface for selecting a bit pattern. An arbitrary number of consecutive bits may be designated for receiving jitter or noise and displayed.

Abstract: A data processing device which performs a data transmission between semiconductor devices using a plurality of signal lines. In the data processing device, when there occurs an error in a data transmission from a transmitting device to a receiving device using a plurality of signal lines, data in which the error has occurred is stored. The stored data is compared bit by bit with non-erroneous data, thereby designating a bit in which error has occurred in the stored data.

Abstract: A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.

Abstract: To provide a signal generator, a signal generating system, and a signal generating method capable of repeatedly generating an arbitrary waveform and making the phases of the head and tail of the generated waveform continuous with each other, without changing the frequency of the waveform. A signal generator (10, 11, 12) includes phase shift means (30) that receives waveform data which is repeatedly output n times, shifts the phase of each sample data item in an n-th waveform data item by a phase shift amount ?n corresponding to the number of times n the waveform data is repeatedly output, and outputs the waveform data to D/A conversion means.