Abstract: A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired.

Abstract: In a method and a device for decoding a signal, the signal is transmitted via at least one connecting line of a data transmission system, in a user of the data transmission system receiving the signal. It is provided to measure the interval of a change—provided compulsorily in a transmission protocol used in the data transmission system—of the signal from rising to falling or from falling to rising edge. A tendency for an asymmetrical delay of the signal can be ascertained from the measured interval. The sampling of the bits of the received signal can be improved as a function of the interval or of the asymmetrical delay, for example, by setting the sampling instant in variable fashion. Alternatively, the interval or the asymmetrical delay can be utilized for diagnostic purposes.

Abstract: A method for testing output of an electrical device includes the following steps: a device being tested transmits a first signal to a test platform through a channel being tested. A signal received through the channel being tested by the test platform is compared with the first signal to determine if the received signal corresponds to the first signal. The channel being tested is determined to be normal if the received signal corresponds to the first signal. The channel being tested is determined to be abnormal if the received signal does not correspond to the first signal.

Abstract: A clock regeneration circuit according to the present invention that generates a clock signal that is synchronized to an input signal, includes: a detection section which detects points at which the input signal transitions; a histogram generation section which associates a plurality of partial periods with the transition points, and generates a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal; a calculation processing section which generates a second histogram by calculation processing based on the first histogram, and calculates a phase adjustment value of the clock signal based on the second histogram; and a phase adjustment section which adjusts a phase of the clock signal based on the phase adjustment value.

Abstract: A test circuit capable of reducing the number of data I/O pins of a tester at a read operation includes a data masking control unit for masking a part of output data in response to an activation of one of an upper data masking signal to control a group of upper data pins and a lower data masking signal to control a group of lower data pins when a test mode signal is activated at a read operation.

Abstract: Processing of a signal received at a node in a network is described in which effects on the signal caused by applying an action to a first part of the signal are quantified based on characteristics of the first part of the signal and effects on the signal caused by not applying the action to the first part of the signal are quantified based on characteristics of a second, subsequent part of the signal. The action may then be selectively applied either to the first part of the signal or to the second part of the signal based upon the quantifications. In some embodiments, the action is applied to a portion of the signal for which the effects on at least one measure of the signal quality are less detrimental.

Abstract: Systems and techniques for communication using coordinated multi-point transmission. In one embodiment, an apparatus comprises at least one processor and a memory storing a set of computer instructions, configured. The processor is configured to cause the apparatus to determine a linear phase variation between at least first and second transmissions from first and second transmission points based at least in part on a propagation delay difference between the first and second transmissions, and transmit the phase variation information for at least the first and the second transmissions.

Abstract: A nonlinear filter includes: a determination unit that determines, based on I and Q signals inputted into the determination unit, whether or not to perform pulse insertion; a rotation detector that detects a rotation direction of the I and Q signals on an IQ plane with respect to the origin of the IQ plane; a pulse generator that generates, when the determination unit determines to perform the pulse insertion, a pulse of which at least one of the direction and the magnitude is determined in accordance with at least the detected rotation direction; and an adder that inserts the pulse into the I and Q signals and outputs resultant I and Q signals.

Abstract: A method for uplink transmission based on a time division duplex (TDD) system is provided. In the method, a terminal measures downlink channel state information, estimates the state information of the uplink spatial channel using the channel reciprocity of the TDD system, and selects an uplink spatial pre-coding matrix using the state information of the uplink spatial channel based on a certain criterion, the terminal executes spatial pre-coding using the selected pre-coding matrix, and transmits the data stream to a base station via terminal transmit antennae. A terminal, a base station and a system which are based on the method are also provided. The invention uses the reciprocity of the TDD system channel fully to achieve the maximal channel capacity, thereby optimizes the uplink spatial-transmission.

Abstract: A system and method for low-cost performance and compliance testing of local oscillators and transmitters for wireless RF applications. A preferred embodiment comprises observing a digital signal from within an RF circuit, manipulating the signal with digital signal processing techniques, and determining if the RF circuit passes a test based upon results from the manipulating. Since the signal is clocked at a much lower frequency than an RF output of the RF circuit and the manipulation is performed digitally, testing can be performed at different stages of the production cycle and expensive test equipment can be eliminated.

Abstract: An embodiment is a method and apparatus to estimate channel quality. An absolute processor computes absolute real and imaginary values of real and imaginary parts, respectively, of output of a demodulator. A phase count unit generates first and second phase counts representing deviations from zero phase noise using the absolute real and imaginary values. An amplitude count unit generates first and second amplitude counts representing attenuation of a received signal using the absolute real and imaginary values. An integrator integrates the first and second phase counts and first and second amplitude counts into a signal quality indicator that represents a measure of quality of channel with respect to noise and fading.

Abstract: Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.

Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: A method in a receiver includes receiving from a transmitter an instruction to check for messages from the transmitter at intervals having a specified time period. A frequency error of the receiver relative to the transmitter is estimated at the receiver, and an actual time period that does not exceed the specified time period is selected based on the estimated frequency error. The receiver is activated periodically according to the selected actual time period so as to reset the frequency error.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit.

Abstract: An apparatus for transferring data in a non-spread domain to a spread domain. The apparatus comprises a first-in-first-out (FIFO) memory; a write pointer generator adapted to generate a write pointer for writing data into the FIFO memory in response to a non-spread clock signal; a spread-clock generator adapted to generate a spread clock signal based on the non-spread clock signal; a read pointer generator adapted to generate a read pointer for reading data from the FIFO memory in response to the spread clock signal; and a controller adapted to control the spread-clock generator in response to the read and write pointers indicating predetermined potential data overflow or underflow of the FIFO memory.

Abstract: Systems, methods and apparatuses for reducing HARQ retransmissions using peak power management techniques are presented. In one example, a receiver may perform multi-level error correction for reducing HARQ retransmissions. The receiver may include a Peak-to-Average-Power Ratio Management Module (PAPR MM) decoder configured to perform a first level of error correction utilizing retransmissions originating at a front end of a distal transmitter. The receiver may further include a symbol demapping module connected to the PAPR MM decoder, a deinterleaver connected to the symbol demapping module, and a decoder connected to the deinterleaver and the PAPR MM decoder, where the decoder may be configured to perform a second level of error correction utilizing retransmissions originating at a back end of the distal transmitter. A transmitter for reducing HARQ retransmissions using PAPR techniques is also presented.

Abstract: A method and apparatus controls diversity reception in a wireless communication device. By determining a value based on a number of active set pilot signals received from a set of base stations, the wireless communication device dynamically enables or disables diversity reception. Diversity reception can be controlled by adjusting a diversity threshold based on the determined value. A channel quality indicator of a channel is measured and compared against the adjusted diversity threshold. The diversity reception mode is then enabled or disabled based on the comparison. For example, if the number of active pilot signals is above a predetermined value, indicating “good” coverage, the diversity threshold is decreased. The measured channel quality indicator is compared against the adjusted threshold, and diversity reception is enabled when the channel quality indicator is less than the decreased diversity threshold.

Abstract: A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator; determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.

Abstract: This disclosure relates systems and methods for a high bandwidth modulation and transmission of communication signals.

Abstract: A method and apparatus of calibrating I/Q mismatch of a communication circuit is disclosed. The disclosure employs I/Q test signals respectively including different frequency components to calibrate the frequency-dependent I/Q mismatch existing in the communication system.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: According to some embodiments, a method and apparatus are provided to generate a sine wave via a jitter modulator to modulate a control voltage of a clock source. The jitter modulator is in-situ on a die. The sine wave is received at a clock and data recovery circuit comprising the clock source. The clock and data recovery circuit is in-situ on the die.

Abstract: The invention relates to background noise estimation in wireless communication systems with power control. The total received interference is measured at a receiving unit. Thereafter, a predetermined noise signal is injected at the receiving unit and the total received interference is measured again, preferably when the power control of the system has responded to the noise injection. The background noise is calculated based on the injected predetermined noise signal and the interference measurements before and after the noise injection.

Abstract: An Arbitrary Waveform Generator has a controller programmed to generate a sequence of test waveforms using previously-defined waveform data files. The controller generates this series of test waveforms by direct synthesis to cause each waveform to contain a respective different predetermined amount of Rj, Sj and ISI jitter components. In this way, the Arbitrary Waveform Generator produces a sequence of waveforms incorporating varying amounts of ISI to sweep the ISI jitter components from an initial amount of ISI, for example, zero ISI, and continually increment the amount of ISI to a full unit interval of ISI in predetermined increments, for example, 0.1 UI steps.

Abstract: An effective data sequence based timing error detector (EDS-TED) for baseband transmission system using Tomlinson-Harashima Precoder is disclosed. The EDS-TED extracts timing error information embedded in the received signal to build up autocorrelation between the ESD signals and minimize the mean square error between the received and desired EDS so as to improve the performance of the TED in terms of Peak-to-Peak Jitter and TED gain. Thus the quality of the received signal increases and the error rate decreases.

Abstract: A device and method for producing Inter Symbol Interference (ISI) scaling of S-Parameter Touchstone files for the generation of ISI scaling effects on serial data patterns by direct digital synthesis is described. The features of the present invention allow user to set parameters such as data rate, voltage amplitude, encoding scheme etc. as per requirements for the serial data patterns. An ISI scaling value is selected and applied to an S-Parameter Touchstone file representing transmission path effects. The serial data pattern parameters and the ISI scaling value used with the S-Parameter Touchstone file are compiled to generate a digital data waveform record file. The digital waveform record file is applied to a waveform generation circuit for converting the digital data into an analog serial data pattern with ISI scaling effects.

Abstract: Systems and methods for receiving an OFDM preamble without knowledge of channel characteristics are provided. An OFDM preamble signal with frequency shifted cyclic extensions is received. Taken together the cyclic extensions form a frequency shifted version of the OFDM preamble signal. Frequency offsets and timing offsets are estimated and corrected in an efficient manner using a simple concatenation approach in the time domain, followed by a summation of the OFDM preamble signal and the concatenation after a transformation of the OFDM preamble and the concatenation into the frequency domain. Phase errors in the frequency domain are estimated and corrected after FFT transformations of the received signals. A valid preamble is detected and additional parameters for receiving subsequently transmitted OFDM symbols in a channel are extracted from the OFDM preamble. The methods are computationally efficient and robust. Receiver implementations for performing the methods in a DVB receiver are disclosed.

Abstract: It is an object of the invention to correctly display the waveform of a demodulation signal with a single apparatus. A jitter demodulator which demodulates a jitter component of a digital signal input from the outside, a jitter amount detector which detects the amplitude value of a demodulation signal output from the jitter demodulator, an interpolator which measures a period of the demodulation signal output from the jitter demodulator and interpolates the demodulation signal processing with a rate corresponding to the measured period, a display unit, and a display control section which displays on the display unit the value detected by the jitter amount detector and a waveform of the demodulation signal interpolated by the interpolator are provided in a single housing.

Abstract: A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin.

Abstract: A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.

Abstract: An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.

Abstract: An integrated circuit 2 includes a serial data transmitter 12 and a serial data receiver 14. A signal amplitude distorting circuit 30 is provided to introduce distortion in the amplitude of a serial data signal generated by the serial data transmitter 12 and looped back to the serial data receiver 14 so as to stress test the serial data receiver 14.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Abstract: A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.

Abstract: Various embodiments of the present invention relate to a discrete denoiser that replaces symbols in a received, noisy signal with replacement symbols in order to produce a recovered signal less distorted with respect to an originally transmitted, clean signal than the received, noisy signal. Certain, initially developed discrete denoisers employ an analysis of the number of occurrences of metasymbols within the received, noisy signal in order to select symbols for replacement, and to select the replacement symbols for the symbols that are replaced. Denoisers that represent examples of the present invention use blended counts that are combinations of the occurrences of metasymbol families within a noisy signal to determine the symbols to be replaced and the replacement symbols corresponding to them.

Abstract: Test signal generator (3) generates test signals represented, by four points, which comprise two sets of two points positioned in point symmetry with respect to the origin of an I/Q orthogonal coordinate system. Envelope detector (8) detects the amplitude of an envelope of the output signal from an orthogonal modulator when the test signals represented by four points are generated, and outputs a signal proportional to the square of the amplitude. Comparing unit (9) calculates an average value of output signals from envelope detector ( ) when the test signals represented by the two points of each set are generated. Controller (10) adjusts the amplitudes and/or phases of the test signals so that the average values produced when the test signals represented by the two sets of the two points are generated are equal to each other, and calculates an I/Q mismatch quantity based on the adjusted results.

Abstract: An integrated circuit is provided comprising: a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The integrated circuit further comprises a duty cycle distortion circuit so that the integrated circuit can be stress tested by distorting the duty cycle of a signal within the integrated circuit.

Abstract: A phase-locking loop (PLL) for use with orthogonal frequency division multiplexed signals. In one embodiment, a wireless receiver includes a PLL is configured to reduce phase and frequency divergence between the wireless receiver and a transmitter of a packet received by the wireless receiver. The PLL includes a loop bandwidth controller. The loop bandwidth controller is configured to set a bandwidth of the PLL to a first value for reception of an initial symbol of the packet. The loop bandwidth controller is configured to reduce the bandwidth of the PLL over a number of symbols preceding an initial header of the packet.

Abstract: High Speed I/O interfaces such as DVI, S-ATA or PCI-Express require expensive test equipment. Loop-back tests are widely used as one alternative, but lack coverage of timing-related defects. A system and method for on-chip jitter injection using a variable delay with controllable amplitude and high accuracy is provided that improves the coverage of loop-back tests.

Abstract: A preamble noise cancellation circuit according to an aspect of the invention may include: a coupler dividing an input signal; a preamble noise detection unit subtracting a predetermined reference preamble signal from a received preamble signal output from the coupler to detect preamble noise included in the received preamble signal; and a noise cancellation unit subtracting the preamble noise detected by the preamble noise detection unit from the received preamble signal output from the coupler.

Abstract: The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by the delayed jitter signal.

Abstract: The data processing unit (15) for a receiver of signals carrying information (1) includes a clock and data recovery circuit (16) on the basis of a data signal (DOUT), and a processor circuit (17) connected to the clock and data recovery circuit. The clock and data recovery circuit is clocked by a local clock signal (CLK) and includes a numerical phase lock loop, in which a numerically controlled oscillator (25) is arranged. This numerically controlled oscillator generates an in-phase pulse signal (IP) and a quadrature pulse signal (QP) at output. The frequency and phase of the pulse signals IP and QP are adapted on the basis of the received data signal (DOUT). The processor circuit is arranged to calculate over time the mean and variance of the numerical input signal (NCOIN) of the numerically controlled oscillator (25), so as to determine the coherence of the data signal if the calculated mean and variance are below a predefined coherence threshold.

Abstract: In a compensator for compensating mismatches, and in methods for such compensation, the compensator compensates for mismatches in output signals of a system with mismatches during normal operation of the system with mismatches. The compensator comprises: a mismatch estimator that monitors at least two mismatched signals output by the system with mismatches during normal operation and that generates matching parameters indicating an amount of mismatch between the at least two mismatched signals, the mismatch estimator updating the matching parameters during normal operation of the system with mismatches, and a mismatch equalizer that compensates mismatches in the mismatched signals output by the system with mismatches during normal operation of the system with mismatches in response to the matching parameters.

Abstract: A measurement apparatus that measures, as an error under measurement, at least one of a gain error and a phase error of a quadrature demodulator or a quadrature modulator as a measurement target. The measurement apparatus includes an output control section that causes the measurement target to output a signal, a detecting section that detects a measured signal representing a real component and an imaginary component of the signal output from the measurement target, and a calculating section that calculates, as the gain error or the phase error, a solution for a variable that maximizes a correlation value between the measured signal detected by the detecting section and an ideal signal that includes the error under measurement as the variable and that represents the measured signal that should be output by the measurement target.

Abstract: Methods for processing a signal of interest in an electrical power system are provided, as well as systems and computer program products for carrying out the methods. The methods include obtaining a representative window of data points from the signal of interest; obtaining a window of interest containing data points from the signal of interest; and comparing a phase drift compensated window to the representative window, wherein the compensated window is calculated in accordance with the window of interest and a phase drift that is present in the window of interest relative to the representative window.

Abstract: Various embodiments relate to an in-system measurement of clock signals in a communications circuit. A circuit may include a central processing unit and at least one phase error counter (PEC) that uses a measurement clock to determine the accuracy of a target signal. In some embodiments, the PEC may include a counter that compares a clock signal produced by a reference oscillator with the signal of the measurement clock by generating an oscillator phase error based the measured difference during a target period. In some embodiments, the PEC may measure the performance of a clock recovery module by measuring a difference between a produced recovered clock signal and the measurement clock signal, which may be the clock recovery phase error between the two signals. The CPU may also use the measured phase errors to determine other values related to the target signal(s).

Abstract: A communication apparatus for a continuous phase modulation signal. The communication apparatus includes a first processing unit configured to generate first information of the continuous phase modulation signal using first symbol data; a symbol converting unit configured to convert the first symbol data into second symbol data or convert the second symbol data into the first symbol data; a symbol storage unit configured to store the second symbol data; a second processing unit configured to second information of the continuous phase modulation signal using the second symbol data stored in the symbol storage unit; a third processing unit configured to generate third information of the continuous phase modulation signal using a modulo operation of an integer related to a modulation index; and an output unit configured to add an output from the third processing unit and an output from the first processing unit and generate the continuous phase modulation signal.

Abstract: A jitter measuring method and device, which is capable of measuring jitters in serial digital signal without high-frequency reference clock. The jitter measuring device comprises a rough length measuring unit for measuring rough length for each pulse of the serial digital signal according to a reference clock, and a phase error measuring unit for measuring the phase errors between the edges of the reference clock and the serial digital signal by multi-phase clocks, which are generated by a multi-phase generator according to the reference clock. The jitter measuring device computes the precise length according to the rough length and the phase error, and measures the jitters from the precise length by filters.