Abstract: A passive equalizer circuit is embedded within a substrate of a package containing an integrated circuit. It is believed that substantial reduction in uneven frequency dependent loss may be achieved for interconnects interconnecting the integrated circuit with other integrated circuits on a printed circuit board. Other aspects are described and claimed.

Abstract: Teachings presented herein offer the performance advantages of sequence estimation for received signal symbol detection, while simultaneously providing potentially significant reductions in computational overhead. Initial demodulation of a received signal identifies a reduced number of candidate symbol values for all or a subset of a sequence of symbols represented in a received signal. A sequence estimation process, e.g., an MLSE process, constrains its state spaces to the reduced number of candidate symbols values, rather than considering all possible symbol values.

Abstract: A receiver may receive a signal that was generated by passage of symbols through a non-linear circuit. An equalizer of the receiver may equalize the received signal based on a first non-linearity compensated, inter-symbol correlated (ISC) feedback signal to generate an equalized signal. The receiver may correct a phase error of the equalized signal to generate a phase-corrected equalized signal. The phase correction may be based on a second, non-linearity compensated, inter-symbol correlated (ISC) feedback signal.

Abstract: A communications circuit includes a filter module with a sampling window, a control module, and an input buffer. The control module has a ray parameter interface to obtain information regarding significant ray changes that make it desirable to re-position the sampling window. The control module determines re-positioning parameters, responsive to this information, which reflect the re-positioning of the sampling window. The input buffer obtains samples of a received signal and outputs received signal data to the filter module. The filter module obtains the re-positioning parameters from the control module, and the filter module and control module temporally re-position the sampling window in duration and/or location in accordance with the re-positioning parameters, and output a filtered chip.

Abstract: An apparatus including an adder, a delay line, and a first detector. The adder may be configured to generate an input signal in response to a received signal and a feedback signal. The feedback signal may include a contribution from each of a plurality of delayed versions of the input signal. The contribution from each of the plurality of delayed versions of the input signal may be determined by a respective weight value. The delay line may be configured to generate the plurality of delayed versions of the input signal. The first detector may be configured to recover a data sample from the input signal in response to a clock signal.

Abstract: Methods and systems are provided for timing synchronization for reception of highly-spectrally efficient communications. An example method may include, filtering, in a receiver, a received inter-symbol correlated (ISC) signal to generate a filtered ISC signal. The method may further include locking to a timing pilot signal of the filtered ISC signal. The timing pilot signal may include a sub-harmonic frequency of a clock signal associated with the received ISC signal. A timing pilot estimate signal of the timing pilot signal may be generated. The timing pilot estimate signal may be cancelled from the filtered partial response signal to generate an output ISC signal. The timing pilot signal includes a signal at ±(1/n*Fbaud), where n is an integer greater than 2, and Fbaud is a symbol rate of the clock signal. The clock signal may be recovered from the filtered ISC signal.

Abstract: This invention relates to methods and apparatus for equalizer adaptation for compensating for channel distortion on received data signals. The method comprises, for each bit, forming an adjusted bit signal comprising a weighted contribution from at least one other bit period. The polarity of the adjusted bit signal is determined and the bit is categorized as a hard, i.e. high confidence, bit is the bit is above an upper threshold or below a lower threshold or otherwise is categorized as a soft bit. The weightings are adjusted based on the category of the bit wherein a first adjustment is made it the bit is categorized as a soft bit but a second, different adjustment is made if the bit is categorized as a hard bit. For a soft bit the weightings may be increased for bits which have the same polarity as the bit in question and decreased for bits of opposite polarity.

Abstract: A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.

Abstract: A combiner system for frequency combining and related methods. Implementations may include a plurality of combiner stages each including a deinterleaver, at least one filter, a frequency downconverter, and a frequency upconverter all operatively coupled together. Each of the plurality of combiner stages may be adapted to receive a complex interleaved input signal including two or more input signals each including a bandwidth, to output a complex stage output signal including the two or more input signals, and to alternately place the bandwidth of each of the two or more input signals in an upper portion and in a lower portion of an output bandwidth of the complex stage output signal. The upper portion and lower portion of the output bandwidth may be contiguous within the output bandwidth and joined at a center of the output bandwidth.

Abstract: Methods and systems are provided for coarse phase estimation for highly-spectrally efficient communications. An example method may include, equalizing, in a receiver, a received inter-symbol correlated (ISC) signal to generate an equalized ISC signal. A phase adjustment signal may be generated based on an ISC feedback signal. The ISC feedback signal may be generated using a sequence estimation process and a non-linearity function. A phase of the equalized ISC signal may be adjusted using the generated phase adjustment signal, to generate a phase adjusted partial response signal. The phase adjustment signal may be generated based on a phase difference between the equalized ISC signal and the partial response feedback signal. At least one ISC vector may be generated by buffering samples of the phase adjusted ISC signal.

Abstract: A communication system and method that allows a transmitter segment (ground end of uplink segment) to dynamically combine power from a plurality of propagation channels (transponders) to improve power levels of signals being transmitted, without affecting the receiver segment (user end of downlink segment) and the propagation segment (space segment), and without modifying propagation apparatus configurations (satellite). Specifically, the transmitter segment generates mixtures of input signals by using Wavefront-Multiplexing and transmits wavefront-multiplexed (WFM) signals through propagation channels to a receiver segment that coherently separates the mixtures of received WFM signals by using adaptive equalization and Wavefront-De-Multiplexing.

Abstract: Tools capable of improving the accuracy of decision feedback equalization (DFE) are described. The tools may adapt a DFE using a more-equal distribution of signals than those actually received. The tools may do so by disregarding, averaging, or weighting certain signals when adapting the DFE when those signals represent an unequal distribution of bit patterns. In one example, the tools detect and disregard some of the signals representing idle bit patterns that are received more often than other bit patterns. The tools may also or instead compensate for a bit pattern that is never or rarely received.

Abstract: An iterative joint Minimum Mean Square Error (MMSE) decision feedback equalizer and turbo decoder includes a turbo decoder portion and a decision feedback equalizer (DFE) portion. The DFE receives input signals and processes these input signals to generate an estimated symbol sequence that is communicated to the turbo decoder portion. The estimated symbol sequence is also communicated to the feedback portion of the DFE. The feedback portion of the DFE includes a symbol-by-symbol detector and a feedback filter. The soft decoder output values generated by the turbo decoder portion are communicated to the feedback portion of the DFE and are combined with the coded output as log likelihood ratio values in a multipass, iterative fashion whereby the equalizer and decoder are linked via iterative feedback to provide communication performance enhancement.

Abstract: A transmission system to transmit a transport stream (TS) having normal data and additional data, the transmission system including: a stream constructor to generate a TS, and a multiplexer (MUX) to insert information representing the characteristics of additional data in the TS. Therefore, it is possible for a reception system to use the additional data efficiently.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

Abstract: An algorithm to detect single path channel conditions and reduce the span (number of taps) of the equalizer in order to mitigate the performance degradation caused by noisy equalizer taps is disclosed. The algorithm provides two novel components comprising single path scenario detection and single path scenario processing or (equalizer shortening). A single path scenario is detected when the energy concentrated in a single channel impulse response tap divided by the total energy of the taps exceeds a predetermined threshold. When a single path scenario is detected, only the equalizer taps within a variable window around the equalizer tap having concentrated energy are used to filter the received signal.

Abstract: An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

Abstract: The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.

Abstract: A receiver includes an adaptive equalizer, a power detecting unit and an adjusting unit. The adaptive equalizer is for receiving a signal and generating an equalized signal. The power detecting unit, coupled to the adaptive equalizer, is for detecting the strength of the equalized signal during a first period to generate a first strength signal, and detecting the strength of the equalized signal during a second period to generate a second strength signal. The adjusting unit, coupled to the power detecting unit and the adaptive equalizer, is for adjusting the compensation strength for the adaptive equalizer according to the first and second strength signals.

Abstract: The present invention provides a signal processing device. The signal processing device includes a first feed forward equalizing unit, a first data slicing unit, a second feed forward equalizing unit, and a second data slicing unit. The first feed forward equalizing unit is utilized for performing a compensation operation according to a digital input signal so as to generate a first equalized signal. The first data slicing unit is coupled to the first feed forward equalizing unit, and utilized for generating a first output signal according to the first equalized signal. The second feed forward equalizing unit is coupled to the first data slicing unit, and utilized for generating a second equalized signal according to the first equalized signal. The second data slicing unit is coupled to the second feed forward equalizing unit, and utilized for generating a second output signal according to the second equalized signal.

Abstract: Embodiments of the invention are generally directed to a high-speed differential energy difference integrator (EDI) for adaptive equalizers. In an embodiment, the EDI includes two differential full-wave rectifiers providing differential outputs that are cross-coupled to the inputs of an integration capacitor. In one embodiment, the active areas of the transistors of the differential full-wave rectifiers are substantially the same.

Abstract: A method is provided. The method includes receiving a carrier signal and analyzing the received carrier signal to identify at least one of a static multipath delay and a dynamic multipath delay in the signal. The method also includes configuring an equalizer based upon the at least one of the static and dynamic multipath delays.

Abstract: A method of processing broadcast data in a transmitting system includes randomizing enhanced data; Reed-Solomon (RS) encoding and Cyclic Redundancy Check encoding the randomized enhanced data to build an RS frame; encoding the enhanced data in the built RS frame at a coding rate of at least ½ or ¼; first interleaving the encoded enhanced data; deinterleaving the first interleaved enhanced data; first multiplexing enhanced data packets including the deinterleaved enhanced data with main data packets including main data; randomizing the main data in the multiplexed enhanced and main data packets; second interleaving the enhanced data in the multiplexed enhanced and main data packets and the randomized main data to output a data group having the interleaved enhanced data and the interleaved main data; trellis encoding data in the data group in a trellis encoding unit; and second multiplexing the trellis-encoded data with field synchronization data and segment synchronization data.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip.

Abstract: The invention is directed to a system and method of regulating a slicer for a communication receiver. A zero-crossing accumulator receives a slicer output from the slicer and accordingly determines a zero-crossing length of the slicer output. A threshold decision unit regulates at least one threshold value of the slicer according to the zero-crossing length.

Abstract: An analog-digital conversion system comprising at least one variable gain amplifier amplifying an input signal e, an analog-digital converter CAN digitizing said signal e, an interference-suppressing digital processing module, processing the digitized signal, also comprises a first automatic gain control AGC loop, called the analog AGC loop, that compares an estimate of the output power of the CAN converter with a control setpoint g1 called the control setpoint of the analog AGC loop, a gain ga used to control the variable gain amplifier being deduced from this comparison. The system also comprises a second automatic gain control AGC loop called the digital loop, said digital loop comparing an estimate of the power after the interference-suppressing digital processing with a predetermined control setpoint gn, the analog AGC loop being controlled by a control setpoint deduced from this comparison.

Abstract: A close-loop power calibration algorithm is performed on a wireless communication device to correct power amplifier pre-distortion or PADR correction curves. In addition to peak to average power ratio or PAPR detection techniques, an algorithm or process is implemented that uses a transmitted reference packet, such as an orthogonal frequency domain multiplexing (OFDM) packet. The reference packet is used to learn the linear response of a detector that measures output of the power amplifier. The transmitted packet can include a linear response. The included linear response can determined by subtracting a normal packet from the reference packet.

Abstract: A method for communication includes modulating data to produce a series of symbols defined in a signal space. The symbols are pulse-shaped using a given pulse shape. A signal, which includes a sequence of the pulse-shaped symbols (104A . . . 104C) transmitted at a symbol rate that is higher than a Nyquist rate defined for the given pulse shape, is transmitted to a receiver (40). Prior to pulse-shaping the symbols, Inter-Symbol Interference (ISI) in the signal is pre-compensated for by applying a lattice precoding operation to the symbols. The lattice precoding operation confines the symbols to a predefined volume (110) in the signal space and is computed independently of any feedback from the receiver.

Abstract: Methods and apparatus are provided for joint adaptation of filter values in two communicating devices, such as a link partner and a link device. The disclosed joint adaptation process initially adapts the filter coefficient values in a first of the two communicating devices until a predefined stopping criteria is satisfied. Thereafter, the filter coefficient values in a second of the two communicating devices are adapted once the predefined stopping criteria for the first communicating device is satisfied. The filter coefficient values can comprise coefficient values of a multi-tap filter. The predefined stopping criteria may determine, for example, whether the first of the two communicating devices is overequalized. The filter coefficient values can be determined by including a contribution of only certain cursor tap values of the channel impulse response.

Abstract: This invention relates to an apparatus and a method for controlling a filter coefficient. The filter coefficient control apparatus controls a coefficient of a filter of a phase recovering apparatus, and comprises a phase offset obtaining means, for obtaining a phase offset between a carrier and a local oscillation; an autocorrelation calculating means, for calculating an autocorrelation and related statistics of the phase offset; and a filter coefficient determining means, for determining the coefficient of the filter in accordance with the autocorrelation and related statistics.

Abstract: A transmission stream (TS) generating apparatus includes an adaptor which receives general data and generates a stream having a plurality of packets, and which provides adaptive field in some of the plurality of packets, and an inserter which inserts additional data into all the payload areas of some of the plurality of packets that are not provided with the adaptive fields. Because additional data is transmitted, without requiring adaptive field header in certain packet, a data transmission rate is increased.

Abstract: The device is used for decoding convolution-encoded reception symbols. In this context, transmission data are modulated with a modulation scheme to form symbols, which are encoded with a transmission filter to form convolution-encoded transmission symbols. A convolution-encoded transmission symbol contains components of several symbols arranged in time succession. These transmission symbols are transmitted via a transmission channel and received as reception symbols. The Viterbi decoder decodes the reception symbols by use of a modified Viterbi algorithm. Before running through the Viterbi decoder, the reception symbols are processed by a state-reduction device, which determines additional items of information relating to possible consequential states of the decoding independently of the decoding through the Viterbi decoder in every state of the decoding. The state-reduction device uses the additional items of information to restrict the decoding through the Viterbi decoder to given consequential states.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: Embodiments of a device include a receive multi-rate CDR unit communicatively coupled to a processor, the receive multi-rate CDR configured to receive signals from a cable and perform clock and data recovery on signals and a transmitter multi-rate CDR unit communicatively coupled to a processor, the transmit multi-rate CDR configured to send signals to the cable after performing clock and data recovery on the signals. Embodiments of the cable include a receiver equalizer configured to receive signals from a wire and a transmitter equalizer configured to receive signals from a connector of the cable and configured to transmit an equalized signal to the wire.

Abstract: Soft bit values are generated for received symbols transmitted based on a modulation constellation by demodulating the received symbols via a sequence of demodulation stages, each demodulation stage producing a symbol decision based on an effective constellation. Each effective constellation used by a non-final one of the demodulation stages includes subsets of centroids approximating a region of the modulation constellation. Adjacent ones of the subsets have one or more common points so that at least two adjacent subsets overlap. The soft bit values for the symbol decisions are determined based on detection metrics computed during demodulation for the points included in the effective constellation constructed incrementally over the sequence of demodulation stages, the effective constellation produced by the final demodulation stage being devoid of one or more points included in the modulation constellation.

Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving ground-referenced single-ended signals. A transmitter combines a direct current (DC) to DC converter including a flying capacitor with a 2:1 clocked multiplexer to drive a single-ended signaling line. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different signaling lines. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.

Abstract: Systems and methods for decoding data using a hybrid decoder are provided. A data signal that includes a codeword is received. A signal quality indicator for the data signal is computed. One of a plurality of decoders is selected based on the computed signal quality indicator. Each of the plurality of decoders is configured to decode information based on a different decoding technique. The codeword included in the data signal is decoded using the selected one of the plurality of decoders.

Abstract: The present invention relates to data processing techniques in multi-channel data transmission systems. In this invention, a method to efficiently deal with FEXT is proposed and a circuit architecture to implement the proposed MIMO-THP equalizer is developed for the application of high/ultra-high speed Ethernet systems. The proposed method relies on the fact that FEXT inherently contains information about the symbols transmitted from the far end transmitters and it can be viewed as a signal rather than noise. Compared with the traditional FEXT cancellation approaches, the proposed design inherits both advantages of MIMO equalization technique and TH precoding technique, thus having better performance. Unlike the existing MIMO-THP technology, the proposed design completely removes the feedback loops in the existing MIMO-THP architecture. Therefore, pipelining techniques can be easily applied to obtain a high-speed design of a multi-channel DSP transceiver.

Abstract: A MMSE equaliser taking into account delays in the reception of signals from plural users. Time delays in reception of signals from plural users may be known or can be measured or estimated and can be used to for the basis for the operation of the equaliser. A low computational complexity version of the equaliser and a regularized equalizer with further reduced complexity for asynchronous reception are also disclosed.

Abstract: The present invention discloses a communication system with a data-dependent superimposed training mechanism and a communication method thereof. The system uses a precoding module installed in front of the data-dependent superimposed training mechanism to precode data by a precoding matrix. The precoding matrix is a N×N unitary matrix, which is constructed by Q×Q precoding sub-matrix. Q is the block size N divided by the channel length. The precoding matrix can achieve full frequency diversity. Any two sets of data precoded by the precoding matrix must be different from each other, such that the receiver can effectively identify the data transmitted from the transmitter and the computational complexity of the receiver is reduced.

Abstract: A circuit for adaptive feedback equalization is disclosed. In one aspect, the circuit includes a frequency-domain feedforward filtering section and a feedback filtering section, a slicer to slice a block of equalized symbols, a summing module for summing outputs of the filtering sections thereby yielding the block of equalized symbols. First and second updating modules provide coefficient updates to the filtering sections. The updating modules are fed with a frequency-domain converted block of error signals indicating the difference between the block of equalized symbols at the slicer input and the block of sliced symbols at the slicer output and for computing updates using the frequency-domain converted block of error signals. A time-domain compensation module receives a time-domain version of the updated filter coefficients of the feedback filtering section and symbols of the block of sliced symbols. It adds a feedback error compensation signal to the block of equalized symbols.

Abstract: In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M?1. Matrix M is inverted by (i) decomposing the matrix M into a plurality of first sub-matrices, (ii) generating, based on the first sub-matrices and without any division operations, numerators for a plurality of second sub-matrices of the inverted matrix M?1, (iii) generating, based on the first sub-matrices and without any division operations, denominators for the second sub-matrices, and (iv) generating the second sub-matrices based on the numerators and denominators. The inverted matrix M?1 is processed to generate an output signal. Accordingly, a reduction in noise level from inaccuracy in division is achieved, and computational complexity is reduced.

Abstract: Methods and apparatus are provided for performing equalization of communication channels. In an embodiment of the invention, at least one tap can be selected from a set of feedforward taps of feedforward filter circuitry, where each tap of the selected at least one tap has a magnitude that is greater than or substantially equal to a magnitude of any tap of the set of feedforward taps that is not in the selected at least one tap. In addition, at least one tap can be added to a set of taps of feedback filter circuitry in communication with the feedforward filter circuitry. The invention advantageously allows for more efficient and reliable equalization of communication channels.

Abstract: A time-interleaved track-and-hold circuit includes a clock generator adapted to receive a global sine-wave clock signal and to generate therefrom multiple square-wave output clock signals of different phases. The track-and-hold circuit includes a switching array operative in at least a track mode or a hold mode. The switching array includes multiple switch circuits, each switch circuit adapted to receive an analog input signal, a corresponding one of the output clock signals, and the global sine-wave clock signal. Each switch circuit is operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and is operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the switch circuits.

Abstract: A timing recovery system that provides a timing estimate between a transmitter clock and a receiver clock. The system includes a down-converter that converts a received intermediate frequency signal in the receiver and down-converts, using Fs/4 down-conversion, the received signal into baseband in-phase and quadrature phase signals. The baseband in-phase and quadrature phase signals are sent to a direct down-converter that frequency shifts the in-phase and quadrature phase. The frequency-shifted in-phase and quadrature phase baseband signals are then low-pass filtered in order to isolate the frequency components of interest, reduce noise, and remove zeros that are artifacts of the Fs/4 down-conversion. The signals are sent to a square-law non-linearity circuit that provides squaring non-linearity to generate non-linear in-phase and quadrature phase signals. The non-linear in-phase and quadrature phase signals are sent to a single-pole, low-pass post-filter circuit that generates the timing estimate.

Abstract: A noise abatement method and system for impulse noise in an RF receiver where the RF analog signal is converted to a digital signal prior to being connected to a demodulator. Two filters are used to detect impulse noise signals even under out-of-band interferer conditions, and prevent the impulse noise from reaching the input to the demodulator. A first of the two filters detects impulse noise using signals lower than the frequency bandwidth of the desired signal, and a second of the two filters detects impulse noise using signals higher the frequency bandwidth of the desired signal. A mean magnitude of the signal is detected over a predetermined time T and is used to select which filter to use for noise abatement.

Abstract: An apparatus of automatic power control for burst mode laser transmitter and method are provided. In one implementation a method includes: pushing a first multi-bit data into a data memory; modifying the data memory to remove a condition of frequent transition in the data memory, if the condition of frequent transition is found; establishing a list of indices pointing to data transition of the data memory; and sequentially examining a respective run length of the data indexed by each entry in the list, modifying the associated data to lengthen the respective run length if the respective run length is too short, modifying the associated data to shorten the respective run length if the respective run length is too long, and outputting a second multi-bit data by taking data from the data memory.

Abstract: The disclosure is a device and a method for receiver-equalizer calibration, in which the device includes an adaptive filter, a Clock Data Recovery (CDR) unit, an adaptive control unit and a run length encoding unit. The adaptive filter receives a channel signal, calibrates the channel signal according to a filter control signal and compensates the channel signal to obtain a compensative signal. The CDR unit receives the compensative signal to generate a sampling clock signal, a data signal and a transition sampling signal. The run length encoding unit receives the data signal and run-length encodes the data signal to generate first code data and second code data. The adaptive control unit receives the first code data, the second code data, the data signal and the transition sampling signal, and performs weight calculation to adjust the filter control signal.