Accumulator Or Up/down Counter Patents (Class 375/236)
  • Patent number: 11700368
    Abstract: A method of video processing includes determining, for a conversion of a block of a video picture in a video and a bitstream representation of the video, gradients of a subset of samples in a region for a classification operation in a filtering process. The region has a dimension of M×N and the block has a dimension of K×L, M, N, K, L being positive integers. The block is located within the region. The method also includes performing the conversion based on the determining.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: July 11, 2023
    Assignees: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD., BYTEDANCE INC.
    Inventors: Li Zhang, Kai Zhang, Hongbin Liu, Yue Wang
  • Patent number: 11553179
    Abstract: A method of video processing includes determining a classification of samples of a block in a video picture of a video according to a rule, wherein the video picture is divided into multiple regions, and wherein the rule disallows use of neighboring samples of a current sample across one or more boundaries of the multiple regions for the classification. The one or more boundaries of the multiple regions comprises a virtual boundary for an adaptive loop filtering (ALF) process. The method also includes performing a conversion between the block and a bitstream representation of the video by selectively applying the ALF process according to the classification.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: January 10, 2023
    Assignees: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD., BYTEDANCE INC.
    Inventors: Li Zhang, Kai Zhang, Hongbin Liu, Yue Wang
  • Patent number: 11394969
    Abstract: A method of video processing includes determining a classification of samples of a block in a video picture of a video according to a rule, wherein the video picture is divided into multiple regions, and wherein the rule disallows use of neighboring samples of a current sample across one or more boundaries of the multiple regions for the classification. The one or more boundaries of the multiple regions comprises a virtual boundary for an adaptive loop filtering (ALF) process. The method also includes performing a conversion between the block and a bitstream representation of the video by selectively applying the ALF process according to the classification.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: July 19, 2022
    Assignees: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD., BYTEDANCE INC.
    Inventors: Li Zhang, Kai Zhang, Hongbin Liu, Yue Wang
  • Patent number: 11356098
    Abstract: A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: June 7, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Byongmo Moon, Jiyoung Kim, Seongook Jung, Jongsoo Lee
  • Patent number: 10432436
    Abstract: A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Krishnan S. Rengarajan, Vaibhav A. Ruparelia
  • Patent number: 9264187
    Abstract: In one embodiment, a receiver includes: a data path having a first slicer to receive and sample an incoming analog signal and to determine a bit level for the incoming analog signal, the first slicer to provide a bit decision to a consuming logic; an analysis path having a second slicer to receive and sample the incoming analog signal and to determine a second bit level for the incoming analog signal; and a controller coupled to receive an output of the first slicer and an output of the second slicer to determine a bit error rate for the data path based on the first and second slicer outputs. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: February 16, 2016
    Inventors: Gaudencio Hernandez Sosa, Varvara Kollia
  • Publication number: 20140355663
    Abstract: A programmable feed forward equalizer (FFE) includes a plurality of unit cells, each unit cell comprising a capacitive element coupled to an input connection by a first switch and coupled to an output connection by a second switch. The FFE also comprises clock logic configured to control the first switch and the second switch so that a selected voltage signal is applied to the capacitive element at a selected time such that the selected voltage signal defines a capacitance of the capacitive element, the clock logic causing the second switch to couple the capacitive element to the output connection so as to apply the selected voltage signal as a filter coefficient to a summing element.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Inventors: Jade Michael Kizer, Robert B. Roze
  • Patent number: 8879615
    Abstract: An equalization adaptation circuit comprises an equalizer, a transition determination circuit, a phase error circuit, a sequence recovery circuit, a phase error accumulator circuit, a transition accumulator circuit, and a controller circuit. The equalizer has adjustable parameters. The transition determination circuit determines observed transitions in an equalized signal output from the equalizer. A phase error circuit determines phase errors of the observed transitions. A sequence recovery circuit generates recovered digital data sequences. A phase error accumulator circuit accumulates the phase errors in respective association with pre-defined patterns matching the recovered digital data sequences containing observed transitions corresponding to the phase errors. A transition accumulator circuit accumulates a number of the observed transitions. A controller circuit controls the adjustable parameters of the equalizer based upon the accumulated phase errors and number of observed transitions.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 4, 2014
    Assignee: PMC-Sierra US, Inc.
    Inventor: Mathieu Gagnon
  • Patent number: 8837573
    Abstract: A method for compensating for gain changes of an N-level pulse amplitude modulation (PAM-N) modulated signal. The method comprises comparing the PAM-N modulated signal to N?1 configurable thresholds, wherein the input PAM-N modulated signal is also equalized and the N?1 configurable thresholds are N?1 different voltage levels; tracking gain changes in the input PAM-N modulated signal by comparing the input PAM-N modulated signal to a compensation threshold; and adjusting a level of the at least one of the N?1 configurable thresholds of the N?1 comparators based on an output of the compensation comparator, thereby offsetting a crossing point of the at least one comparator respective of the at least one of the N?1 configurable thresholds to compensate for gain changes in the input PAM-N modulated signal.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 16, 2014
    Assignee: Transwitch Corporation
    Inventors: Eran Doron, Baruch Meborach Bublil, Yaron Slezak, Idan Versano
  • Patent number: 8705606
    Abstract: An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 22, 2014
    Assignee: Rambus Inc.
    Inventor: Ramin Farjad-Rad
  • Patent number: 8675777
    Abstract: A center frequency of an adjustable filter is controlled to achieve a compromise between DC offset rejection and image rejection.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: March 18, 2014
    Assignee: Broadcom Corporation
    Inventor: Meng-An Pan
  • Patent number: 8619578
    Abstract: Presently described is a system and method for switching multimedia data communications, including but not limited to Voice over IP (VoIP) telephony, cable TV, digital audio and video. The system utilizes a single, integrated device to provide all PacketCable-compliant functionality, including enhanced user privacy, compliance with CALEA, E911 and other mandated services not available in conventional distributed PacketCable systems. High speed and efficient, low cost operation are provided by means of an optimized data unit encapsulation scheme for internal switching and routing. A proprietary fiber optic backplane and removable optical connectors are used to enable lightspeed internal communications hot-swapping of components. Furthermore, the present system is extensible to all forms of digital data switching and is secure, resistant to Denial of Service attacks, and fault-resilient.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: December 31, 2013
    Assignee: Genband US, LLC
    Inventors: Geoffrey Devine, Patrick Quigley, Jeffrey J. Fitzgerald, Daniel W. English, John Doucette, Paul Miller, Jr.
  • Patent number: 8559495
    Abstract: This invention relates to methods and apparatus for equalizer adaptation for compensating for channel distortion on received data signals. The method comprises, for each bit, forming an adjusted bit signal comprising a weighted contribution from at least one other bit period. The polarity of the adjusted bit signal is determined and the bit is categorized as a hard, i.e. high confidence, bit is the bit is above an upper threshold or below a lower threshold or otherwise is categorized as a soft bit. The weightings are adjusted based on the category of the bit wherein a first adjustment is made it the bit is categorized as a soft bit but a second, different adjustment is made if the bit is categorized as a hard bit. For a soft bit the weightings may be increased for bits which have the same polarity as the bit in question and decreased for bits of opposite polarity.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: October 15, 2013
    Assignee: Phyworks Limited
    Inventors: Chris Born, Miguel Marquina, Ben Willcocks, Andrew Sharratt, Allard Van Der Horst
  • Patent number: 8472563
    Abstract: A signal processing apparatus includes a first baseline wander correcting unit, provided in a processing path in which a predetermined processing is performed on an input signal, which corrects baseline wander by a feedforward and a second baseline wander correcting unit, provided anterior to the first baseline wander unit, which corrects the baseline wander by a feedback control. The first baseline wander correcting unit derives an amount of baseline wander. Further, it calculates a value corresponding to an average value of the amount of derived baseline wander and fine-adjusts a correction amount of baseline. Then it corrects the baseline wander by using the fine-adjusted baseline amount. The second baseline wander correcting unit calculates a value corresponding to an average value of the amount of baseline wander derived by the baseline wander derivation unit and coarse-adjusts a correction amount of baseline, and corrects the baseline wander by using the coarse-adjusted baseline amount.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: June 25, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Atsushi Esumi, Kai Li, Hidemichi Mizuno
  • Patent number: 8472083
    Abstract: To provide an intra prediction apparatus which can circumvent a hazard problem and improve the time reduction effect. An intra prediction apparatus 11 performs intra predictions of a picture. The intra predictions include: second intra predictions of respective second blocks (blocks) which are obtained by dividing a first pixel block; and a first intra prediction of the first block (macroblock) which constitutes the picture. The intra prediction apparatus 11 includes: an intra prediction unit (a prediction unit 113, an orthogonal transform and quantization unit 115, an inverse orthogonal transform and inverse quantization unit 116, and an adder 117) which performs the intra predictions; and a control unit 119 which controls the intra prediction unit to perform in parallel the intra prediction of the macroblock and the intra predictions of the respective pixel blocks.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Arakawa, Koji Arimura, Tatsuro Juri, Takashi Masuno, Kei Tasaka
  • Publication number: 20130156088
    Abstract: An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Huawen Jin, Jawaid Ahmad, Yaqi Hu
  • Patent number: 8325856
    Abstract: An acquisition module includes a coherent correlator configured to receive a transmission having a pilot signal and correlate the received transmission with a local copy of the pilot signal to produce a first output, a delayed correlator configured to delay the first output and correlate the first output with the delayed first output to produce a second output, and a detector configured to detect the pilot signal in the transmission based on the second output.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: December 4, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Raghuraman Krishnamoorthi, Tao Tian, Fuyun Ling, Yuheng Huang
  • Patent number: 8116366
    Abstract: Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: February 14, 2012
    Assignees: Renesas Electronics Corporation, The Board of Trustees of the Leland Stanford Junior University
    Inventors: Toshitsugu Kawashima, Mark Horowitz
  • Publication number: 20110299585
    Abstract: To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 8, 2011
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Yasumoto TOMITA, Hisakatsu Yamaguchi, Satoshi Kawahara
  • Patent number: 8059707
    Abstract: A decoding unit for decoding a modulated signal includes a summing unit having i) a first input, ii) a second input, and iii) an output. The summing unit is configured to i) receive the modulated signal at the first input, ii) receive a feedback signal at the second input, and iii) output a first waveform based on the modulated signal and the feedback signal. A demodulation unit has a first demodulation pathway and a second demodulation pathway. The demodulation unit is configured to i) select between the first demodulation pathway and the second demodulation pathway, ii) receive and demodulate the modulated signal with the first demodulation pathway, and iii) receive and demodulate the first waveform with the second demodulation pathway. The remodulation unit is configured to selectively i) output a first complex waveform based on the modulated signal, and ii) output a subsymbol waveform of the first waveform.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: November 15, 2011
    Assignee: Marvell International Ltd.
    Inventors: Yungping Hsu, Nelson Xu, Ricky Cheung
  • Patent number: 8050368
    Abstract: A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the immunity of phase-modulated signals (PSK) to intersymbol interference (ISI) such as caused by transmitter or receiver impairments, frequency selective channel response filtering, timing offset or carrier frequency offset. The invention uses phase domain signals (r, ?) rather than the classical Cartesian quadrature components (I, Q) and employs a nonlinear adaptive equalizer on the phase domain signal. This results in significantly improved ISI performance which simplifies the design of a digital receiver.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: November 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Lerner, Yossi Tsfati
  • Patent number: 8014444
    Abstract: An algorithm is provided that computes values for correcting for DC offsets of baseband I and Q signals, compensates for amplitude imbalance between the baseband I and Q signals and compensates for phase imbalance between the baseband I and Q signals. Test signals are injected into the I and Q signal processing paths (either or both of the receiver path and baseband path in a modem). Samples of the I and Q signals produced in the I and Q signal processing paths are generated and analyzed to determine DC offsets of the I and Q signals, amplitude imbalance between the I and Q signals and phase imbalance with respect to a desired orthogonal relationship between the I and Q signals.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: September 6, 2011
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventor: Anthony G. Marino
  • Patent number: 7876866
    Abstract: A method and apparatus are provided for reducing, and preferably substantially eliminating, data-pattern autocorrelations found in digital communication systems. The method employed is referred to as Data Subset Selection (DSS) and is implemented in the form of DSS engine. Autocorrelations in the data-pattern can cause many digital adaptive systems to converge to an incorrect solution. For example, the LMS method, which is often used in adaptive filtering applications, can converge to an incorrect set of filter coefficients in the presence of data-pattern autocorrelations. Digital timing recovery methods are also susceptible. Other impairments that result from data-pattern autocorrelations include increased convergence time and increased steady-state chatter.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: January 25, 2011
    Assignee: PMC-Sierra US, Inc.
    Inventors: Matthew W. McAdam, Jurgen Hissen, Graeme Boyd
  • Patent number: 7835434
    Abstract: The invention relates to an adaptive Radio Frequency (RF) filter (11), which is particularly useful as an RF filter in Wireless Local Area Networks (WLAN's). As greater demands are placed on RF systems, for example in WLAN's in order to increase channel capacity by utilizing available bandwidth, corresponding demands are placed upon performance and tolerance of components used in FR circuits.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thien Luong Huynh, Anil Gercekci, Anthony David Newton
  • Patent number: 7817767
    Abstract: A processor-controlled clock-data recovery (CDR) system. Phase error signals having either a first state or a second state are generated within the CDR system according to whether a first clock signal leads or lags transitions of a data signal. A difference value is generated based on the phase error signals, the difference value indicating a difference between the number of the phase error signals having the first state and a number of the phase error signals having the second state. The difference value is transferred to a processor which is programmed to determine whether the difference value exceeds a first threshold and, if so, to adjust the phase of the first clock signal.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: October 19, 2010
    Assignee: Rambus Inc.
    Inventors: Stephen G. Tell, Thomas H. Greer, III
  • Patent number: 7746925
    Abstract: A feedback equalizer includes a summing unit having an output and first input for receiving a modulated signal, which includes a symbol defined by a first number of chips. A subsymbol processor is coupled to the output of the summing unit. The symbol processor is capable of generating a subsymbol waveform upon receipt of a second number of chips of the symbol. The second number is less than the first number. A feedback filter is coupled to a second input of the summing unit and the symbol processing unit to selectively filter the subsymbol waveform from the modulated signal.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: June 29, 2010
    Assignee: Marvell International Ltd.
    Inventors: Yungping Hsu, Nelson Xu, Ricky Cheung
  • Patent number: 7746924
    Abstract: For a given channel and a filter having at least one filter tap, a set of at least one weight value is determined for the at least one filter tap according to which at least one weight value substantially minimizes a gradient of a frequency response for the given channel and substantially maximizes energy of the frequency response for the given channel within a predetermined bandwidth.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: June 29, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Karl Joseph Bois, Dacheng Zhou, Shad R. Shepston, David W. Quint
  • Patent number: 7738546
    Abstract: A method and apparatus for a feed forward equalizer for a communication system are described. An equalizer comprising a tapped filter having multiple filter multipliers and a summing element is described. The equalizer further comprises a correlator having multiple correlator multipliers, with each correlator multiplier having a corresponding integrator, a set of shared delay elements to connect to the filter multipliers and the correlator multipliers; and an error signal generator to connect to the correlator.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventor: Benny Christensen
  • Patent number: 7711042
    Abstract: A second-order Volterra filter has a quadratic section including a plurality of multiplication units that multiply a first input signal with a second input signal. One of the multiplication units employs a signal not delayed from the first input signal, as the second input signal. A remaining one of the multiplication units employs a signal delayed a preset time from the first input signal, as the second input signal. The one of the multiplication units includes a multiplier that multiplies the signal output from the one of the multiplication units and a signal output from each of one or more delay units, each with a preset coefficient. A step gain parameter for updating each preset coefficient of a multiplier of the remaining one of the multiplication units is twice a step gain parameter for updating each preset coefficient of the multiplier of the one of the multiplication units.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: May 4, 2010
    Assignee: Sony Corporation
    Inventor: Yoshiyuki Kajiwara
  • Patent number: 7706436
    Abstract: Exemplary embodiments of the present invention provide an equalizer combined with a decoder and a method of updating filter coefficients. The method may include calculating output error signals ek, multiplying the output error signals by a parameter, obtaining a partial value by multiplying a delayed decoder decision stored in a filter delay line corresponding to an i-th filter coefficient by the result obtaining a partial value by multiplying a constant by a feedback coefficient and obtaining an updated value by adding the two partial values.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: April 27, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sergey Zhidkov
  • Patent number: 7627029
    Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: December 1, 2009
    Assignee: Rambus Inc.
    Inventors: Andrew Ho, Vladimir Stojanovic, Bruno W. Garlepp, Fred F. Chen
  • Patent number: 7613238
    Abstract: An adaptive equalizer comprises: a forward equalizer (FE) receiving a symbol stream to generate an FE output; a decision feedback equalizer (DFE) receiving a decision symbol stream to generate a DFE output; a first adder, coupled to the forward equalizer and the decision feedback equalizer, adding the FE and DFE outputs to generate an equalizer output; a first trellis decoder, coupled to the first adder, receiving the equalizer output to generate a trellis decoded stream by a trellis decoding process; and a compensator for compensating the equalizer output according to the decision symbol stream, the trellis decoded stream, and a coefficient vector stored in the decision feedback equalizer, to generate a compensated equalizer output.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: November 3, 2009
    Assignee: Mediatek Inc.
    Inventor: Chiao-Chih Chang
  • Patent number: 7596175
    Abstract: Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: September 29, 2009
    Assignee: Rambus Inc.
    Inventor: Fred F. Chen
  • Patent number: 7593483
    Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: September 22, 2009
    Assignee: Broadcom Corporation
    Inventors: Todd L. Brooks, Kevin L. Miller, Josephus A. Van Engelen
  • Patent number: 7590175
    Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: September 15, 2009
    Assignee: Rambus Inc.
    Inventors: Brian S. Leibowitz, Bruno W. Garlepp
  • Patent number: 7567642
    Abstract: A method and apparatus for extending the linear range of a phase detector. In one embodiment, a limited range phase difference is generated between selected edges of first and second input signals, and an excursion of the limited range phase difference beyond a predetermined threshold is detected. In response to detecting the excursion of the limited range phase difference beyond a threshold, an edge of the first or second input signal is prevented from influencing subsequent generation of the limited range phase difference, and a compensated phase difference is generated, derived from the limited range phase difference and including a correction component which compensates for the effect of preventing said edge from influencing subsequent generation of the limited range phase difference.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: July 28, 2009
    Assignee: Analog Devices, Inc.
    Inventor: Peter John White
  • Patent number: 7542508
    Abstract: A continuous-time domain Decision Feedback Equalizer (DFE) for use in a serial communication channel comprises in one embodiment a summer, a decision circuit, a capture flip-flop (FF) and an N-th order active filter. The DFE and its active filter operate in continuous time to give improved performance over a discrete-time DFE. In one embodiment involving a first-order active filter, the capture FF is outside the continuous-time negative feedback loop of the DFE and involves a differential signal amplifier. In another embodiment, the capture flip-flop is inside the DFE loop, and in a third embodiment the decision circuit comprises a comparator.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: June 2, 2009
    Assignee: LSI Logic Corporation
    Inventors: Mark J Marlett, Mark Rutherford
  • Patent number: 7526021
    Abstract: In a multi-carrier system employing OFDM, for example DMT, an adaptive channel equalizer is normally used, operating in the frequency domain. The sampling clock is controlled so that the time delay between the transmitter and the receiver is effectively eliminated. If the information used to control the sampling clock is received from the equalized data stream, it will introduce an ambiguity between the operation of the channel equalizer and the mechanism used to control the sampling clock. Operation of the equalizer can mask an increasing time difference, between transmitter and receiver, which the sample clock controller should be tracking. The present invention eliminates the ambiguities in the operation of the equalizer and sample clock controller by preventing the equalizer accepting time differences which should be corrected by operation of the sample clock controller.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: April 28, 2009
    Assignee: STMicroelectronics S.A.
    Inventors: Magnus Johansson, Lennart Olsson, Gunnar Bahlenberg, Daniel Bengtsson, Mikael R. Isakssaon, Sven-Rune Olofsson, Sven Göeran Öekvist
  • Patent number: 7526019
    Abstract: A system for providing multi-channel multi-mode QAM equalization and carrier recovery is provided. According to one exemplary embodiment, the system includes an equalization circuit and a carrier recovery circuit operating in a concurrent manner to provide equalization and carrier recovery. The equalization circuit and the carrier recovery circuit each have two operating modes, namely, an acquisition mode and a tracking mode. The carrier recovery circuit evaluates a phase detection error calculated based on signals obtained from the equalization circuit. Based on the evaluation of the phase detection error, the equalization circuit and the carrier recovery circuit are respectively directed to switch operating mode, if appropriate.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: April 28, 2009
    Assignee: Broadlogic Network Technologies Inc.
    Inventors: Vladimir Radionov, Bin-Fan Liu, Yu Kou
  • Patent number: 7508870
    Abstract: A sequence of unfiltered channel estimation values xk is determined in a method for calculation of filtered channel estimation values dk in radio systems. A specific set of filter coefficients is selected from two or more filter coefficient sets, with the filter coefficients being calculated on the basis of the MMSE optimality criterion for a predetermined recursive digital filter (F). The sequence of unfiltered channel estimation values is then filtered by means of this recursive digital filter (F) using the selected filter coefficients.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: March 24, 2009
    Assignee: Infineon Technologies AG
    Inventor: Robert Denk
  • Patent number: 7505536
    Abstract: An energy dispersal circuit, which generates a PRBS (Pseudo Random Binary Sequence) and executes an XOR (exclusive-OR) operation with respect to a data signal and the PRBS based on a bit, includes a register value calculator for calculating a register value of a shift register based on inputted data and a packet number. The register value calculator has a bit divider for dividing the packet number from LSB to MSB, packet shift operators for bit-shifting an initial value of the shift register from 20 bits to 2N?1 bits, and selectors for selecting inputs and outputs thereof.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: March 17, 2009
    Assignee: Panasonic Corporation
    Inventors: Tetsuya Yagi, Tomohiro Kimura
  • Patent number: 7502411
    Abstract: In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: March 10, 2009
    Assignee: Silicon Image, Inc.
    Inventors: Ook Kim, Gyudong Kim
  • Patent number: 7463682
    Abstract: This invention presents a coding method for binary digits coding and its circuit for digits transmission. With this coding method, the binary digits are corresponding to a sequence of pulse groups. The binary digits “0” and “1” are corresponding to the two pulse groups with same defined number of pulses and with two special defined pulse frequencies respectively. The two pulse groups have the same defined number of pulses. The number is at least 2. The corresponding decoding method divides the sequence of pulse groups, according to the same defined number, into a set of pulse groups. The duration time of each pulse group is measured. The binary digits “0” and “1” are corresponding to the differences of the duration time of the pulse groups.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: December 9, 2008
    Assignee: Institute of Process Engineering, Chinese Academy of Sciences
    Inventors: Zhangyuan Yang, Li Guo, Yanhua Wang
  • Patent number: 7453932
    Abstract: A testing apparatus for testing a device under test is provided, wherein the testing apparatus includes: a comparator for receiving a signal output from the device under test and converting the signal into a logic signal by comparing the signal with a first reference voltage; a driver for amplifying a logic signal to be output to the device under test on the basis of a second reference voltage and outputting to the device under test; a comparator setting unit for determining the first reference voltage so as to compensate for a delay amount of a reception signal received from the device under test and setting the comparator to be the first reference voltage; and a driver setting unit for determining the second reference voltage on the basis of the reference voltage of the comparator and setting the driver to be the second reference voltage.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: November 18, 2008
    Assignee: Advantest Corporation
    Inventors: Toshiaki Awaji, Takashi Sekino
  • Patent number: 7443909
    Abstract: Receiving downlink CDMA signals in a fast-fading environment is facilitated at higher receiver velocities by updating the block-adaptive linear minimum mean square error (LMMSE) downlink CDMA equalizer. The autocorrelation matrix of the observed data is updated by passing block-wise autocorrelation slides through a filter. Each autocorrelation slide is an autocorrelation matrix estimated from a short block of observed data over which the channel can be considered constant. This method achieves a reliable estimate for the autocorrelation matrix when the block size must be small to ensure that the block-wise stationarity assumption holds in cases of fast fading channels. In addition, small block sizes make it possible to satisfy the equalizer delay constraint imposed by hardware and certain voice transmission standards such as CDMA2000 1X where demodulated data must be delivered within only several symbol periods of the signal arrival time.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: October 28, 2008
    Assignee: Nokia Corporation
    Inventors: Hoang Nguyen, Jianzhong Zhang, Yuanbin Guo, Dennis McCain, Joe Dowling
  • Patent number: 7433418
    Abstract: Some embodiments store a training sequence in a communications system. The stored training sequence exhibits certain desirable characteristics when used by a peak to average power constrained modulation format. In one embodiment, a set of original ordered sequences is selected to have at least one desired property. A set of extended sequences is created from the original sequences by beginning with an element of an original sequence and cyclically appending elements of the original sequence in order to obtain a desired extended sequence length. Each extended sequence is modified using a corresponding modifying sequence, such that a training sequence can be generated from any one of the modified extended sequences. Each modifying sequence is selected so that the generated training sequence when modulated by a selected modulation format has the at least one desired property of the corresponding original ordered sequence.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: October 7, 2008
    Assignee: ArrayComm, LLC
    Inventors: Mithat C. Dogan, Mitchell D. Trott
  • Patent number: 7386240
    Abstract: In one aspect a system and method for providing a multi-port memory having a plurality of read ports, each read port including a filter coefficient value representing a dispersion compensation value associated with an optical link. The method includes processing an input optical signal using the filter coefficient values in the multi-port memory to generate an output optical signal for transmission on the optical link.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: June 10, 2008
    Assignee: Nortel Networks Limited
    Inventors: Sandy Thomson, Ruibin Jin, Eric Hall, Paul MacDonald
  • Patent number: 7340657
    Abstract: In an embodiment, a method includes forming a plurality of time/voltage points from a number of voltage values and from a number of time values, generating serialized data having a predetermined number of bits, comparing the serialized data to a set predetermined voltage to produce analysis data, and capturing the analysis data at a respective time data point of a plurality of time data points. The method may be implemented as part of integrated circuits, electronic assemblies, or systems.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: March 4, 2008
    Assignee: Intel Corporation
    Inventors: Jared W. Crop, David J. O'dell, Mike D. Wang
  • Patent number: RE47356
    Abstract: A communication apparatus includes a reference signal generating section, a transmitting section, a propagation estimating section, a first data acquiring section, and a decoding section. The reference signal generating section generates a first reference signal to enable a communicating party to estimate a propagation environment. The transmitting section transmits the first reference signal. The propagation estimating section estimates a first propagation estimation value of the propagation environment using a second reference signal transmitted from the communicating party. The first data acquiring section generates first data using the first propagation estimation value. The decoding section decodes a transmission signal encoded using a second propagation estimation value that is estimated by the communicating party using the first reference signal, to obtain second data using the first data.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 16, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Masayuki Orihashi, Yutaka Murakami, Katsuaki Abe, Akihiko Matsuoka
  • Patent number: RE49244
    Abstract: A communication apparatus includes a reference signal generating section, a transmitting section, a propagation estimating section, a first data acquiring section, and a decoding section. The reference signal generating section generates a first reference signal to enable a communicating party to estimate a propagation environment. The transmitting section transmits the first reference signal. The propagation estimating section estimates a first propagation estimation value of the propagation environment using a second reference signal transmitted from the communicating party. The first data acquiring section generates first data using the first propagation estimation value. The decoding section decodes a transmission signal encoded using a second propagation estimation value that is estimated by the communicating party using the first reference signal, to obtain second data using the first data.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: October 11, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Masayuki Orihashi, Yutaka Murakami, Katsuaki Abe, Akihiko Matsuoka