Abstract: Embodiments provide a terminal point of a communication system, wherein a control signal is emitted in the communication system for coordinating the participants of the communication system, wherein the control signal is transferred distributed in correspondence with a frequency hop-based occupancy of resources of the frequency band, indicated by a control signal hopping pattern, wherein the terminal point has a receiver, wherein a receive bandwidth of the receiver is smaller at least by the factor 3 than a bandwidth of the frequency hop-based occupancy of resources of the frequency band, indicated by the control signal hopping pattern, wherein the terminal point is configured to receive a reference signal, the reference signal having information on the control signal, wherein the terminal point is configured to receive the control signal based on the information on the control signal.

Abstract: An electrical system may include a processing circuit and one or more electrical components that emit thermal heat energy. The processing circuit may be configured to identify signal degradation or failure of an in-band communication channel between the electrical system and a second electrical system, identify a data message to transmit to the additional electrical system via an out-of-band communication channel, and direct the one or more electrical components to adjust an electrical workload to modulate and transmit the data message on the out-of-band communication channel as a recoverable sequence of thermal pulses.

Abstract: A transmission system for converting a signal of a 9-channel encoder into a 1000 Mbps PHY signal, includes a PHY chip circuits U1 and U2, digital photocouplers U3˜U11, 485 transceivers U12˜U20, RJ45 isolation transformer-integrated jacks J1 and J2, a field programmable gate array (FPGA) chip circuit, an electronic propulsion control system (EPCS) configuration chip circuit, a Jtag interface and SM-6P-PCB jackets J3˜J11, wherein two-channel MII digital signal output and input ends of the FPGA chip circuit are respectively connected with MII digital signal input and output ends of the PHY chip circuits U1 and U2; differential data signal output and input ends of the PHY chip circuits U1 and U2 are respectively connected to the RJ45 isolation transformer-integrated jacks J1 and J2, and a master station and a slave station are arranged at the same time.

Abstract: The exemplary embodiments of the present disclosure relate to a phase adjustment apparatus, and its operation method, provided with a phase detector, phase controller and phase calibrator for reducing complexity of a circuit and enabling execution of a phase adjustment operation in the background.

Abstract: A voltage sampling system is provided. The voltage sampling system includes a voltage sampling device, two optic-fiber transmission lines and a control device. The voltage sampling device includes a voltage-dividing resistor module, a common mode rejection circuit and an analog-to-digital converter. The voltage-dividing resistor module generates a first and a second divided voltages according to a voltage source. The common mode rejection circuit receives the first and the second divided voltages to perform a common-mode noise rejecting process to generate an output voltage. The analog-to-digital converter converts the output voltage to generate a digital data signal. The two optic-fiber transmission lines transmit the digital data signal and a clock signal respectively. The control device receives the digital data signal from the analog-to-digital converter and the clock signal to perform a digital data processing.

Abstract: A data communication method in a single-wire protocol communication is provided. The method includes determining a number of first data bits having a logical high state or a number of second data bits having a logical low state from among data bits in a communication packet, determining whether the number of the first data bits exceeds a first predetermined number or the number of the second data bits is below a second predetermined number, inverting the data bits in the communication packet when the number of the first data bits exceeds the first predetermined number or the number of the second data bits is below the second determined number, and transferring the inverted data bits to a reception side via a single-wire input/output.

Abstract: Optical range finders are configured to transmit optical bursts toward a target and detect a corresponding received burst. DC offset in the received burst due to square law detection can be offset based on a difference between high pass and low pass filtered portions of the received burst. Edge records associated with bursts can be obtained, and correlated with a reference signal or waveform to obtain a range estimate.

Abstract: A method of converting an input clock to generate an output clock and providing a certain system with the output clock is provided. The method includes setting up a desired output clock value and a variable value and determining whether the input clock is the rising edge; adding the output clock value to the variable value to provide a calculated value when the input clock is the rising edge; comparing the calculated value with the input clock value; and outputting, when the calculated value is equal to or larger than the input clock value as a result of comparison, the output clock as logic state ‘1’ and setting, a value obtained by subtracting the input clock value from the calculated value, as the variable value.

Abstract: A communication device including circuitry configured to receive a signal transmitted to the communication device via a communication channel. A receiver is configured to generate a filter coefficient to be used for filtering the received signal, generate a gain coefficient, wherein the gain coefficient corresponds to a condition of the communication channel, adjust the filter coefficient using the gain coefficient, and filter the received signal using the filter coefficient, as adjusted using the gain coefficient, to remove intersymbol interference from the received signal.

Abstract: A system for communicating data comprises a clock channel configured to transmit a clock signal at a predetermined rate and at least one data channel configured to transmit data as a sequence of blocks of multi-level symbols being sent at a fixed multiple of the clock rate. Each block of multi-level symbols comprises a sequence of at least three multi-level symbols. Each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, the predetermined number being an integer greater than two. The fixed multiple of the clock rate is an integer greater than one.

Abstract: Circuits and techniques for operating an integrated circuit (IC) are disclosed. A disclosed circuit includes a divider circuit that is operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal. A recovery circuit is coupled to the divider circuit. The recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal. A phase aligner circuit, operable to align a phase of the second signal with a phase of the recovered clocks signal based on the first ready signal, is coupled to the recovery circuit.

Abstract: There is provided a video processing device capable of reducing the influence of a disturbance of an input vertical synchronization signal. When the synchronization signal detecting unit detects an input of the input-side vertical synchronization signal at a predetermined cycle, the synchronization signal control unit outputs the input-side vertical synchronization signal, which has been input, as an output-side vertical synchronization signal, and, when the synchronization signal detecting unit detects an input of a next input-side vertical synchronization signal before the predetermined cycle elapses after the output of the output-side vertical synchronization signal, a next input-side vertical synchronization signal input before the predetermined cycle elapses is not output as a next output-side vertical synchronization signal, and an input-side vertical synchronization signal input further next is output as the next output-side vertical synchronization signal.

Abstract: Provided is a signal processing apparatus including an encoder for encoding, according to respective specific coding schemes, a first bit string formed from bit values at odd-numbered positions and a second bit string formed from bit values at even-numbered positions that are obtained by alternately extracting bit values from a bit string that is expressed by mutually different first and second bit values, and generating first and second encoded signals that do not include a DC component, and a signal generation unit for generating a multilevel signal by respectively adding, to a clock signal having larger amplitude than the first and second encoded signals that are generated by the encoder, the first encoded signal in synchronization with a timing of the clock signal being at a positive amplitude value and the second encoded signal in synchronization with a timing of the clock signal being at a negative amplitude value.

Abstract: A timing detection device includes a draw back amount acquiring unit and a detecting unit. The draw back amount acquiring unit is configured to acquire a draw back amount of a received signal with respect to a peak value of the signal. The detecting unit is configured to detect the timing at which the draw back amount acquired by the draw back amount acquiring unit has exceeded a constant value as the timing at which a value of the signal is switched.

Abstract: Certain aspects of a method and system for a delay locked loop for a rake receiver are disclosed. Aspects of one method may include normalizing a signal power of a first control channel based on a threshold value. A sampling time associated with at least one or more of the following: the first control channel, a second control channel, an on-time control channel, and a data channel, may be adjusted based on a comparison between the normalized signal power of the first control channel and a signal power of the second control channel. The second control channel may be delayed with respect to the first control channel by a particular time period. The first and second control channels may be common pilot control channels (CPICHs). The combined signal power of the first control channel may be normalized based on said threshold value.

Abstract: According to an aspect of an embodiment, a communication system includes a transmission apparatus with a coding section that generates multi-level-coded signals and transmits the multi-level-coded signals; and a deskew signal generation section that generates and transmits a deskew signal related to the multi-level-coded signals. The communication system also includes a receiving apparatus with a decoding section that decodes the multi-level-coded signals to generate decoded signals, and a deskew processing section that performs deskew processing for compensating skew among the decoded signals of the multiple channels. The deskew signal generation section generates the deskew signal that has been framed by extracting a part of the data from each of the channels of the input signals, adding framing data for enabling a receiving apparatus to recognize which channel the extracted data has been extracted from, and performing rate conversion.

Abstract: A method of communicating on a single serial line between two devices is disclosed. The method includes combining a data stream and a clock to form a three-voltage level stream such that the third voltage level records the transitions of the clock while the serial data is either high or low. Either the first or the second device can send a combined stream on the line. The method further includes, in some embodiments, the second device driving the same voltage levels as those transmitted by the first device and the first device sensing current on the single serial line to determine that the second device has received data from the first device.

Abstract: A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by—multiple clocks with different phases such that the signals of the differential channel may be separately or individually time adjusted to account for skew between them so that they may be differentially compared for data resolution. In one embodiment, a positive sampler and negative sampler are controlled by distinct clock signals to permit, at different times, sampling and holding of the positive and negative signals representing a data bit on the differential channel. A differential decision circuit may then differentially resolve the data using a latter one of the distinct clock signals. Timing generation circuitry for producing the offset clocks may include a skew detector that permits dynamic adjustment of the different clock signals according to skew associated with the signals of the differential channel.

Abstract: The invention relates to a system for transmitting data from a medium access control device (2) via a digital interface (IF1) to a physical layer (PHY) and to an antenna (5), the physical layer (PHY) comprising a base band (4) with a base band controller (7) and a data processing pipeline (3) comprising a plurality of functional blocks (FB1 to FB 13), wherein a burst timing control block of one of all functional blocks (FB1 to FB 13) of the data processing pipeline (3) detects an end of a packet of payload data and, thereupon, sets a halt signal (STALL) for those functional blocks (FB1 to FB 13) preceding the burst timing control block (FB1 to FB 13) in the data processing pipeline (3) and starts a timer (T1) for counting a duration of a minimum inter-frame space (MIFS), wherein the burst timing control block (FB1 to FB 13) resets the halt signal (STALL) after expiration of the timer (T1). It also relates to a corresponding method.

Abstract: The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

Abstract: A radio channel estimation result which is an estimation result of a state of a propagation path to a mobile terminal that is a communication target, is generated. Whether a correction operation for correcting a frequency drift of a radio frequency used in radio communication between a radio base station and the mobile terminal has converged or not is determined. Then, a moving speed of the mobile terminal is estimated using only the radio channel estimation result at the time when the correction operation has converged.

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop utilizes a frequency error estimator implemented as a maximum-likelihood estimator with slope fitting based on a sequence of arrival timestamps, and a loop filter implemented as a series combination of an adaptive-bandwidth filter and a proportional-integral controller.

Abstract: Synchronization of satellite and terrestrial broadcasts in a shared frequency arrangement is use in order to facilitate simultaneous reception of the broadcasts. A delay value is adjusted based on a synchronization between a first terrestrial broadcast and a satellite broadcast, and a delay value for a second terrestrial broadcast is adjusted based on a synchronization between the second terrestrial broadcast, the first terrestrial broadcast and the satellite broadcast. The adjustment of the relative delay values provides an improved reception pattern based on receipt of a shared frequency communication from multiple sources by improving a signal quality factor within at least selected regions of the coverage areas in which the relative delay values permit synchronization.

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop comprises a primary loop having a first frequency error estimator for generating a first estimate of error between the master and slave clock frequencies, a second frequency error estimator outside of the primary loop for generating a second estimate of error between the master and slave clock frequencies, and an accumulator coupled between the second frequency error estimator and the primary loop. The second estimate is controllably injected into the primary loop via the accumulator.

Abstract: According to an aspect of an embodiment, a communication system includes a transmission apparatus with a coding section that generates multi-level-coded signals and transmits the multi-level-coded signals; and a deskew signal generation section that generates and transmits a deskew signal related to the multi-level-coded signals. The communication system also includes a receiving apparatus with a decoding section that decodes the multi-level-coded signals to generate decoded signals, and a deskew processing section that performs deskew processing for compensating skew among the decoded signals of the multiple channels. The deskew signal generation section generates the deskew signal that has been framed by extracting a part of the data from each of the channels of the input signals, adding framing data for enabling a receiving apparatus to recognize which channel the extracted data has been extracted from, and performing rate conversion.

Abstract: The disclosed embodiments provide methods and systems for synchronizing a transmitter and a receiver. In one embodiment, a method for synchronizing a transmitter and a receiver includes the transmitter performing a reset operation, and the receiver responding by performing a reset operation. In another embodiment, a method for synchronizing a transmitter and a receiver includes the receiver performing a reset operation, and the transmitter responding by performing a reset operation. The reset indicator includes toggling a reset indicator.

Abstract: Systems and techniques are disclosed wherein a gated pilot signal can be re-acquired faster by searching a last known pilot offset and/or searching a last coset in which the last pilot signal was found.

Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.

Abstract: In a provided information processing device, a first information processing module, within its transmission time segment, transmits an encoded signal in which mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the same amplitude value not occurring consecutively and the amplitude value polarity being inverted with each cycle. Within a transmission time segment for a second information processing module, the first information processing module transmits a clock signal that corresponds to the cycle at which the polarity is inverted.

Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed.

Abstract: A pulse signal reception device of a comparatively simple configuration detects a signal sampled at an optimal clock timing for a pulse modulation signal having a signal width shorter than a symbol frequency. In this device, a time division unit (103) samples a data signal at a clock signal rise edge and outputs the sampled data signals to counters (104-1 to 104-3), respectively. The counters (104-1 to 104-3) count the number of High levels when the data signal becomes High level within a predetermined period, and a maximum value detection unit (105) outputs maximum data string information on a data string counted by a counter in which the maximum number of High levels has been detected among the counters (104-1 to 104-3) to a selection data judgment unit (106). The selection data judgment unit (106) judges which data string sampled at a particular timing is to be selected as a demodulation data string.

Abstract: A multi-level signal uses the third/fourth signal level to signal both a word clock edge and a data word boundary. At the receiver, a level detector detects a transition to or from the third/fourth level as a clock signal transition and the word boundary. The bit clock can be recovered using a conventional clock multiplier. Bi-level signaling is used for data between the word boundaries. Additional signal states are available in the multi-level signal by modulating the pulse width at the third/fourth signal level.

Abstract: A method and apparatus for providing a single-chip digital multimedia receiver for multi-channel/multi-tuner rendering comprising receiving multiple independently encoded input streams on a system-on-a-chip, and independently locking each video output to a corresponding input channel, to ensure that each video and audio output has a clock matched to an encoder clock.

Abstract: Digital video data is transmitted from a video source (61) to a video sink (62) as a group of three multilevel symbols (611, 612, and 613) per pixel color with each associated symbol being sent at a rate of three times the pixel clock (601). When eleven levels are used per symbol (611) and undesirable symbol groups having excess DC residual or minimal energy are eliminated, and a built-in-test symbol group is added for pixel alignment; there results a one-to-one correspondence between the remaining symbol groups available and the two-hundred and sixty possible states that are used in the TMDS physical layer that is in widespread commercial use.

Abstract: The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

Abstract: A method and system for removing the effect of intersymbol interference (ISI) from a data record indicating times of logic level transitions exhibited by a data signal that has been distorted by ISI exhibited by a system having a particular step response may perform the following acts. The data record may be received, and a transition from within the data may be selected record for removal of ISI. Preceding transitions within the data record are then inspected. A time defect is obtained, based at least in part upon the inspected preceding transitions. Finally, the data record is adjusted, based upon the time defect, to indicate a new time of transition for the selected transition, thereby removing the effect of ISI for the selected transition.

Abstract: Techniques for assigning primary synchronization code (PSC) sequences and secondary synchronization code (SSC) sequences to cells in a wireless communication system are described. At least one PSC sequence and multiple SSC sequences may be used for multiple cells in a Node B. In one design, the available SSC sequences in the system may be arranged into groups, with each group including M different SSC sequences. Additional groups of M SSC sequences may be formed with different permutations (e.g., different cyclic shifts) of each group of M SSC sequences. In one design, three SSC sequences SSC(G1), SSC(G2) and SSC(G3) may be used for three cells in one Node B. A first permutation including SSC(G3), SSC(G1) and SSC(G2) may be used for three cells in another Node B. A second permutation including SSC(G2), SSC(G3) and SSC(G1) may be used for three cells in yet another Node B.

Abstract: This invention provides a method of detecting time alignment of an analog audio signal and a digital audio signal in a hybrid radio system. The method comprises the steps of filtering the analog audio signal to produce a filtered analog audio signal, filtering the digital audio signal to produce a filtered digital audio signal, and using the filtered analog audio signal and the filtered digital audio signal to calculate a plurality of correlation coefficients, wherein the correlation coefficients are representative of time alignment between the analog audio signal and the digital audio signal. An apparatus for performing the method is also provided.

Abstract: A system and method for providing a digital In-Flight Entertainment (IFE) system in a vehicle, such as an aircraft, that is capable of presenting a video program and associated audio in a synchronized manner to a large number of individual video monitors and speakers. The system and method employ processing operations in at least one decoder of the IFE system, to perform operations such as adjusting a local clock based on a master clock, setting a delay time in relation to a master clock, and adjusting video and audio playback based on the delay, to substantially synchronize playback of the audio and video data by the audio and video players, to thus eliminate or at least minimize the negative effects of source and load based jitter, network delays, clock drifts, network errors and decoder buffering differences, on synchronizing video and audio playback.

Abstract: A clock data recovery circuit. The clock data recovery circuit comprises a transmission line, a phase locked loop, a voltage controlled oscillator, a phase selector, and a D flip-flop. The transmission line receives an input signal. The phase locked loop receives the input signal via the transmission line and a reference clock and generates a first clock signal. The voltage controlled oscillator receives the input signal via the transmission line and a control voltage from an internal node of the phase locked loop, and generates a clock signal. The phase selector receives the input signal via the transmission line and the clock signal from the voltage controlled oscillator, and generates a clock output signal. The D flip-flop receives the input signal via the transmission line and the clock output signal, and generates a data output signal.

Abstract: A multilevel symbol timing signal detector is provided, which is used for reliably detecting the symbol timing of a multilevel QAM signal. When an oversampling I signal is inputted to I-Signal Histogram Generator 610, the signal is subjected to 1-symbol length buffering by computing absolute values. Sampling times corresponding to an oversampling frequency and amplitude data for these times are extracted from the buffered data and the amplitude data is buffered for each sampling time over predetermined intervals. Histograms of the amplitude data for each sampling time are generated based on these buffered amplitude data. Symbol timing is acquired by detecting a sampling time corresponding to the amplitude data with the highest frequency of detection based on the histograms of amplitude data.

Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.

Abstract: Provided is a signal processing apparatus including an encoder for encoding, according to respective specific coding schemes, a first bit string formed from bit values at odd-numbered positions and a second bit string formed from bit values at even-numbered positions that are obtained by alternately extracting bit values from a bit string that is expressed by mutually different first and second bit values, and generating first and second encoded signals that do not include a DC component, and a signal generation unit for generating a multilevel signal by respectively adding, to a clock signal having larger amplitude than the first and second encoded signals that are generated by the encoder, the first encoded signal in synchronization with a timing of the clock signal being at a positive amplitude value and the second encoded signal in synchronization with a timing of the clock signal being at a negative amplitude value.

Abstract: A method of synchronizing a receiver with a transmitter. The method includes determining number of bits, j, for adjusting a bit stream, where the bit stream is generated from n tones and is dividable into codewords having a codeword length of N bytes, and the number of bits for adjusting the bit stream is determined based upon n and N. The method includes detecting a loss of synchronization indication. In response to detection of the loss of synchronization indication, the method includes adjusting the bit stream by j bits. The method includes determining whether synchronization has been regained. When synchronization has not been regained, the method includes adjusting the bit stream again by j bits. When synchronization has been regained, the method includes terminating adjustment of the bit stream.

Abstract: A buffer management method based on a bitmap table includes: dividing the bitmap table into a plurality of areas each containing at least one bit; determining and recording an idleness status of each of the areas in accordance with an unoccupied status of the bit in the area; and performing a management on a buffer address pointer in accordance with the recorded idleness status of each of the areas. The entire inventive procedure of allocating a buffer address pointer is fixed and easily controllable, and the RAM consumed for management on each buffer element including at least a 1-bit buffer space is approximately 1 bit, with a relatively fewer resources being consumed. The invention can enable that it takes two clock cycles on average to complete one procedure of allocating a buffer address pointer, and thus the efficiency in allocating and reclaiming a buffer address pointer is high, and the controllability during buffer management is improved.

Abstract: A method of allocating sub-channel signal interleaving patterns to BSs forming a wireless communication system that divides a frequency band into a plurality of sub-carriers and including a plurality of sub-channels, which are a set of predetermined adjacent sub-carriers. The method includes: creating a basic orthogonal sequence having a length identical to a number of the sub-carriers forming the sub-channel; creating a plurality of sequences having a same length as the basic orthogonal sequence by cyclic-shifting the basic orthogonal sequence a predetermined number of times or performing a modulo operation based on a number of the sub-carriers forming the sub-channel, after adding a predetermined offset to the cyclic-shifted basic orthogonal sequence; selecting a predetermined number of sequences corresponding to a number of the BSs from among the plurality of sequences; and allocating the selected sequences as the sub-channel signal interleaving patterns for the BSs.

Abstract: The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and, logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

Abstract: In a provided information processing device, a first information processing module, within its transmission time segment, transmits an encoded signal in which mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the same amplitude value not occurring consecutively and the amplitude value polarity being inverted with each cycle. Within a transmission time segment for a second information processing module, the first information processing module transmits a clock signal that corresponds to the cycle at which the polarity is inverted.

Abstract: In a recording and reproducing apparatus for recording and reproducing video data, includes: a shuffling memory (6); a writing means for writing video data into the shuffling memory in accordance with the synchronizing signal and a write reference clock signal in synchronization with the video data; and a reading means for reading out the video data from the shuffling memory in accordance with a synchronizing signal and a stabilized read reference clock which is asynchronous with the write clock signal.

Abstract: Provided is a system and method for terrestrial digital broadcasting service using a single frequency network without additional equipment. The system and method synchronizes input signals into transmitting stations by inserting a transmission synchronization signal into a header of TS periodically, and solves the problematic ambiguity of the trellis encoder by including a trellis encoder switching unit separately and initializing a memory of the trellis encoder. The terrestrial digital broadcasting system includes: a broadcasting station for multiplexing video, voice and additional signals into transport stream (TS) and transmitting the TS to the transmitting stations and a transmitting stations for receiving the TS and broadcast the TS to receiving stations through a single frequency network.