Abstract: Apparatus and methods for distributing synchronization throughout a network is disclosed. The distribution of the synchronization is through the use of generating a reference timing signal, and by counting the line clock pulses between the start of a frame and the timing reference signal pulse at a first office and that count is then encoded and transmitted to the next office. At the next office, the transmitted count is decoded and used for regenerating synchronization by counting a number of received line clock pulses from the start of the frame to regenerate the reference timing signal. Particular criteria for selecting the frequencies for the timing reference signal are disclosed.

Abstract: A method and a circuit for simple clock recovery from multi-level at high transmission rates. The circuit is compatible with standard PLL-type clock recovery techniques for NRZ and generalized two-level signalling. The timing information is extracted from a single threshold crossing, irrespective of the number of levels (M) of the signal. This was verified to provide sufficient spectral information for the proper operation of a clock recovery PLL. The threshold may be programmed for various line codes.

Abstract: A clock extraction circuit for retiming a ternary data stream derives first and second binary streams corresponding respectively to the positive and negative going portions of the ternary data stream These binary streams are combined to provide a further binary stream which is retimed to a local clock whereby to generate a reference stream for retiming the first and second binary data streams to said reference stream. The retimed binary data streams are combined to generate a retimed ternary data stream.

Abstract: A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.

Abstract: Binary data is transmitted to a network physical layer from a media access controller as a series of multibit nibbles and is encoded into a multi-level data stream and split among a number of transmission channels, thereby reducing the signal frequency necessary to carry the data on each one of the transmission channels. The multi-level signal is then translated at a receiver back into a binary data stream. In a specific embodiment, the symbol transmission frequency on each of the transmission channels is at the same frequency as the nibble transfer rate between the media access controller and the physical layer.

Abstract: Existing infrastructures such as DS1 or E1 are used at currently accepted rates to carry a third more information by using a hybrid encoding technique wherein a 4B3T encoding is done for the payload bits, while a 1B1T encoding technique is used for framing information. In this way, for example, a DS1 can be used at 1.54 Mbit per second to carry 2.058 Mbits of binary payload, while respecting the 8 kilobits of framing expected by DS1 hardware. Similarly, for example, an E1 infrastructure can be used at the accepted 2.048 Mbit per second rate to carry 2.560 Mbits of binary payload plus 128 kilobits of binary framing/CRC without having to change the accepted E1 framing techniques.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: A block demodulation method and apparatus that provides for synchronizing bursts of incoming data without a special symbol synchronization word, and minimal frame synchronization overhead. An entire burst, comprising ramp up time, a preamble, guard times, data and ramp down time, is captured and stored in the form of baseband samples of the signal burst. The burst samples are then filtered to reduce pattern jitter. Thereafter, the samples are squared to derive the symbol clock. Then, the samples are differenced and cyclically accumulated. The cyclicly accumulated samples are examined to find a valid zero crossing. In the event that the aforementioned method does not identify a valid zero crossing, two additional methods for finding a valid zero crossing are employed.

Abstract: A totally D.C. balanced and bit-rate independent digital clock encoding technique is applicable to a variety of digital signalling systems, including fiber optic digital signalling. Each of successive event cells of the clock signal is demarcated by clock transitions of opposite polarity, so that each clock cycle contains two event cells, one of which is redundant. For a first binary data value, such as a `0`, a pair of unmodified successive event cells of the clock signal are provided as an output. Namely, the clock signal is unaffected, so that both halves of a complete, unmodified clock cycle are reproduced `as is` as the encoded clock output. For a second binary data value, such as a `1`, an event cell is modified by inserting a pulse, of finite duration, less than the duration of the event cell, the pulse being delayed with respect to a leading clock transition of the pair of alternating, opposite clock transitions of the event cell.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: A data, synchronization device adapted to re-synchronize a multi-level digital signal (IN; OUT) with an output or local clock signal (CLKO). In case of a binary signal, the device includes two counter systems (CA1-CC1, MAJ1, SEL1; CA0-CC0, MAJ0, SEL0) each associated with a logical level of the signal and counting the number of successive 1's or 0's respectively. These counter systems produce a count number including the number of counted bits and their level. The device further includes a decoder (DEC) generating in synchronism with the local clock signal (CLKO) a number of bits which is a function of the count numbers. These generated bits constitute the requested output signal (OUT).

Abstract: A timing recovering apparatus comprises an equalizer for equalizing a digital data signal subjected to interleaved NRZI such that the digital data signal has partial response (1, 0, -1), two comparators for comparing the equalized data signal with two different reference levels, two phase comparing portions for detecting phase difference between the outputs of the comparators and a reproduced clock signal separately, an adder for summing the outputs of the phase comparators, and a VCO for generating the reproduce clock signal in accordance with the output of the adder. This timing recovering apparatus performs phase comparing with two different phase comparators and PLL control is performed on the sum of the outputs of the two different phase comparators, so that the clock signal is not affected by data pattern of the data signal.

Abstract: A DC removal circuit for removing residual DC from a digitally encoded signal including a plurality of multi level data symbols occurring at a constant symbol rate and formatted in repetitive data fields, each including repetitive data segments having data segment sync. A derived value is subtracted from each of the received data symbols. The output of the subtractor is sampled, at a rate that is less than the symbol rate, and the sampled output is accumulated in an accumulator for generating the derived value. The sampling is synchronized with the data segment sync to avoid sampling the data segment sync and the accumulator is disabled until data segment lock is achieved.

Abstract: Timing loop apparatus and method are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) providing samples to a digital filter during a tracking mode and to a gain and timing control during an acquisition mode. Sample values from the ADC are received at peaks and zeros on sync field pattern. An error absolute value is calculated from the received ADC sample values and an error sign of the calculated error absolute valve calculated using a most significant bit of the current and a previous sample. Timing correction values are calculated responsive to the calculated error absolute value and applied to a clock gated register that latches and holds the generated timing correction values for a predefined number of clock cycles.

Abstract: A high bit-rate serial communications link encodes data by inserting non-data 0's and 1's. These extra bits are removed by a decoder at the receiving end of the link. Transmission of data can be made along optical fibers.