Abstract: Circuits for receivers including: N first mixers that each receive an input signal, are each clocked by a different phase of a first common clock frequency, and each provide an output; and for each N first mixer: a set of M second mixers, wherein each second mixer receives as an input the output of a same one of the N first mixers unique to the set, wherein each of M second mixer is clocked by a different phase of a second common clock frequency, and wherein each second mixer has an output; a set of M resistors having a first side and a second side, wherein the first side is connected to the output of a corresponding one of the set of M second mixers; and a set of M trans-impedance amplifiers that each having an input connected to the second side of a corresponding one of the resistors.

Abstract: An analog-to-digital conversion circuit includes; a first analog-to-digital converter (ADC), a second ADC and a third ADC collectively configured to perform conversion operations according to a time-interleaving technique, and a timing calibration circuit configured to calculate correlation values and determine differences between the correlation values using first samples generated by the first ADC, second samples generated by the second ADC, and third samples generated by the third ADC during sampling periods, wherein the timing calibration circuit is further configured to control a phase of a clock signal applied to the second ADC in response to a change in absolute value related to the differences generated during the sampling periods.

Abstract: Circuits for a receiver, comprising: M first mixers that each receive an input signal, that are each clocked by a different phase of a first common clock frequency, and that each provide an output, wherein M is a count of the first mixers; and M sets of N second mixers, wherein N is a count of the second mixers in each of the M sets, wherein each second mixer in each set of N second mixers receives as an input the output of a corresponding one of the M first mixers, wherein each of the N second mixers in each of the M sets are clocked by a different phase of a second common clock frequency, and wherein each of the second mixers has an output.

Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

Abstract: A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.

Abstract: A method for synchronizing radio frequency carrier correction of dynamic radio frequency carriers is provided. The method includes receiving a carrier configuration from a carrier controller to modulate a carrier signal based on the carrier configuration and receiving a time reference and timestamped carrier configuration information from the carrier controller. The timestamped carrier configuration information includes a correlation between a plurality of timestamps and a plurality of carrier attributes. The method also includes synchronizing an internal clock of a RF correction preprocessor to the time reference, and receiving a modulated carrier signal from the RF modem. The method further includes generating a radio frequency correction set including a correction solution for each of a plurality of timeslots based on the timestamped carrier configuration information, and generating a corrected carrier signal based on applying the RF correction set to the modulated carrier signal at a coincident timeslot.

Abstract: Embodiments of an access point (AP) may comprise memory and processing circuitry coupled to the memory, and transceiver circuitry coupled to the processing circuitry. The processing circuitry of the AP may be configured to encode a trigger frame to allocate a center 26 tone RU of an 80 MHz channel for an HE-trigger-based PPDU, the center 26 tone RU having an adjacent upper 20 MHz subchannel and an adjacent lower 20 MHz subchannel. In an embodiment, the center 26 tone RU is for a station (STA) and wherein the trigger frame indicates to the STA to transmit a pre-HE-STF preamble on one of the adjacent upper 20 MHz subchannel, the adjacent lower 20 MHz subchannel, or both the adjacent upper and lower 20 MHz subchannels, and configure the wireless device to transmit the trigger frame to the station.

Abstract: Systems and method for resampling are provided. A method of resampling includes receiving a first sampled signal that is sampled at a first sample rate, where the first sample rate is a submultiple of a system clock rate for a Farrow filter. The method further includes resampling the first sampled signal, using the Farrow filter having a plurality of finite impulse response (FIR) filters and an arbitrary position interpolator, at a second sample rate to generate a second sampled signal. The interpolation factor for each sample of the second sampled signal is retrieved from at least one lookup table stored in memory and the first sample rate and the second sample rate are fixed and locked to a common frequency reference. The method further includes outputting the second sampled signal at the second sample rate.

Abstract: An electronic device may be operable to sample a signal during an analog-to-digital conversion using an analog-to-digital converter in the electronic device, and the signal may comprise a wide bandwidth and a plurality of channels. The electronic device may adaptively change a sample rate of the sampling to move aliasing out of a region of one or more desired channels of the plurality of channels. The electronic device may change the sample rate using a variable oscillator in the electronic device. The change of the sample rate may comprise, for example, increasing or decreasing the sample rate by a particular percentage. In response to the change of the sample rate, the electronic device may perform, using a variable rate interpolator in the electronic device, variable rate interpolation. The variable rate interpolator may comprise, for example, a finite impulse response filter.

Abstract: A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

Abstract: The present invention discloses a receiver for coherent optical transport systems based on analog signal processing and the method of recovering transmitted data by processing signals in electronic domain. In the present invention, high-speed electrical signals obtained from optical-to-electrical converters which carry transmitted data information in a coherent transport system are jointly processed in analog domain itself without converting these signals to the digital domain using high speed ADCs. Different processing steps which may include carrier phase & frequency offset recovery and compensation, polarization mode dispersion and/or chromatic dispersion, clock & data recovery and deserialization may be performed while keeping the information signals in analog domain itself.

Abstract: An encoder signal processing device detects position data at every predetermined time interval from an original signal which is an analog amount generated in an encoder according to movement of a measurement target. The encoder signal processing device includes: an approximate curve calculation unit that calculates an approximate curve of a detection error included in the original signal on the basis of the detection error of the position data at at least three or more points; an approximate error computation unit that computes an approximate value of the detection error of the position data at an arbitrary time point on the basis of the approximate curve of the detection error; and a position data correction unit that corrects the detection error of the position data at the arbitrary time point on the basis of the approximate value of the detection error of the position data.

Abstract: Aspects herein describe techniques for synchronizing clocks between two moving platforms (e.g., land vehicles, ships, aircraft, and the like) using optical signals generated from lasers. In one aspect, a method for mixing an intermediate signal with a local reference clock in a method of communicating between moving platforms includes mixing the intermediate signal with a sine representation of the local reference clock to generate a first offset error; mixing the intermediate signal with a cosine representation of the local reference clock to generate a second offset error; and combining the first and second offset errors to generate the fine phase offset.

Abstract: The present disclosure provides techniques for performing bit-level interleaving for orthogonal frequency-divisional multiplexing (OFDM) symbols across a plurality of code blocks. In some aspects, a transmitting device may dynamically switch between bit-level interleaving and tone-level interleaving for each OFDM symbol based on factors such as number of bits that are carried in each tone, size of each code block, the processing time requirements of the transmitting device and/or the receiving device, or the transmitting device preference.

Abstract: Apparatus and methods for frequency tuning of rotary traveling wave oscillators (RTWOs) are provided herein. In certain configurations, distributed quantized tuning is used to tune a frequency of the RTWO. The RTWO includes a plurality of segments distributed around the RTWO's ring, and the segments include tuning capacitors and other circuitry. The distributed quantized frequency tuning is used to control the tuning capacitors in the RTWO's segments using separately controllable code values, thereby enhancing the RTWO's frequency step size or resolution. Moreover, in configurations including multiple RTWO rings that are locked to one another to reduce phase noise, the distributed quantized frequency tuning can be used to separately set the tuning capacitors across multiple RTWO rings that are coupled to one another.

Abstract: Degradation of a reception performance by an image signal is reduced. A semiconductor device includes: an oscillation circuit configured to generate a local signal; a mixer configured to multiply a reception signal by the local signal; an analog filter configured to filter a signal output from the mixer; an AD converter configured to digitalize a signal that has passed through the analog filter to generate a first signal; a digital filter configured to filter a signal that has passed through the AD converter to generate a second signal; a power comparator configured to detect the power difference between the first signal and the second signal; a register configured to store a theoretical power difference; and a determination unit configured to determine a frequency of the local signal based on the power difference from the theoretical power difference.

Abstract: An implantable wireless device for transmitting data includes an external control device and an internal processing device. The external control device receives digital data and an alternating current carrier signal and uses the alternating current carrier signal to modulate the digital data into a phase shift keying modulation signal. The digital data have a plurality of time points that binary data change. The internal processing device includes a phase-lock loop (PLL)-based phase shift keying demodulator. The PLL-based phase shift keying demodulator obtains a ripple voltage signal according to the phase shift keying modulation signal. The ripple voltage signal decreases from a fixed voltage value at each of the plurality of time points and then increases to the fixed voltage value. The PLL-based phase shift keying demodulator demodulates the ripple voltage signal into the digital data.

Abstract: According to one embodiment, an RF frontend IC device includes a first RF transceiver to transmit and receive RF signals within a first predetermined frequency band and a second RF transceiver to transmit and receive RF signals within a second predetermined frequency band. The RF frontend IC device further includes a full-band frequency synthesizer coupled to the first and second RF transceivers to perform frequency synthetization in a wide frequency spectrum, including the first and second frequency bands. The full-band frequency synthesizer generates a first LO signal and a second LO signal for the first RF transceiver and the second RF transceiver to enable the first RF transceiver and the second RF transceiver to transmit and receive RF signals within the first frequency band the second frequency band respectively. The first RF transceiver, the second RF transceiver, and the full-band frequency synthesizer are integrated within a single IC chip.

Abstract: A robust frequency drift tracking receiver. The received signal is translated to an intermediate frequency in the RF stage by a quadrature demodulator, and is then brought into the base band by a digital mixer made by a CORDIC. A base band processing stage allows for a synchronization of the receiver relative to the data frame, to estimate data and to output a counter-reaction signal to the CORDIC, obtained by integration of successive frequency corrections, with a predetermined step.

Abstract: Techniques pertaining to an adaptive/configurable IF wireless receiver are disclosed. Such an adaptive/configurable IF wireless receiver can be used in a Bluetooth device.

Abstract: A frequency converter (100, 200, 300, 500, 600) comprising a first mixer (105) arranged to receive a first and a second input signal and to have as its output the sum and the difference of the first and second input signals. The frequency converter (100, 200, 300, 500, 600) also comprises generating means (120) for generating the second input signal and for receiving the output signal of the first mixer (105) and multiplying it by a signal at a frequency which is two times the frequency of the second input signal, thereby generating a product. The frequency converter (100, 200, 300, 500, 600) also comprises adding means (110) for obtaining the sum of this product and the output signal from the first mixer.

Abstract: A data processing device includes a splitter in which an input stream made up of a plurality of packets is split, so as to generate split streams of a plurality of channels, of which the smallest increment is base band frames (BBFs) where the packets of the input stream are placed in consecutive order in a data field of the BBF which is the object of forward error correction (FEC).

Abstract: A method for operating a phase shifter chip RF self-test. The method includes outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, outputting, by the control hardware, a second signal from the pre-amplifier to a device under test, selecting, by the control hardware, a target level, and adjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to cause the input peak detector value to approximately match the target level. The input peak detector is configured to output an input peak detector value based on the first signal.

Abstract: A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.

Abstract: Embodiments related to systems, methods, and computer-readable media to enable a digital phase locked loop are described. In one embodiment, a digital synthesizer comprises a digital phase locked loop with detection circuitry to calculate an estimate of a magnitude and a phase of a spurious response from an error signal within the digital phase locked loop. The digital phase locked loop further comprises generation circuitry to generate an inverse spur based on the estimate of the magnitude and the phase, and further comprises injection circuitry to inject the inverse spur into the digital phase locked loop. In some embodiments, least mean squares (LMS), recursive least squares (RLS), or other such adaptation is used to estimate the magnitude and phase of the spurious response.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: A digital system of measuring parameters of the signal (phase, frequency and frequency derivative) received in additive mixture with Gaussian noise. The system is based on the use of variables of a PLL for calculating preliminary estimates of parameters and calculating the corrections for these estimates when there is a spurt frequency caused by a receiver motion with a jerk. A jerk is determined if the low pass filtered signal of the discriminator exceeds a certain threshold. The jerk-correction decreases the dynamic errors. Another embodiment includes a tracking filter for obtaining preliminary estimates of parameters to reduce the fluctuation errors. Estimates are taken from the tracking filter when there is no jerk and from the block of jerk-corrections when there is a jerk.

Abstract: An RF receiver includes an RF signal reception path to process an input signal for the receiver for a first mode of the receiver; an oscillator; and a harmonic generator. The harmonic generator generates a harmonic signal in response to operation of the oscillator to replace the input signal with the harmonic signal for a second mode of the receiver.

Abstract: A digital Radio Frequency (RF) receiver may exhibit image frequencies and these image frequencies may be mathematically related to the intermediate frequency (IF) that is utilized for transmission and reception. In accordance with an embodiment, channel switching may be performed to identify an appropriate receive frequency in the presence of image frequencies on other channels. In accordance with another embodiment, data on a receive channel is evaluated to determine whether the data is inverted, and then appropriate correction may be performed on subsequently received data.

Abstract: A frequency synthesizing circuit comprising a first mixer configured to receive a first input signal, a first filter configured to receive an output of the first mixer and to remove undesired frequency signals from the output signal of the first mixer, and a feedback loop configured to provide an output of the first filter to an input of the first mixer. The feedback loop comprises a second mixer arranged within the feedback loop configured to receive the output of the first filter and to mix the output of the first filter with a second input signal.

Abstract: Adjusting a relative phase within a polar receiver to reduce a DC error, the polar receiver having (i) a harmonic ILO having an RF modulated signal input and a phase-compressed divided-frequency output, (ii) a fundamental ILO connected to the phase-compressed divided-frequency output and having a phase-locking output, (iii) a delay element, and (iv) a phase discriminator connected to the delay element output and to the phase-locking output, and having a phase-detection output representative of a phase difference between signals on the delay output and the phase-locking output.

Abstract: This disclosure includes embodiments of a tunable hybrid coupler. The tunable hybrid coupler includes a first inductive element having a first inductance, a second inductive element having a second inductance and mutually coupled to the first inductive element, a first variable capacitive element having a first variable capacitance, and a second variable capacitance having a second variable capacitance. The first variable capacitive element is coupled between a first port and a second port. The second variable capacitive element is coupled between a third port and a fourth port. The first inductive element is coupled from the first port to the third port, while the second inductive element is coupled from the second port to the fourth port. Accordingly, the tunable hybrid coupler may form an impedance matching network that is tunable to different radio frequency (RF) communication bands. The tunable hybrid coupler can be used in a tunable RF duplexer.

Abstract: A multi-link input/output (I/O) interface uses both feed-forward and feedback signaling to reduce the impact of noise on data capture at a memory controller. To transfer data from a source module to a destination module, a defined pattern is communicated from the memory module along a master channel concurrent with the memory module providing data via one or more slave channels. Based on the phase of the defined pattern as it is received, the multi-link I/O interface feeds forward to the slave channels control signaling whose phase reflects a predicted noise pattern for the system. Each slave channel performs CDR by adjusting timing of its corresponding capture clock signal based on the fed forward control signaling and based on feedback signaling for the corresponding slave channel, whereby the feedback signaling reflects an error measurement between a phase of a capture clock signal and transitions in received data.

Abstract: The present invention concerns a method and associated apparatus for reducing the time required to scan an incoming satellite transmission power spectrum for available signals and to determine the characteristics of those signals. The frequency range of interest is scanned in narrow slices to determine approximate input power within each slice. Center frequencies and symbol rates of individual transponders are then estimated based upon these input power approximations.

Abstract: A storage device configured to communicate with a host according to a serial communication standard. The storage device includes a receiver configured to receive host data from the host; a clock data recovery circuit configured to determine a first frequency of host data transmitted by a host; a phase locked loop configured to generate a local phase corresponding to a local clock signal; a frequency offset calculator configured to generate a frequency offset corresponding to the first frequency and a second frequency of the local clock signal; an accumulator configured to generate a phase offset corresponding to a difference between the local phase and a phase of the host data; an interpolator configured to generate a compensated local clock signal using the phase offset and the local phase; and a transmitter configured to transmit device data to the host using the compensated local clock signal.

Abstract: The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment and calibration computing equipment for receiving and processing test and calibration signals from wireless communications circuitry to be calibrated. During testing and calibration operations, a device may be provided with initial pre-distortion calibration values. The initial pre-distortion calibration values may be generated at least in part based on calibration operations performed for other wireless electronic devices. The device may generate a test signal using the initial pre-distortion calibration values. The calibration system may determine whether the test signal is within an acceptable range of a known reference signal.

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract: The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.

Abstract: A method of analyzing a phase of a clock signal for receiving data is described. The method comprises identifying an end of an eye pattern associated with received data; testing points along a contour of the eye pattern to establish a margin for an opening of the eye pattern; and determining whether a phase of the clock signal is acceptable for receiving the received data. A circuit for analyzing a phase of a clock signal for receiving data is also described.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.

Abstract: A continuous-time delta-sigma digital-to-analog converter (DAC) includes a first delta-sigma modulator configured to quantize a most significant bit or bits of a digital input signal and produce a first quantization error signal, and a second multi-stage delta-sigma modulator configured to quantize less significant bits of the digital input signal. A first DAC is coupled to an output of the first delta-sigma modulator, and a second DAC is coupled to an output of the second noise-shaping filter. The second DAC has a greater resolution than the first DAC. A low pass output filter is coupled to a sum of an output of the first DAC and an output of the second DAC.

Abstract: Briefly, in accordance with one or more embodiments, in response to receiving a single carrier signal that is not phase locked, channel equalization may be applied to the signal via a channel equalizer. The equalized signal may be phase averaged to provide a signal that is at least partially phase stabilized. The channel equalizer may then be trained by feeding back the at least partially phase stabilized phase reference to the channel equalizer. The resulting signal may then be decoded via coherent or quasi-coherent detection.

Abstract: A receiver is an ATSC (Advanced Television Systems Committee)-receiver and comprises a phase lock loop (PLL) for performing carrier tracking of a carrier in a received signal. The PLL includes a detector (160) comprising two pseudo-Hilbert filters (205, 215). The detector uses energy from both band edges of the received ATSC signal for driving the PLL.

Abstract: A method includes relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path thereof when there is a near-integer relationship between the reference clock frequency input and the output frequency. The method also includes filtering the spur frequency component through the phase-locked loop.

Abstract: Methods and apparatus for processing multichannel signals in a multichannel receiver are described. In one implementation, a plurality of demodulator circuits may provide a plurality of outputs to a processing module, with the processing module then simultaneously estimating noise characteristics based on the plurality of outputs and generating a common noise estimate based on the plurality of outputs. This common noise estimate may then be provided back the demodulators and used to adjust the demodulation of signals in the plurality of demodulators to improve phase noise performance.

Abstract: Methods and systems to generate control signals for timing recovery of a signal received over baseband communications systems are disclosed. The timing control circuit uses a multi-rate DSP structure for the implementation of the DSP functions in the control loop for use in an ASIC and requires a reduced DSP clock rate, which in turn reduces the need for pipelining and/or high-speed libraries. Thus lower latency, better tracking performance and lower power consumption are achieved. An example embodiment involves splitting the timing error signal, supplied at a given update rate, into a sum and a difference component, and processing each component in separate circuit chains at half the update rate. The resultant half-rate control signals from each separate circuit chain are joined to provide a control signal at the full update rate. Thus, implementations of the present disclosure perform like a full-rate structure, but require a halved DSP clock rate.

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract: An apparatus includes a data flow circuit and a clock recovery circuit. The data flow circuit is configured to extract client data, which is encapsulated in an inner frame that is encapsulated in at least an outer frame, and to output the extracted client data in accordance with a client clock signal. The clock recovery circuit includes a first clock recovery module that is configured to recover a first clock signal that matches payload data in the outer frame, and a second clock recovery module that is configured to derive from the first clock signal a second clock signal that matches the client data in the inner frame, and to produce the client clock signal from the second clock signal, for use by the data flow circuit.