Abstract: According to one embodiment, a register outputs a first control code in first and second operation modes, saves the first control code as a third control code at an end of the first operation mode, and outputs the third control code at a beginning of a third operation mode. In the first operation mode, a digital-to-analog converter supplies a control signal with a control voltage to a voltage controlled oscillator. In the second operation mode, the control signal is supplied to a buffer amplifier, the amplifier drives a bandlimiting filter, and the filter generates the control voltage. In the third operation mode, the control signal is supplied to the filter, and the filter generates the control voltage.

Abstract: A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.

Abstract: A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.

Abstract: This disclosure relates to analog to digital conversion using irregular sampling. A method may include combining an analog signal with a feedback signal into a combined signal, filtering the combined signal using a digital noise shaping filter into a combined noise shaped signal, modulating the combined noise shaped signal into a modulated signal, generating samples of the modulated signal, and reconstructing as a digital signal the analog signal from the samples of the modulated signal.

Abstract: A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.

Abstract: The present invention provides a communications system, node and method of operation for forming a wireless network from independently operating nodes that have the ability to self-synchronize with each other, independently determine master and slave modes of operation to cooperate as a network, and independently vary those functions to adjust to changes in the network.

Abstract: A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.

Abstract: To provide a complex bandpass ??AD modulator capable of suppressing the influence of an image component caused by a mismatch between I- and Q-channels on a signal component with low power consumption. A complex bandpass ??AD modulator 10 is configured by a subtraction unit 20, a complex bandpass filter 30, an addition unit 40, a noise extraction circuit unit 50, an ADC unit 60, and a DAC unit 70. The noise extraction circuit unit 50 extracts a quantized noise signal of the ADC unit 60 based on an input signal of the ADC unit 60 and an output signal of the DAC unit 70, delays the extracted quantized noise signal by one sample time, phase-rotates the delayed signal by a predetermined angle, and feeds back the rotated signal to the input side of the ADC unit 60. Thus, a complex bandpass ??AD modulator capable of suppressing the influence of the image component caused by a mismatch between I- and Q-channels on the signal component with low power consumption is provided.

Abstract: A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.

Abstract: The invention relates to a circuit and method for receiving a signal of which—at the receiver end—the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived—estimated—circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.

Abstract: A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.

Abstract: A receiver having an intermediate frequency error correction circuit includes a mixer having a source input, a local oscillator input, and an IF output, an adjustable frequency local oscillator having an output coupled to the local oscillator input of the mixer, an IF filter having an input coupled to the IF output of the mixer and an IF filtered output, where the IF filter has an IF filter frequency response, and control circuitry coupled to the local oscillator such that the frequency of the local oscillator can be varied to at least: partially correct an IF frequency error.

Abstract: A system and method are disclosed for transmitting and receiving signals. The method includes receiving a received signal; demodulating the received signal by mixing the received signal with a receiver local oscillator signal generated by a voltage controlled oscillator configured to generate the receiver local oscillator signal; switching the configuration of the voltage controlled oscillator to generate a transmission signal for use by a transmitter; and transmitting a modulated signal derived from the transmission signal.

Abstract: The invention describes a field bus system, in particular a field bus system (10), comprising at least one clocked transmitter (16) and one clocked receiver (17) for transmitting data signals to another field bus device (30) or for receiving data signals from the other field bus device (30). To allow interfering emissions to be reduced, a spread spectrum clock (40) is provided which supplies a local spread spectrum clock signal (SST1). The spread spectrum clock signal is sent to the transmitter (16) and the receiver (17) to allow data signals (DO1, DI1) to be transmitted and received synchronously with the local spread spectrum clock signal.

Abstract: A frequency synthesizer includes a phase-locked loop circuit having an output. A frequency divider is connected to the output of the phase-locked loop circuit for receiving the signal therefrom and dividing the frequency of the signal. A tunable bandpass filter is connected to the frequency divider and is tuned for selecting a harmonic frequency to obtain a fractional frequency division for a signal output from the phase-locked loop circuit.

Abstract: Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first- reference frequency (in accordance with a receiver implementation).

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: Frequency of an oscillating signal is temporarily adjusted to adjust frequency and/or phase of an output signal. For example, the frequency of the oscillating signal may be adjusted for a very short period of time to adjust the phase of the output signal. In addition, the frequency of the oscillating signal may be temporarily adjusted in a repeated manner to adjust the effective frequency of the output signal. In some aspects the frequency of the oscillating signal is adjusted by reconfiguration of reactive circuits associated with an oscillator circuit.

Abstract: A method may include performing a logical exclusive OR and a logical inverse exclusive or on an input reference signal and an output signal to generate an XOR signal and an XNOR signal, respectively. The method may also include generating a switch control signal indicative of whether a first phase of the input reference signal leads or lags a second phase of the output signal. The method may additionally include: (i) transmitting the XOR signal to an output of a switch if the first phase leads the second phase; and (ii) transmitting the XNOR signal to the output of the switch if the first phase lags the second phase. The method may further include generating a phase detector output signal indicative of a phase difference between the second phase based on a signal present on the output of the switch.

Abstract: Arbitrary phase variations of a shared frequency synthesizer can be calibrated using a reference harmonic each time the shared frequency synthesizer is allocated to a network device to enable one frequency synthesizer to be shared between multiple network devices. On determining that the shared frequency synthesizer has been allocated to the network device, an output frequency of the shared frequency synthesizer can be aligned with a predetermined reference frequency that is associated with an operating frequency band of the network device. A phase correction factor associated with the shared frequency synthesizer can be calculated from a signal calculated based, at least in part, on the output frequency of the shared frequency synthesizer and the predetermined reference frequency. The phase correction factor is applied to a signal received at the network device to correct a phase error associated with the shared frequency synthesizer.

Abstract: A device and method to compensate for distortions of amplitude that afflict systems for communicating through capacitive coupling. A circuit includes a first transmitter stage, a first receiver stage, and a first coupling capacitor, coupled between the first transmitter stage and the first receiver stage. The first receiver stage includes a calibration amplifier of a variable-gain type coupled between the first coupling capacitor and an output of the electronic circuit. The electronic circuit includes a reference channel formed by: a transmission calibration stage; a reception calibration stage; and a reference capacitor coupled between the transmission calibration stage and the reception calibration stage.

Abstract: An electronic system having a spread spectrum clock is disclosed. A spread spectrum clock source creates and transmits both a spread spectrum clock signal and a modulation signal. A spread spectrum clock generator uses a modulation waveform on the modulation signal to frequency modulate a reference oscillator frequency. A logic unit comprises a Phase Locked Loop that receives the spread spectrum clock signal and the modulation signal and generates a logic unit clock signal.

Abstract: A method of computing a vector angle by using a CORDIC and an electronic apparatus using the same are disclosed. The electronic apparatus mainly includes a phase error detector, a loop filter, a small-area iteration LUT module and a phase compensation circuit. The phase error can be locked by using the error function in the phase error detector, and even the phase error can be locked to the minimum so that the error oscillates up-and-down about the zero level. The first transfer function in the loop filter can determine the baseband and the converging speed. Moreover, if the shifting technique is used, the operation of the first transfer function is speeded up. By using a phase-locking loop in association with looking up the above-mentioned LUT, the method is able to get fast converging and higher accuracy for the computation.

Abstract: Embodiments of the present invention relate to a system for clock synthesis or data timing recovery. No analog continuous time oscillator is required, all the building blocks of a Frequency Locked Loop/Phase Locked Loop belonging in the digital discrete time domain. From a system-level perspective, the system is characterized by its strong non-linear behavior due to the intrinsic nature of some building blocks. This inherent non-linearity is responsible for some unusual, attractive property of the complete system. The system is able to multiply the input frequency clock by an arbitrarily large factor, ensuring in any case the convergence of the algorithm in two reference clock cycles.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: The present invention describes methods and circuitry for a sub-rate bang-bang phase detector, in which the reference clock has frequency that is a fraction of the bit rate of the received data stream. The sub-rate bang-bang phase detector is enabled by multiple phases of the reference clock.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.

Abstract: A receiver can be configured to include an RF front end that is configured to downconvert a received signal to a baseband signal or a low Intermediate Frequency (IF) signal. The receiver can downconvert the desired signal from an RF frequency in the presence of numerous interference sources to a baseband or low IF signal for filtering and channel selection. The filtered baseband or low IF signal can be converted to a digital representation. The digital representation of the signal can be upconverted in the digital domain to a programmable IF frequency. The digital IF signal can be converted to an analog IF signal that can be processed by legacy hardware.

Abstract: A 4× over-sampling data recovery system consists of a charge pump PLL, a 4× over-sampler, a data regenerator and a digital PLL. The charge pump PLL receives a clock signal and generates a plurality of multiplicative clock signals in response to the clock signal. The 4× over-sampler samples a serial data to generate a M-bit signal according to the plurality of multiplicative clock signals, wherein each bit in the serial data is sampled for four times. The data regenerator sequentially receives and combines two M-bit signals to generate a (M+N)-bit signal. The digital PLL divides the (M+N)-bit signal into (N+1) groups of M-bit data and selects a designated M-bit data from the (N+1) groups of M-bit data to generate a P-bit recovery data.

Abstract: An automatic gain control (AGC) circuit and method for performing AGC for an orthogonal frequency-division multiplexing (OFDM) receiver measures signal power of input digital signals that are derived from incoming data frames with preambles to produce gain change signals when the signal power differs from a reference target power level. The gain of an amplifier of the OFDM receiver is changed in response to the gain change signals until a preamble of the data frames is detected for the first time. The gain of the amplifier of the OFDM receiver is further changed in response to the gain change signals, after the preamble is detected, only during periods when the preambles of the data frames are being processed by the OFDM receiver such that the gain of the amplifier is not changed during periods when other portions of the data frames are being processed by the OFDM receiver.

Abstract: A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module that generates a reference frequency adjustment signal for correcting the reference frequency signal when the communications subsystem operates in closed loop mode. The subsystem further includes an open loop frequency correction means that that samples values of the reference frequency adjustment signal during the closed loop mode and generates a frequency correction signal for correcting the reference frequency signal when the communications subsystem operates in a mode other than closed loop mode.

Abstract: Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.

Abstract: A system for initiating scheduled program processing functions such as program display, recording or playback, derives a time clock based on a current time reference indication produced by a particular broadcast source. The derived time clock is used in initiating scheduled processing functions for programs derived from the particular broadcast source and time clocks derived from sources other than the particular broadcast source are disregarded. The system displays a second time clock different to the derived time clock. In addition, the system forms a composite program guide from data from multiple broadcast sources to associate current time reference indications with their corresponding broadcast sources.

Abstract: Recovering a data signal is disclosed. Recovering includes receiving an input signal from a magnetic recording channel, sampling the input signal according to a sampling clock having a sampling phase wherein the sampling phase is determined at least in part by comparing the sampled input signal to a signal associated with a decision, and filtering the sampled input signal according to a target.

Abstract: A spread spectrum clock signal generator modulates a reference clock signal based on a spread spectrum frequency profile and includes a phase-lock loop for generating a spread spectrum clock signal by aligning a phase of the modulated reference clock signal with a phase of the spread spectrum clock signal. The spread spectrum clock signal generator also includes a loop modulator for modulating the spread spectrum clock signal based on the spread spectrum frequency profile. Because the spread spectrum clock signal generator modulates both the reference clock signal and the spread spectrum clock signal based on the spread spectrum frequency profile, the spread spectrum clock signal has a non-distorted frequency profile and low phase jitter.

Abstract: A baud rate acquisition circuit (10) for synchronizing a sampling signal with an input signal operates in broad rate sweeping and a rate fine tuning phases. In the rate sweeping phase, a timing error detector (24) examines the sampling signal generated by a decimator (16). If the sampling signal is outside a rate acquisition range from the target rate, a rate sweeping algorithm selects a new sampling rate. In response to the sampling rate within the rate acquisition range, the timing error detector (24) examines the asymmetry thereof to generate a rate correction signal to synchronize the sampling signal with the input signal. Next in the rate fine tuning phase, a multiplexer (22) routes the sampling signal through a square root filter (18). By examining the waveform shaped signal, the time error detector (24) synchronizes the sampling signal with the input signal with high accuracy.

Abstract: Systems of clock generation for integrated radio frequency receiver. In an integrated radio frequency receiver, a mixer is often used to down convert the incoming radio frequency signal. The down converted signal is then digitized and digital signal processing circuitry is used for efficient and flexible implementation of various functions to receive the underlying audio and/or data information. The mixer requires clock generation circuitry to provide a proper local oscillator signal for a selected channel. On the other hand, the digital signal processing circuitry requires its separate digital clock for proper operations. The clock generation system utilizes single local oscillator generation circuitry to provide the local oscillator signals required by the mixer and the digital clock signals required by the digital signal processing circuitry.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: In one embodiment, a method includes receiving an input signal from a receiver, receiving a data clock (DCLK) signal, and receiving a boundary clock (BCLK) signal. The method includes, based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal. The method includes, based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal. The method includes, based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.

Abstract: A multilevel QAM demodulator includes a phase difference calculation unit calculating a phase difference signal based on the common phase signal and orthogonal signal after the phase rotation compensation, a phase shift amount calculation unit calculating a phase shift amount indicating a degree of a phase shift based on the common phase signal and orthogonal signal after the phase rotation compensation and phase noise compensation, and a correction unit correcting the phase difference signal based on the phase shift amount. A phase rotation is performed for the phase noise compensation based on the phase difference signal corrected by the correction unit.

Abstract: With the objective of enhancing receiving performance of a receiver with respect to pulse signals spread by spread codes, the receiver comprises an RF front-end section which performs amplification, an AD converter section which AD-converts signals outputted from the RF front-end section, a baseband section which inversely spreads the output of the AD converter section and performs signal detection and demodulation thereon, a reception environment measuring section which measures reception environment using the input signals of the baseband section, and a parameter setting section which sets parameters for respective parts on the basis of signals outputted from the reception environment measuring section. The parameter setting section sets the parameters for the respective parts to the optimum according to the environmental condition measured by the reception environment measuring section.

Abstract: The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained.

Abstract: Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track-and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with “re-used” or shared analog processing circuitry.

Abstract: An integrated receiver circuit includes a phase locked loop circuit (21) with a voltage controlled oscillator (VCO) (25) and a quadrature generator circuit (29) which uses hybrid-branch line coupler circuits (27, 28) coupled to buffered VCO outputs, where the hybrid-branch line coupler circuits (27, 28) are tuned by same control voltage (25a) that controls the VCO (25). By replicating the VCO core circuitry in each hybrid-branch line coupler circuit (27, 28) under common control of a control voltage, calibrated quadrature signals are generated that have the same frequency as the phase locked loop circuit (21).

Abstract: The invention relates to a method or to a correspondingly equipped circuit for line-coupled generation of a clock (t), wherein the clock (t) is controlled in relation to a synchronization signal (hs) and by means of a closed loop (FLL) with respect to the phase and/or the frequency in relation to the synchronization signal (hs); wherein a plurality (n) of at least two count values (cn, c0-c7) is determined, wherein each of the count values (cn, c0-c7) is determined with at least one count duration number (z) of consecutive periods of the synchronization signal (hs), and wherein each of the count values (cn, c0-c7) is determined offset relative to at least one further count value (cn, c0-c7) with a count offset (v) which is different from the count duration number of consecutive periods of the synchronization signal (hs).

Abstract: A clock generation circuit includes: a first determination circuit that detects an input signal at a first phase position based on first frequency signal; a second determination circuit that detects the input signal at a second phase position based on second frequency signal; a phase detector that compares output of the first determination circuit and output of the second determination circuit; a first summing circuit which sums comparison result and first control signal; a second summing circuit which sums comparison result and second control signal; a first voltage controlled oscillation circuit which receives output of the first summing circuit and outputs the first frequency signal; a second voltage controlled oscillation circuit which received output of the second summing circuit and outputs the second frequency signal; and a phase adjustment circuit which generates first control signal and second control signal based on first frequency signal and second frequency signal.

Abstract: The present invention provides a communications system, node and method of operation for forming a wireless network from independently operating nodes that have the ability to self-synchronize with each other, independently determine master and slave modes of operation to cooperate as a network, and independently vary those functions to adjust to changes in the network.

Abstract: Systems and devices for controlling frequency drift in satellite broadcast systems. A receiver antenna system for a direct broadcast satellite signal communications system in accordance with one or more embodiments of the present invention comprises an oscillator, a mixer, coupled to the oscillator, for converting satellite signals at a first frequency to signals at an intermediate frequency, an analog-to-digital (A/D) converter, coupled to the mixer, for receiving the signals at the intermediate frequency and for converting the signals at the intermediate frequency at near-real-time to a digital data stream, a Digital Signal Processor (DSP), coupled to the A/D converter, for processing the digital data stream, and a drift estimator, coupled to the DSP, the drift estimator determining a frequency drift of the oscillator, wherein the receiver antenna system corrects the frequency drift of the oscillator using the determined frequency drift.

Abstract: In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost.

Abstract: A novel interpolating phase detector for use in a multiphase PLL is described comprising an array of individual phase comparators, all operating at essentially the same operating point which permits the circuits to be designed simultaneously for high speed and for low power consumption. Two adjacent phase outputs of a multi-phase VCO may be selected and interpolated in between, by selectively attaching a variable number of phase comparators to each phase output and summing their phase error outputs. By varying the number of phase comparators attached to each phase output, interpolation can be achieved with high linearity.