Abstract: A method is provided. A multi-amplitude signal is received and downconverted so as to generate I and Q signals using a local oscillator signal. The I and Q signals are equalized, and the equalized I and Q signals are digitized. First and second gains are adjusted with the second and first digital signals, respectively, and applied to the equalized I and Q signals, respectively. The difference between the first and second amplified signals is determined, and an error signal is generated from the difference between the first and second amplified signals. The local oscillator signal is then adjusted with the error signal.

Abstract: A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.

Abstract: Embodiments of circuits and methods are described for decreasing transmitter waveform dispersion penalty (TWDP) in a transmitter. A data stream is received for transmission across a channel and a main data signal is generated from the data stream. At least two cursor signals are generated where each of the at least two cursor signals are shifted at least a portion of a clock period from the main data signal. The at least two cursor signals are subtracted from the main data signal to generate an output data signal with improved TWDP. Other embodiments include generating a main data signal, a pre-cursor signal shifted on previous clock cycle relative to the main data signal, and a post-cursor signal Shifted one subsequent clock cycle relative to the main data signal. The pre and post cursor signals are subtracted from the main data signal to generate an output data signal.

Abstract: A method of performing timing error detection includes receiving, by a multi-core processor, a data stream and up-sampling the data stream by a plurality of processing cores of the multi-core processor. The up-sampling is performed in parallel by the plurality of processing cores. The method includes selecting one sample per symbol of the data stream to generate a sampled data output. The method also includes performing symbol timing recovery based on the sampled data output to adjust a resampling point.

Abstract: A circuit, use, and method for controlling a receiver circuit is provided, wherein a complex baseband signal is generated from a received signal, a phase difference between a phase of the complex baseband signal and a phase precalculated from previous sampled values is determined, the phase difference is compared with a first threshold, a number is determined by counting the exceedances of the first threshold by the phase difference, a number of the counted exceedances is compared with a second threshold, and the receiver circuit is turned off if the number of counted exceedances exceeds the second threshold within a time period.

Abstract: A semiconductor integrated circuit includes a first wireless access system reception unit including a first analog reception unit and a first digital reception unit, a voltage-controlled oscillator, a phase locked loop, and a digital interface. The first analog reception unit comprises a first reception mixer for down-converting an RF reception signal into a first analog reception signal and a first analog-digital converter for converting the first analog reception signal into a first digital reception signal. The first wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop enable switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second RF reception signal of a second system.

Abstract: Compressing a variable phase component of a received modulated signal with a second harmonic injection locking oscillator, and generating a delayed phase-compressed signal with a fundamental injection locking oscillator, and combining the phase-compressed signal and the delayed phase-compressed signal to obtain an estimated derivative of the variable phase component, and further processing the estimated derivative to recover data contained within the received modulated signal.

Abstract: An exemplary clock and data recovery circuit includes a serial data input node arranged for receiving a serial data; a reference clock input node arranged for receiving a reference clock; a control circuit arranged for generating a control signal to selectively configure the clock and data recovery to operate in one of a plurality of phases; a detective circuit arranged for generating a first adjusting signal while the clock and data recovery operates in a frequency locking phase, and for generating a second adjusting signal while the clock and data recovery circuit operates in a clock and data recovery phase; and a controllable oscillator arranged for generating a recovered clock according to the first adjusting signal in the frequency locking phase, and for generating the recovered clock according to the second adjusting signal in the clock and data recovery phase.

Abstract: A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.

Abstract: A transceiver is described. The transceiver includes a first injection-locked oscillator and a second injection-locked oscillator. The transceiver also includes a first phase-locked loop coupled with the first injection-locked oscillator. The first phase-locked loop is configured to generate a first frequency reference. Further, the transceiver includes a second phase-locked loop coupled the second injection-locked oscillator. The second phase-locked loop is configured to generate a second frequency reference. The transceiver includes a mixer configured to receive the first phase-locked loop output and configured to receive said second injection-locked oscillator output. The mixer is also configured to generate a carrier frequency signal based on the first injection-locked oscillator output and the second injection-locked oscillator output. And, the transceiver includes a modulator configured to receive said carrier frequency signal.

Abstract: The present disclosure provides a method of carrier phase error removal associated with an optical communication signal. The method includes estimating and removing a first phase angle associated with an information signal using coarse phase recovery, the information symbol being associated with a digital signal, the digital signal representing the optical communication signal; estimating a carrier frequency offset between a receiver light source and a transmitter light source by using the estimated first phase angle, the carrier frequency offset being associated with the information signal; removing carrier phase error associated with the carrier frequency offset; and estimating and removing a second phase angle associated with the information signal, the estimated second phase angle being based on the estimated first phase angle and the estimated carrier frequency offset.

Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.

Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

Abstract: The present disclosure provides an auto-determining sampling frequency method. The method is for determining sampling frequency for an input signal of a single wire transmission interface. Each frame of the input signal includes a preamble and binary data presented in a plurality of bits. The method includes utilizing an internal sampling clock to acquire a plurality of period widths of the preamble and the binary data in the input signal and determining range of the sampling frequency according to the detected period widths of the preamble and the binary data.

Abstract: A mixer for the elimination of harmonic mixing in signal transmission is presented. The mixer incorporates a mixing unit and a modulation output unit. The mixing unit receives an input signal and a modulated signal, and outputs an output signal after signal mixing. The modulation output unit is for the generation of modulated signals, which are usually pulse-width modulated. The modulation output unit includes a delta sigma modulator and a digital domain code generator. The delta sigma modulator outputs the modulated signal responding to the received oscillation signal and digital domain code, the digital domain code generator generates the digital domain code in order to provide digital domain sine wave code for the use of the delta sigma modulator. The oscillation signal may be a signal of constant hi-frequency, or a signal that has a frequency larger or equal to that of the input signal by an integer factor.

Abstract: A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal.

Abstract: One bit is a smallest increment of binary measurement in first and second digital values. The first digital value is converted into a first analog signal. The second digital value is converted into a second analog signal. The first analog signal is augmented by a first amount that equates to less than the smallest increment of binary measurement, so that the augmented first analog signal by definition does not equal the second analog signal. The second analog signal is augmented by a second amount that equates to less than the smallest increment of binary measurement, so that the augmented second analog signal by definition does not equal the first analog signal. The augmented first analog signal is compared to the second analog signal, and a first signal is output in response thereto. The augmented second analog signal is compared to the first analog signal, and a second signal is output in response thereto.

Abstract: Navigation satellite receivers have a large number of channels, where phase discriminators and loop filter of a PLL operate in phase, with data bits and control of numerically controlled oscillator (NCO) carried out simultaneously on all channels. Since symbol boundaries for different satellites do not match, there is a variable time delay between the generation of control signals and NCO control time. This delay may be measured by counting a number of samples in the delay interval. A proposed system measures non-energy parameters of the BPSK signal carrier received in additive mixture with noise when a digital loop filter of PLL controls NCO with a constant or changing in time delay. A control unit controls bandwidth and a LF order by changing transfer coefficients based on analyzing estimated signal parameters and phase tracking error at a PD output.

Abstract: Apparatuses, systems, and methods are directed to maintaining optimal carrier tracking performance in view of operating conditions that prevail. Such configurations employ a phase lock loop that configured to generate an estimated phase error value, a variance module configured to calculate a phase noise variance based on the estimated phase error value, and a loop control bandwidth module that calculates a loop bandwidth value based on a detected lower phase noise variance, generates modified loop filter values in accordance with the calculated loop bandwidth value, and updates the phase lock loop with the modified loop filter values. During subsequent iterations, the modified loop filter values are incrementally adjusted along a particular direction until the phase noise variance increases at which point the modified loop filter values are incrementally adjusted in an opposite direction to converge on an optimal loop bandwidth value.

Abstract: An ultra low power radio receiver architecture based on phase locked loop is provided. Embodiments of an ultra low power radio receiver architecture based on phase locked loop can detect a complex modulated MSK signal with only a single path receiver chain. According to an embodiment of the present invention, the overall power consumption of the radio receiver in the present invention can be reduced by almost fifty percent compared to that of the conventional complex path radio receiver architecture. The radio receiver architecture of the invention is suitable for the ultra low power radio application such as wireless sensor networks (WSN).

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract: In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.

Abstract: A method for wireless data communication between a wireless device having means for short-range data communication, and an electronic device includes mounting a data communication device having means for short-range radio frequency wireless data communication in a general purpose expansion memory location of the electronic device, activating a short-range radio frequency wireless data communication link between the wireless device and the data communication device, and transmitting data between the electronic device and the wireless device so that the wireless device operates as an ordinary expansion memory from the view point of the electronic device.

Abstract: To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided. A/D converter 2 samples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSP 3 demodulates the digital signal converted by A/D converter 2 and computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuit 4 extracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuit 5 adjusts the phase of the clock signal extracted by sampling clock extraction circuit 4 to the phase computed by DSP 3 and generates a clock signal having the adjusted phase as the sampling clock signal.

Abstract: To reduce the time of reception operation switching between multiple wireless systems, a semiconductor integrated circuit includes a first reception unit including a first analog reception unit and a first digital reception unit, and a digital interface. The first analog reception unit includes a first reception mixer and a first A/D converter, and the first digital reception unit includes a first digital filter. The first reception unit, an oscillator, and a PLL enable switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second RF reception signal of a second system. In a period of an end transition operation of the first digital reception unit in the switching, the PLL starts a lock operation so as to match a frequency of an oscillation output signal generated from the oscillator to a desired frequency of the second system.

Abstract: A method of accelerated carrier signal acquisition for a digital communication receiver, the method comprising receiving a carrier signal by a receiver comprising a carrier recovery loop (CRL), setting the CRL to an open loop setting using a processor, setting a numerically controlled oscillator (NCO) within the CRL at a center frequency of the NCO, determining, by the processor, one or more initial parameters of the CRL, calculating an estimate and polarity for a sign frequency detection frequency using a sign frequency detector while simultaneously estimating a Fast Fourier Transform (FFT) frequency by running an FFT using the processor, comparing polarities of the estimates of the sign frequency detection frequency and FFT frequency and determining a frequency offset using the processor, and adjusting one or more parameters of the CRL based on the frequency offset using the processor.

Abstract: A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.

Abstract: Methods and apparatuses for compensating for frequency mismatch between a base station and mobile station are disclosed. At a first oscillator, a fixed reference oscillation signal is generated. At a second oscillator, a baseband oscillation signal is generated. A frequency divided version of the baseband oscillation signal is locked to a frequency divided version of the first reference oscillation signal. At a third oscillator, a first RF oscillation signal is generated. A frequency divided version of the first RF oscillation signal is locked to the frequency divided version of the second reference oscillation signal. A frequency adjustment signal is inputted to the second and third oscillators. At the second and third oscillators, frequency errors of the baseband oscillation signal and first RF oscillation signal, respectively, are compensated based on the frequency adjustment signal.

Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

Abstract: A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio.

Abstract: An integrated circuit is described. The integrated circuit includes a global positioning system core that generates a GPS clock signal using an inductor-capacitor voltage controlled oscillator. The integrated circuit also includes a transceiver core configured to use the GPS clock signal. The transceiver core may not include a voltage controlled oscillator.

Abstract: Compressing a variable phase component of a received modulated signal with a second harmonic injection locking oscillator, and generating a delayed phase-compressed signal with a fundamental injection locking oscillator, and combining the phase-compressed signal and the delayed phase-compressed signal to obtain an estimated derivative of the variable phase component, and further processing the estimated derivative to recover data contained within the received modulated signal.

Abstract: The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.

Abstract: Systems and methods are disclosed for feeder link configurations to layered modulation. One feeder link system employs feeder link spot beam to antennas in distinct coverage areas to enable frequency reuse. Another system employs narrow beam width feeder link antenna to illuminate individual satellites also enabling frequency reuse. Yet another system uses layered modulation in the feeder link. Another feeder link system employs a higher order synchronous modulation for the satellite feeder link than is used in the layered modulation downlink signals.

Abstract: A frequency detector includes a multi-phase clock generation unit, a sampling unit connected to the multi-phase clock generation unit and a digital logic unit connected to the sampling unit. An inputted single-phase clock is received by the multi-phase clock generation unit and transformed into a multi-phase clock. Inputted random data are received by the sampling unit and sampled by the multi-phase clock. Each data bit of the random data is divided into several sampling intervals according to a phase number of the multi-phase clock. The digital logic unit analyzes sampling values logically, judges the corresponding sampling interval of each sampling value and outputs signals for indicating that a frequency of the random data is higher or lower than the frequency of the single-phase clock based on differences in the corresponding sampling intervals of the sampling values at two adjacent times. A method for detecting frequencies is further provided.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: The present invention aims at eliminating the effects of frequency offsets between two transceivers by adjusting frequencies used during transmission. In this invention, methods for correcting the carrier frequency and the sampling frequency during transmission are provided, including both digital and analog implementations of such methods. The receiver determines the relative frequency offset between the transmitter and the receiver, and uses this information to correct this offset when the receiver transmits its data to the original transmitter in the return path, so that the signal received by the original transmitter is in sampling and carrier frequency lock with the original transmitter's local frequency reference.

Abstract: A signal demodulation module is disclosed. The signal demodulation module includes an injection-locked oscillator, an envelope detector and a data slicer. The injection-locked oscillator has a central oscillating frequency equal to a frequency of a digital modulation signal received, and outputs a phase-locked oscillating signal which is in phase to the digital modulation signal. When input phase of the digital modulation signal changes, output phase of the injection-locked oscillator changes synchronously. The envelope detector is used for detecting an envelope line of the phase-locked oscillating signal and outputting an envelope signal accordingly. The data slicer is used for receiving the envelop signal and outputting a first digital signal according to a reference voltage and the envelop signal.

Abstract: A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal.

Abstract: Techniques, apparatuses and systems for providing communications based on time reversal of a channel impulse response of a pulse in a transmission channel between a transmitter and a receiver to enhance reception and detection of a pulse at the receiver against various effects that can adversely affect and complicate the reception and detection of the pulse at the receiver.

Abstract: The communications device includes a phase and frequency tracking loop having a signal input and an adjustable loop filter that establishes a predetermined tracking loop bandwidth for samples of communication signals received at the signal input and processed within the tracking loop. A tracking loop update circuit updates loop filter operating parameters and is operative with the loop filter for increasing or decreasing the tracking loop bandwidth of the phase and frequency tracking loop based on the dynamics of the frequency offset of measured samples from the output of the loop filter over time.

Abstract: A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.

Abstract: Briefly, in accordance with one or more embodiments, in response to receiving a single carrier signal that is not phase locked, channel equalization may be applied to the signal via a channel equalizer. The equalized signal may be phase averaged to provide a signal that is at least partially phase stabilized. The channel equalizer may then be trained by feeding back the at least partially phase stabilized phase reference to the channel equalizer. The resulting signal may then be decoded via coherent or quasi-coherent detection.

Abstract: An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.

Abstract: A phase-locking loop (PLL) for use with orthogonal frequency division multiplexed signals. In one embodiment, a wireless receiver includes a PLL is configured to reduce phase and frequency divergence between the wireless receiver and a transmitter of a packet received by the wireless receiver. The PLL includes a loop bandwidth controller. The loop bandwidth controller is configured to set a bandwidth of the PLL to a first value for reception of an initial symbol of the packet. The loop bandwidth controller is configured to reduce the bandwidth of the PLL over a number of symbols preceding an initial header of the packet.

Abstract: A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

Abstract: A digital signal transmitter in which multiple data streams are each transmitted by modulation of a respective frequency band within one of a group of frequency channels, the frequency bands each occupying no more than a predetermined maximum bandwidth less than or equal to the channel width; comprises means for transmitting at respective frequency positions within each frequency channel, one or more instances of band information defining the frequency bands corresponding to all of the data streams carried within that frequency channel, the one or more instances being arranged so that any portion of the frequency channel equal in extent to the predetermined maximum bandwidth includes at least one instance of the band information.

Abstract: A device comprises a transmitter, a receiver and a clock generator that generates a clock signal having a local clock phase. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from a host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the local clock phase and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset.

Abstract: A method of embedding information within a burst carrier signal, the method comprising modulating meta-data using a modulator such that a meta-carrier signal results, lowering a Power Spectral Density (PSD) of the meta-carrier signal by Direct Sequence Spread Spectrum (DSSS) chipping the meta-carrier signal using a linear Pseudo-Random Number (PRN) sequence, embedding one or more modulated symbols of the meta-carrier signal within an unused portion of one or more quadrants of a modulation constellation of a burst carrier signal such that a composite carrier signal results, and synchronously transmitting the composite carrier signal using a transmitter such that symbols of the meta-carrier signal are synchronized with symbols of the burst carrier signal.

Abstract: Disclosed herein is a synchronizing circuit including: a first PLL circuit; a second PLL circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; a control circuit; and a holding section.