Including Switching Or Gating (digital Circuits) Patents (Class 375/328)
  • Patent number: 9860093
    Abstract: A communications adaptor comprises a receiver circuit, which can comprise a signal input configured to receive a frequency shift keyed (FSK) signal; a delay circuit in communication with the signal input and including a delayed signal output; a multiplier circuit in communication with the signal input and the delayed signal output, and the multiplier circuit can be configured to produce a serial bit steam from at least the signal input and the delayed signal output, the serial bit stream corresponds to one or more bits encoded with frequency shift keying in the FSK signal; and a signal output configured to output the serial bit stream. The communications adaptor also can comprise a transmitter circuit and a processor in communication with the receiver circuit and the transmitter circuit.
    Type: Grant
    Filed: March 19, 2011
    Date of Patent: January 2, 2018
    Assignee: PEPPER+FUCHS GMBH
    Inventors: Kenneth Burns, Kenneth Malecek
  • Patent number: 9281816
    Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.
    Type: Grant
    Filed: December 22, 2012
    Date of Patent: March 8, 2016
    Assignee: Rambus Inc.
    Inventors: Amir Amirkhany, Farshid Aryanfar, Ravindranath Kollipara, Xingchao (Chuck) Yuan
  • Patent number: 9094017
    Abstract: An arrangement is described in which phase parity or phase opposition between two signals can be determined, and if necessary remedial action may be taken.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: July 28, 2015
    Assignee: Sequans Communications Ltd.
    Inventors: Jackson Harvey, Peter Martin
  • Patent number: 9049732
    Abstract: A terminal (10) includes elements for transmitting data towards a station (20) in the form of radio signals, the radio signals being transmitted using a frequency resource (MC) shared between a plurality of terminals (10), characterized in that the terminal is configured to emit radio signals, the instantaneous frequency spectrum of which has a bandwidth (TOB) that is significantly lower than a frequency drift of a frequency synthesis unit of the terminal. Also disclosed are a method for using a frequency resource, a method for manufacturing terminals (10) and a telecommunication system (1).
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 2, 2015
    Assignee: SIGFOX
    Inventors: Christophe Fourtet, Thierry Bailleul
  • Patent number: 9036727
    Abstract: A precoding codebook matrix/vector of length 2L is generated by the selection of two matrices/vectors, each from one of a predetermined set of L×L matrices and multiplying each column of one of the matrices/vectors by a complex coefficient.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: May 19, 2015
    Assignee: Koninklijke Philips N.V.
    Inventors: Milos Tesanovic, Timothy James Moulsley, Choo Chiap Chiau
  • Patent number: 9031167
    Abstract: A receiver is described. The receiver includes a filter configured to receive a quadrature phase shift keying (“QPSK”) signal. Further, the receiver includes an amplifier coupled with the filter. And, a QPSK decomposition filter is coupled with the amplifier. The QPSK decomposition filter is configured to generate a first BPSK signal based on the QPSK signal and a second BPSK signal based on the QPSK signal.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: May 12, 2015
    Assignee: Innophase Inc.
    Inventor: Yang Xu
  • Patent number: 8842787
    Abstract: A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: September 23, 2014
    Assignee: Marvell International Ltd.
    Inventors: King Chun Tsai, Patrick Clement, David Cousinard
  • Patent number: 8837288
    Abstract: A flow-based network switching system includes a memory having a flow table and a packet processor coupled to the memory. The packet processor includes a user-programmable flow-based rule storage that includes a plurality of flow-based rules. A flow-based handler and session manager in the packet processor is operable to retrieve application layer metadata from a first packet received over a network, determine a first flow session associated with the first packet using the application layer metadata from the first packet and the flow table, and retrieve at least one of the plurality of flow-based rules from the programmable flow-based rule storage using the application layer metadata from the first packet. A flow-based rule processing engine in the packet processor is operable to apply the at least one flow-based rule to the first packet. Packets with applied flow-based rules are forwarded through the network.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: September 16, 2014
    Assignee: Dell Products L.P.
    Inventors: Rabah S. Hamdi, Saikrishna M. Kotha
  • Patent number: 8805680
    Abstract: Provided are a method and an apparatus for encoding and decoding an audio signal. A method for encoding an audio signal includes receiving a transformed audio signal, dividing the transformed audio signal into a plurality of subbands, performing a first sinusoidal pulse coding operation on the subbands, determining a performance region of a second sinusoidal pulse coding operation among the subbands on the basis of coding information of the first sinusoidal pulse coding operation, and performing the second sinusoidal pulse coding operation on the determined performance region, wherein the first sinusoidal pulse coding operation is performed variably according to the coding information. Accordingly, it is possible to further improve the quality of a synthesized signal by considering the sinusoidal pulse coding of a lower layer when encoding or decoding an audio signal in an upper layer by a layered sinusoidal pulse coding scheme.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: August 12, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Mi-Suk Lee, Heesik Yang, Hyun-Woo Kim, Jongmo Sung, Hyun-Joo Bae, Byung-Sun Lee
  • Patent number: 8744014
    Abstract: A FFR (fractional frequency reuse)-based network MIMO (multiple-input multiple-output) transmission architecture in a cellular system that employs cell sectoring using directional antennas. Each cell is sectorized into three outer sectors using three directional antennas which transmit in three different directions using three different frequency subbands. The cell sectors are arranged based on a frequency partition scheme so that three sectors in three neighboring cells form a coordinated group for network MIMO transmission. A regular and a rearranged frequency partition are described. Further, a practical implementation of SON (self organizing network)-based three-cell FFR-based network MIMO for a wireless OFDM system is described.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: June 3, 2014
    Assignee: Mediatek Inc.
    Inventors: Chu-Jung Yeh, Li-Chun Wang, I-Kang Fu
  • Publication number: 20140140445
    Abstract: An apparatus and method for demodulation of FSK signals are provided. Digital pulses of the FSK signals can be processed to detect digital data contained in the FSK frequencies by converting the FSK frequencies from a frequency signal to a digital logic signal and vice versa.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: Honeywell International Inc.
    Inventors: Harvinder Singh, Abdul Hakim, Srikanth K.S, Harinath Babu M R
  • Patent number: 8705602
    Abstract: Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: April 22, 2014
    Assignee: Altera Corporation
    Inventors: Weiqi Ding, Mengchi Liu, Mingde Pan, Thungoc M. Tran, Sergey Shumarayev
  • Patent number: 8503578
    Abstract: A method of processing first and second corresponding signals having a delay therebetween. The method includes introducing a plurality of different delays between the first and second signals, successive delay amounts differing from each other by less than the interval between chip boundaries, and for each introduced delay, summing samples of the second signal which are obtained at the times of, at least, chip boundaries between bits of the first signal which have the same state, to obtain a value; thereby to obtain a representation of how the value varies according to the introduced delay, which representation contains a level change associated with an introduced delay which bears a predetermined relationship to the delay between the first and second signals.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: August 6, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Nongji Chen
  • Publication number: 20130195224
    Abstract: A receiver is described. The receiver includes a filter configured to receive a quadrature phase shift keying (“QPSK”) signal. Further, the receiver includes an amplifier coupled with the filter. And, a QPSK decomposition filter is coupled with the amplifier. The QPSK decomposition filter is configured to generate a first BPSK signal based on the QPSK signal and a second BPSK signal based on the QPSK signal.
    Type: Application
    Filed: January 30, 2013
    Publication date: August 1, 2013
    Applicant: Innophase Inc.
    Inventor: Innophase Inc.
  • Patent number: 8462887
    Abstract: A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: June 11, 2013
    Assignee: Marvell International Ltd.
    Inventors: King Chun Tsai, Patrick Clement, David Cousinard
  • Patent number: 8457223
    Abstract: A wireless communication device is provided that includes: a plurality of receiving portions that respectively receive wireless signals that are transmitted based on frequency-use methods set from among a plurality of frequency-use methods; and a setting portion that sets one of the plurality of frequency-use methods on each of the plurality of receiving portions respectively. The setting portion changes the frequency-use method of the plurality of receiving portions, based on a receiving result of a wireless signal in each of the plurality of receiving portions.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: June 4, 2013
    Assignee: Sony Corporation
    Inventor: Shigeru Sugaya
  • Patent number: 8325853
    Abstract: Embodiments of the present invention relate to a system for clock synthesis or data timing recovery. No analog continuous time oscillator is required, all the building blocks of a Frequency Locked Loop/Phase Locked Loop belonging in the digital discrete time domain. From a system-level perspective, the system is characterized by its strong non-linear behavior due to the intrinsic nature of some building blocks. This inherent non-linearity is responsible for some unusual, attractive property of the complete system. The system is able to multiply the input frequency clock by an arbitrarily large factor, ensuring in any case the convergence of the algorithm in two reference clock cycles.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: December 4, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventor: Carmelo Burgio
  • Patent number: 8311176
    Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: November 13, 2012
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Thomas H. Greer, III, Jade M. Kizer, Brian S. Leibowitz, Mark A. Horowitz
  • Patent number: 8311158
    Abstract: A receiver circuit includes an LPF configured to remove an interference signal and/or a noise from a received signal, an ADC configured to digitize a signal output from the LPF, an FIR filter configured to further remove an interference signal and/or a noise from the signal output from the ADC and compensate imperfection in in-band characteristics caused in the LPF, a delay circuit configured to delay the signal output from the ADC by a predetermined time period, and a control circuit configured to control a destination of the signal output from the ADC, wherein the control circuit switches the destination of the signal output from the ADC to one of the FIR filter and the delay circuit according to a predetermined condition.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: November 13, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yoshida, Kazumi Sato, Takehiko Toyoda
  • Patent number: 8300681
    Abstract: A frequency translation system includes first and second translational switches, and a signal bus coupled therebetween. The first translational switch includes one or more inputs configured to receive a respective one or more first input signals, a first plurality of outputs, and a second plurality of outputs. The second translational switch includes one or more inputs configured to receive a respective one or more second input signals, a first output, and a second output. The signal bus, coupled between the first and second translational switches, includes (i) a first bus line coupled to a first one of the first plurality of outputs of the first translational switch, and to the first output of the second translational switch, and (ii) a second bus line coupled to a first one of the second plurality of outputs of the first translational switch, and to the second output of the second translational switch.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: October 30, 2012
    Assignee: R.F. Magic, Inc.
    Inventors: Branislav Petrovic, Keith Bargroff, Jeremy Goldblatt
  • Patent number: 8238497
    Abstract: A device (1) for reducing the interference in a received communication signal. The device includes: an adaptive filter (2) which uses a self-reference signal to remove a coherent and stable interfering signal from the received communication signal; a detection module (3) for detecting the existence of the target signal among the received communication signals; and a demodulation module (7) for demodulating the received communication signal when the target signal is detected. Further, this device includes: a noise-classifying device (5) which detects various interfering signals of the received communication signal and determines the classification of the detected interfering signals; and a switching module (6) for selecting the input signal for the demodulation module on the basis of the determination made by the noise-classifying device and the value when the existence of the target signal is detected.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: August 7, 2012
    Assignee: Aisin Seiki Kabushiki Kaisha
    Inventor: Abderrahman Essebbar
  • Patent number: 8229037
    Abstract: A system, method, and apparatus for a multiple data rate communication system is presented herein. The communication system receives data samples that are either sampled at a narrowband rate or a wideband rate and provides various functions and services, such as echo cancellation, DTMF detection and generation, and call discrimination. For wideband signals, a down-sampled signal is provided for each of the foregoing function and service. The output of the function or services is then recombined with the wideband signal.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: July 24, 2012
    Assignee: Broadcom Corporation
    Inventors: Wilf LeBlanc, Phil Houghton, Kenneth Cheung
  • Patent number: 8224281
    Abstract: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal, and applications thereof are described herein. Reducing or eliminating DC offset voltages and re-radiation generated when down-converting an electromagnetic (EM) signal is also described herein. Down-converting a signal and improving receiver dynamic range is also described herein.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 17, 2012
    Assignee: ParkerVision, Inc.
    Inventors: David F. Sorrells, Michael J. Bultman, Robert W. Cook, Jonathan S. Jensen, Martin R. Johnson, Richard C. Looke, Charley D. Moses, Jr., Gregory S. Rawlins, Michael W. Rawlins, Robert T. Short, Jamison L. Young
  • Publication number: 20120163429
    Abstract: The Application is directed at arrangements at which switch mode power converters share a common load. More particularly, the application provides a masterless arrangement in which no single converter controls the operation of the other converters. This is achieved by an arrangement in which each converter attempts to share its current measurement with other converters through an arbitration scheme employed on a data line, with the winning converter providing a defacto current measurement; for example, a maximum or minimum, to the overall arrangement.
    Type: Application
    Filed: June 15, 2010
    Publication date: June 28, 2012
    Inventors: Karl Rinne, Anthony Kelly, Eamon O'Malley
  • Patent number: 8208590
    Abstract: Filter circuit includes Nth-order active filters switching circuit which switches shorting or non-shorting of active filter, and power-supply control circuit which controls such that a power supply of active filter is turned off when switching circuit shorts active filter. A receiver employing filter circuit turns off the power supply of active filter not needed when no interference wave exists within a given range from a desired frequency band. The foregoing structure allows lowering the power consumption of filter circuit.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: June 26, 2012
    Assignee: Panasonic Corporation
    Inventors: Eiji Okada, Takeshi Fujii, Hiroaki Ozeki
  • Patent number: 8150355
    Abstract: There is provided a method that comprises identifying a parasitic signal transfer in a filter using a signal-directed graph; and adding compensation paths to the filter to reduce or eliminate the effect of the parasitic signal transfer A corresponding filter is provided which comprises a plurality of amplifier stages that generate one or more filter poles; at least one component coupled to at least one of the amplifier stages, the component causing a parasitic effect in the filter; and means for applying a compensation current to the at least one amplifier stage to reduce or eliminate the parasitic effect.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: April 3, 2012
    Assignee: NXP B.V.
    Inventor: Hendrikus C. Nauta
  • Patent number: 8149908
    Abstract: A device for generating a modulation signal for an RF pulse transmitter is disclosed. The device includes a detector, a video amplifier, an analog processing device, and a modulation signal generating device. The modulation signal generating device is configured to receive an information cue from the analog processing device and to output the modulation signal. The modulation signal generating device includes a digital processing device and a signal generating device. The digital processing device is configured to receive a transmission synchro signal and the information cue and to generate a first control signal and a second control signal. The signal generating device is configured to generate a variable-amplitude Gaussian-shaped signal in response to the first control signal, to generate a variable-amplitude square-shaped signal in response to the second control signal, and to generate the modulation signal according to the Gaussian-shaped signal and the square-shaped signal.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: April 3, 2012
    Assignee: Thales
    Inventor: Alain Letemplier
  • Patent number: 8131242
    Abstract: A system and method for implementing an IQ generator includes a master latch that generates an I signal in response to a clock input signal, and a slave latch that generates a Q signal in response to an inverted clock input signal. A master selector is configured to provide a communication path from the master latch to the slave latch, and a slave selector is configured to provide a feedback path from the slave latch to the master latch. The foregoing I and Q signals are output directly from the respective master and slave latches without any intervening electronic circuitry.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: March 6, 2012
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Derek Mellor, Bernard J. Griffiths, Frank E. Hayden
  • Patent number: 8130874
    Abstract: The invention relates to an arrangement for bypassing a low noise amplifier unit in the front stage of a radio receiver, especially intended for the base stations of mobile communication networks. The front stage includes, in succession, a divider (420), an amplifier unit (430) comprising two parallel, low noise amplifier branches, and a first combiner (450). The by-pass arrangement includes a second combiner (443), by which the halves (E11, E12) of the received signal are combined immediately after the divider before the amplification. A change-over switch (SW) is then used to select either the signal that has propagated through the amplifier unit and then combined (G·E1) or the signal (E1?) that has been directly combined as the output signal of the front stage. Due to the invention, the noise figure of the front stage is improved and the integration of its structure is facilitated.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: March 6, 2012
    Assignee: Powerwave Comtek Oy
    Inventor: Mika Niemi
  • Patent number: 8098718
    Abstract: A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: January 17, 2012
    Assignee: Qualcomm Incorporated
    Inventors: Matthew D. Sienko, Joseph G. Hamilton, Iain W. Finlay
  • Patent number: 8054924
    Abstract: A data transmission method with phase shift error correction comprising: transmitting through a network a transmission signal, wherein the transmission signal comprises a reference signal component having a predetermined frequency and a data signal component; receiving the transmission signal, wherein the received transmission signal includes a phase shift error caused by the network, wherein the phase shift error is in both the received reference signal component and the received data signal component; generating a multiplier signal at a receiver having the predetermined reference frequency; using the multiplier signal to determine the phase shift error in the received transmission signal; and correcting the received data signal component using the determined phase shift error.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: November 8, 2011
    Assignee: General Motors LLC
    Inventor: Sethu K. Madhavan
  • Patent number: 8045626
    Abstract: According to one embodiment of the present invention, it is possible to realize a signal transmitter which is capable of reducing power consumption and which can be easily designed. A differential transmitter block outputs differential output signals fixed to a predetermined logic signal to a differential receiver block and disconnects terminating resistors from a signal transmission path in an idle state. In the differential receiver block, a differential comparator outputs a logic determined by symbols of the differential output signal from the differential transmitter block, and an operating state detector detects the idle state upon detection that time successively outputting a predetermined logic by the differential comparator reaches a predetermined time, and controls switches so as to disconnect the terminating resistors from the signal transmitter in the receiving side upon detection of the idle state.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Tadashi Iwasaki
  • Patent number: 8009725
    Abstract: A translational switch system includes first and second translational switches, and a signal bus coupled therebetween. The first translational switch includes one or more inputs configured to receive a respective one or more first input signals, a first plurality of outputs, and a second plurality of outputs. The second translational switch includes one or more inputs configured to receive a respective one or more second input signals, a first output, and a second output. The signal bus, coupled between the first and second translational switches, includes (i) a first bus line coupled to a first one of the first plurality of outputs of the first translational switch, and to the first output of the second translational switch, and (ii) a second bus line coupled to a first one of the second plurality of outputs of the first translational switch, and to the second output of the second translational switch.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: August 30, 2011
    Assignee: RF Magic, Inc.
    Inventors: Branislav Petrovic, Keith Bargroff, Jeremy Goldblatt
  • Patent number: 7992067
    Abstract: Methods and apparatus for coding a digital data string to represent a sequence of acoustic frequencies to be transmitted as an acoustic signal by a genuine acoustic authentication device; related to providing for improving the rate of successfully detecting a valid data string contained in the acoustic signal transmitted by the device. Each of a plurality of groups of bits of the data string are coded to represent a respective frequency value set of one or more acoustic frequencies to be transmitted acoustically to represent the respective group of bits. The number of acoustic frequencies in a frequency value set is less than the number of bits in the respective group of bits that the frequency value set represents. For each of the plurality of groups of bits of the data string, the respective frequency value set is selected according to a predetermined frequency assignation pattern that provides for probabilistic transition coding used for error correction of the acoustic signal.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: August 2, 2011
    Assignee: Identita Technologies International SRL
    Inventors: Yannick Le Devehat, David Perron, Olivier Fraysse, Pierre Dumouchel, Rene Landry, Jr., Francois Rivest
  • Patent number: 7944246
    Abstract: A full-wave rectifier circuit receives complementary signals and produces a current corresponding to an added value of differential signals at different levels. A voltage comparator performs a comparison between output signals produced and subjected to current addition and voltage conversion by the full-wave rectifier circuit. A timer detects whether an output signal of the voltage comparator is kept in the same state for a predetermined time or more, and produces a signal indicating a result of the detection. A signal detecting circuit that can accurately identify a state of digital signals of a minute amplitude transferred through a pair of complementary signal lines is achieved without complicating manufacturing steps.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: May 17, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hideki Uchiki
  • Patent number: 7894558
    Abstract: A receiver circuit controls a power source of a front-end circuit and a demodulator using a first power source control signal. Upon receiving data of a plurality of receiving slots having a guard bit provided between receiving slots adjacent to each other, the first power source control signal becomes a power source ON signal before starting receiving of the data, then becomes a power source OFF signal within the guard bit, and becomes a power source OFF signal after completing the receiving of the data. The receiver circuit controls a power source of an active filter circuit using a second power source control signal, which becomes a power source OFF signal after completing the receiving of the data after becoming a power source ON signal before starting the receiving of the data.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: February 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Mamoru Nishimura, Koji Takahashi, Satoshi Yamaguchi, Tetsurou Yokota
  • Patent number: 7894789
    Abstract: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal, and applications thereof are described herein. Reducing or eliminating DC offset voltages and re-radiation generated when down-converting an electromagnetic (EM) signal is also described herein. Down-converting a signal and improving receiver dynamic range is also described herein.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: February 22, 2011
    Assignee: ParkerVision, Inc.
    Inventors: David F. Sorrells, Michael J. Bultman, Robert W. Cook, Jonathan S. Jensen, Martin R. Johnson, Richard C. Looke, Charley D. Moses, Jr., Gregory S. Rawlins, Michael W. Rawlins, Robert T. Short, Jamison L. Young
  • Patent number: 7860172
    Abstract: A k-to-2k decoder is provided. Within the final stage of a k-to-2k decoder is a plurality of word line drivers. These word line drivers utilize clocking signals to fire word lines to a memory array. However, power consumption by clocks has become a serious issue with the increase component density on silicon wafers. To alleviate the problem, signals from the first stage of the k-to-2k decoder provide enablement signals to Local Clock Buffers (LCBs) that allow the word line drivers to fire. The enablement signal reduces the number of active buffers and signals carried to word line drivers, reducing power consumption.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chad Adams, Toru Asano, Andrew Maust
  • Patent number: 7835469
    Abstract: There is provided a receiver comprising: a control unit for controlling the functions of the receiver; a receiving unit for receiving data signals and timing signals; and a digitally controlled delay line unit connected to the receiving unit and to the control unit. The control unit is configured to measure several samples of the received data signal and the timing signal, to determine average values of the several measured samples of the data signal and the timing signal for defining compensation values, and the digitally controlled delay line unit is configured to adjust the number of unit delay elements for compensating for skew between the data signal and the timing signal on the basis of the defined compensation values.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: November 16, 2010
    Assignee: Nokia Corporation
    Inventor: Marko Pessa
  • Patent number: 7782929
    Abstract: A method and apparatus for receiving one of a plurality of Ethernet transmission protocol signals is disclosed. Each transmission protocol signal includes a plurality of transmission signal streams. The method includes determining which of the transmission protocol signals is being received. An analog front-end processor is connected to one of a plurality of protocol digital processors based on the transmission protocol signal being received. A setting of at least one functional parameter of the analog front-end processor and/or the protocol digital processors is selected based on the transmission protocol signal being received. A sampling rate of the analog front-end processor and/or a processing rate of the protocol digital processors are selected based on the transmission protocol signal being received. The plurality of transmission signal streams of the transmission protocol signal being received by the analog front-end processor are ADC sampled based on a shared clock source.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: August 24, 2010
    Assignee: Teranetics, Inc.
    Inventors: Dimitry Taich, Jose Tellado
  • Patent number: 7773945
    Abstract: An RFID reader analog front end architecture employs multiplexed use of a single analog to digital converter in order to digitize the inphase and quadrature components of the incoming signal from the reader's receiving antenna. The Type 1 architecture includes an analog I/Q switch that controls which of the baseband signals will be digitized by a single Analog to Digital Converter. In the Type 2 architecture, the I/Q switch is moved so that it is directly adjacent to the receive mixers, requiring only one antialiasing filter block and gain block. In the Type 3 architecture, one mixer and its associated filtering chain are eliminated. The Type 4 architecture provides for selection of transmitter phase basis by means of an I/Q switch operating under control of the DSP that phase-shifts the transmitter with respect to the receiver.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: August 10, 2010
    Assignee: Thingmagic, Inc.
    Inventor: Matthew Stephen Reynolds
  • Patent number: 7697902
    Abstract: A control signal is wirelessly transmitted from a first radio communication unit of a portable communication device to a second radio communication unit. The portable communication device is provided for radio communication over a first radio frequency band using a first modulation technique. The control signal is transmitted by generating a control signal, switching off the first modulation of a carrier signal, shifting the frequency of the carrier signal from a first radio frequency band to a second radio frequency band for the first radio communication unit, switching on the second modulation of the carrier signal having a frequency within the second radio frequency band, wherein the carrier signal is modulated with the control signal, and transmitting the control signal modulated carrier signal wirelessly over the second radio frequency band to the second radio communication unit.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: April 13, 2010
    Assignee: Sony Ericsson Mobile Communications AB
    Inventor: Paul Johansson
  • Patent number: 7653167
    Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: January 26, 2010
    Assignee: Intel Corporation
    Inventors: Hongjiang Song, Tofayel Ahmed
  • Patent number: 7627057
    Abstract: The present invention, takes advantage of the properties of quadrature signals to achieve precise quadrature alignment in a simple fashion. The expectation of the product of quadrature signals is zero. A phase error detection network therefore operates by multiplying the received quadrature signals and low-pass filtering the product to produce an error signal. When the signals are in precise quadrature relationship, the error signal will be zero. Real-time feedback control may be used to drive the error to zero. In accordance with another aspect of the invention, a variable phase shift network is achieved using a dual delay line. The difference in delay between the two delay lines is adjusted in response to the error signal to obtain precise quadrature alignment. The principles of the invention may be applied in connection with traditional mixer architectures or with switch-mode architectures.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: December 1, 2009
    Assignee: Panasonic Corporation
    Inventor: Earl W. McCune, Jr.
  • Patent number: 7627291
    Abstract: An integrated circuit operable to wirelessly communicate with other devices by utilizing a radio transceiver and a routing element is disclosed. The routing element is operable to route a signal between various circuit elements and is selectively operable to function as an antenna when coupled with the radio transceiver.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: December 1, 2009
    Assignee: XILINX, Inc.
    Inventors: Philip B. James-Roxby, Daniel J. Downs
  • Patent number: 7555051
    Abstract: A quadrature transmitter and receiver have configurable I and Q channel paths that facilitate the application of selected test signals to determine gain and phase imbalances introduced by the transmitter and receiver. In a first ‘normal’ configuration, the I and Q channels are independently tested by applying an I-only test signal, followed by a Q-only test signal. In a second ‘switched transmitter’ configuration, the Q-only test signal is again applied. In a third ‘switched receiver’ configuration, the I-only test signal is again applied. By combining the results, gain and phase imbalances of the transmitter and the receiver can be determined. In a preferred embodiment, these configurations and test signals are applied within a single transceiver that has the output of its transmitter closed-loop coupled to the input of its receiver.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: June 30, 2009
    Assignee: NXP B.V.
    Inventor: Yifeng Zhang
  • Patent number: 7529533
    Abstract: The embodiments of the present invention provide a configurable homodyne/heterodyne RF receiver including first and second mixers. The configurable homodyne/heterodyne RF receiver functions as a homodyne receiver when the first and second mixers are configured to operate in parallel, and as a heterodyne receiver when the first and second mixers are configured to operate in series. The embodiments of the present invention further provides an RFID reader employing the configurable homodyne/heterodyne RF receiver to facilitate a listen-before-talk function.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: May 5, 2009
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: John Vincent Bellantoni
  • Patent number: 7514993
    Abstract: A method and apparatus for the demodulation, filtering, decimation and optional voltage multiplication of modulated signals to produce in-phase and quadrature outputs using a discrete time architecture.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: April 7, 2009
    Inventor: Alon Konchitsky
  • Patent number: 7505533
    Abstract: A clock data recovery circuit with feedback type phase discrimination. The clock data recovery circuit has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits per cycle from a data input signal according to a sampling clock signal. The phase region decision circuit generates a plurality of binary up-down decision signals according to the oversampled data input signal and a current phase status signal. The phase status register generates the current phase status signal according to the binary up-down decision signals. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: March 17, 2009
    Assignee: Via Technologies, Inc.
    Inventors: Tse-Hsien Yeh, Wei-Yu Wang
  • Publication number: 20080279172
    Abstract: A demodulation section 13 receives a TDMA-TDD based phase-modulated burst signal of mobile communications and demodulates the burst signal by a synchronous detection system (or a quasi-synchronous detection system). The demodulation section 13 includes a frequency deviation compensation section and a carrier recovery section each having a loop filter 14 with three or more stages of time constants. The time constants are switched by a selector switch 15 based on a control signal from a demodulation control section 16. This achieves quick pull-in and jitter after convergence is minimized, thereby allowing highly efficient performance of frequency deviation compensation, etc. that is required for synchronous detection (or quasi-synchronous detection) without increasing the size of circuit.
    Type: Application
    Filed: May 17, 2004
    Publication date: November 13, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Taisei Suemitsu