Abstract: An RFID reader analog front end architecture employs multiplexed use of a single analog to digital converter in order to digitize the inphase and quadrature components of the incoming signal from the reader's receiving antenna. The Type 1 architecture includes an analog I/Q switch that controls which of the baseband signals will be digitized by a single Analog to Digital Converter. In the Type 2 architecture, the I/Q switch is moved so that it is directly adjacent to the receive mixers, requiring only one antialiasing filter block and gain block. In the Type 3 architecture, one mixer and its associated filtering chain are eliminated. The Type 4 architecture provides for selection of transmitter phase basis by means of an I/Q switch operating under control of the DSP that phase-shifts the transmitter with respect to the receiver.

Abstract: A control signal is wirelessly transmitted from a first radio communication unit of a portable communication device to a second radio communication unit. The portable communication device is provided for radio communication over a first radio frequency band using a first modulation technique. The control signal is transmitted by generating a control signal, switching off the first modulation of a carrier signal, shifting the frequency of the carrier signal from a first radio frequency band to a second radio frequency band for the first radio communication unit, switching on the second modulation of the carrier signal having a frequency within the second radio frequency band, wherein the carrier signal is modulated with the control signal, and transmitting the control signal modulated carrier signal wirelessly over the second radio frequency band to the second radio communication unit.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: The present invention, takes advantage of the properties of quadrature signals to achieve precise quadrature alignment in a simple fashion. The expectation of the product of quadrature signals is zero. A phase error detection network therefore operates by multiplying the received quadrature signals and low-pass filtering the product to produce an error signal. When the signals are in precise quadrature relationship, the error signal will be zero. Real-time feedback control may be used to drive the error to zero. In accordance with another aspect of the invention, a variable phase shift network is achieved using a dual delay line. The difference in delay between the two delay lines is adjusted in response to the error signal to obtain precise quadrature alignment. The principles of the invention may be applied in connection with traditional mixer architectures or with switch-mode architectures.

Abstract: An integrated circuit operable to wirelessly communicate with other devices by utilizing a radio transceiver and a routing element is disclosed. The routing element is operable to route a signal between various circuit elements and is selectively operable to function as an antenna when coupled with the radio transceiver.

Abstract: A quadrature transmitter and receiver have configurable I and Q channel paths that facilitate the application of selected test signals to determine gain and phase imbalances introduced by the transmitter and receiver. In a first ‘normal’ configuration, the I and Q channels are independently tested by applying an I-only test signal, followed by a Q-only test signal. In a second ‘switched transmitter’ configuration, the Q-only test signal is again applied. In a third ‘switched receiver’ configuration, the I-only test signal is again applied. By combining the results, gain and phase imbalances of the transmitter and the receiver can be determined. In a preferred embodiment, these configurations and test signals are applied within a single transceiver that has the output of its transmitter closed-loop coupled to the input of its receiver.

Abstract: The embodiments of the present invention provide a configurable homodyne/heterodyne RF receiver including first and second mixers. The configurable homodyne/heterodyne RF receiver functions as a homodyne receiver when the first and second mixers are configured to operate in parallel, and as a heterodyne receiver when the first and second mixers are configured to operate in series. The embodiments of the present invention further provides an RFID reader employing the configurable homodyne/heterodyne RF receiver to facilitate a listen-before-talk function.

Abstract: A method and apparatus for the demodulation, filtering, decimation and optional voltage multiplication of modulated signals to produce in-phase and quadrature outputs using a discrete time architecture.

Abstract: A clock data recovery circuit with feedback type phase discrimination. The clock data recovery circuit has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits per cycle from a data input signal according to a sampling clock signal. The phase region decision circuit generates a plurality of binary up-down decision signals according to the oversampled data input signal and a current phase status signal. The phase status register generates the current phase status signal according to the binary up-down decision signals. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal.

Abstract: A demodulation section 13 receives a TDMA-TDD based phase-modulated burst signal of mobile communications and demodulates the burst signal by a synchronous detection system (or a quasi-synchronous detection system). The demodulation section 13 includes a frequency deviation compensation section and a carrier recovery section each having a loop filter 14 with three or more stages of time constants. The time constants are switched by a selector switch 15 based on a control signal from a demodulation control section 16. This achieves quick pull-in and jitter after convergence is minimized, thereby allowing highly efficient performance of frequency deviation compensation, etc. that is required for synchronous detection (or quasi-synchronous detection) without increasing the size of circuit.

Abstract: A parallel data transmission test system can include a receiver section (100) having input selector circuits (104-O to 104-N) that provide a received test data to logic adjust circuits (106-O to 106-N) that “logically align” multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit (108) can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit (110).

Abstract: The invention relates to the distribution of a synchronization signal in an optical communication system which is inherently asynchronous. In order to accomplish a cost-efficient mechanism for transmitting a synchronization signal in such a system, the amplitude of a payload signal is modulated with the synchronization signal, whereby an amplitude-modulated payload signal is obtained. This amplitude-modulated payload signal is transmitted as an optical signal to the opposite end of an optical link, where the synchronization signal is separated from the payload signal.

Abstract: Apparatus for reducing DC offset in a signal path of a conversion system comprising a front end circuit for providing an input signal having an a DC offset; an amplifier system coupled to the front end circuit to receive and amplify the input signal; a multi-bit sigma delta modulator for receiving the input signal from the amplifier system and providing a first bit quantizer; a DC adapt circuit coupled to the sigma delta modulator for receiving the first bit quantizer from the sigma delta modulator and for providing an operation to reduce DC offset; a digital to analog converter (DAC) coupled to the digital DC adapt circuit to provide an analog signal representative of the DC offset correction to the input of the amplifier system, wherein the digital DC adapt circuit and the DAC form a feedback path originating at the first bit of the multi bit sigma delta modulator to the input of the amplifier system.

Abstract: A decoder of a data signal subjected to phase shifting keying (PSK) modulation uses a plurality of phase locked loops (801-1 to 801-n) having an inner decoder for short block codes, at least one of which is adapted to apply excess processing power to process a selected burst of the data signal, such as processing the burst with multiple initial phase/frequency error estimates. A selection circuit identifies the burst and supplies to said one of said plurality of phase-locked loops (801-1 to 801-n) for re-processing the bust with excess processing power. An outer Reed-Solomon block decoder (319) may be used to correct errors in the codewords from the phase locked loops and may be used in the selection of the burst by the selection circuit.

Abstract: A radio receiver is configurable to operate in both low-IF and zero-IF modes with maximum re-use of of analogue and digital circuitry between modes. The receiver comprises a quadrature down-converter (108,110,112,114) for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter (516) for performing image rejection filtering. In the low-IF mode, one of the outputs (Q) of the filter (516) is terminated, the other (I) is digitised by a non-complex ADC (520), then the digital signal is filtered and decimated. Quadrature-related IF signals are then re-generated before down-conversion and demodulation. In the zero-IF mode, both outputs of the filter (516) are digitised and processed in parallel before demodulation. By enabling analogue-to-digital conversion and channel filtering to be performed at low-IF on non-complex signals, use of just two non-complex ADCs (120,1620) is possible, thereby avoiding duplication of circuitry and providing significant power savings.

Abstract: Frequency translation and applications of the same are described herein, including RF modem and wireless local area network (WLAN) applications. In embodiments, the WLAN invention includes an antenna, an LNA/PA module, a receiver, a transmitter, a control signal generator, a demodulation/modulation facilitation module, and a MAC interface. The WLAN receiver includes at least one universal frequency translation module that frequency down-converts a received EM signal. In embodiments, the UFT based receiver is configured in a multi-phase embodiment to reduce or eliminate re-radiation that is caused by DC offset. The WLAN transmitter includes at least one universal frequency translation module that frequency up-converts a baseband signal in preparation for transmission over the wireless LAN. In embodiments, the UFT based transmitter is configured in a differential and multi-phase embodiment to reduce carrier insertion and spectral growth.

Abstract: In a transceiver which is configured in particular for transmitting optical data, there is provided a device for reconstructing data from a received data signal (RX), having a clock-signal recovery unit (3) for recovering a clock signal belonging to the transmitted data from the received data signal, and having a data reconstruction unit (2) for reconstructing the transmitted data from the received data signal using the recovered clock signal (fCLK), and for emitting a data stream (DATA) which is synchronised with the recovered clock signal.

Abstract: Methods and apparatuses for frequency selectivity and frequency translation, and applications for such methods and apparatuses, are described herein. The method includes steps of filtering an input signal, and down-converting the filtered input signal. The filtering and the down-conversion operations are performed in an integrated, unified manner. The apparatus described herein can be implemented as an integrated circuit (IC).

Abstract: For use in an orthogonal frequency division multiplexing (OFDM) transceiver, a multimode local oscillator circuit and a method of operating the same. In one embodiment, the circuit includes: (1) a single sideband mixer having an output, first and second inputs and a local oscillator input and (2) a signal generator, coupled to the single sideband mixer, for alternatively providing to the first and second inputs: (2a) constant values to cause the single sideband mixer to generate a first receiver local oscillator signal for operating the OFDM transceiver as a zero intermediate frequency receiver and (2b) a first orthogonal baseband signal to cause the single sideband mixer to generate a second receiver local oscillator signal for operating the OFDM transceiver as a low intermediate frequency receiver.

Abstract: All-digital FSK demodulation can be accomplished by producing in response to a received IF signal digital information (22) indicative of a frequency of the IF signal. A symbol represented by the IF signal can then be determined (28, 44) in response to the digital information.

Abstract: A carrier wave NTSC component or a VSB pilot signal in an IF signal is extracted and judged. Then, on the basis of the judgment result, either of demodulation circuit 13 and 14, which is appropriate for the received broadcast wave is switched. Information of co-broadcasting programs for analog and digital broadcasts are acquired from EPG and memorized. In case of high-speed channel search, analog broadcast is preferentially switched to. In case of co-broadcasting, the analog broadcast program is displayed on the screen at the beginning, and then, the digital broadcast program is switched when the data decoding is completed.

Abstract: Method and modem for fast timing recovery of transmitted data between a master ?DSL modem and a slave ?DSL modem, over a noisy, high loss, high distortion wiring. Transmitted QAM symbols are received and sampled at the slave modem. The sampled data is split into in-phase and quadrature channel, each of which is filtered by matched filter. The filtered outputs are sampled at twice the symbol rate and the lower and upper band edge components are extracted by modulating each of the sampled sequences of outputs with two discrete time sequences: cos(0.5 ? n)=. . . 1,0,?1,0 . . . and sin(0.5 ? n)=. . . 0,1,0,?1 . . . . Each of the resulting products is filtered with a first order low-pass filters and re-sampled again at the symbol rate. The Bit Error Rate is computed, and the slave modem switches from blind timing recovery mode, to data directed timing recovery mode, after the Bit Error Rate has sufficiently decreased.

Abstract: A synchronization system in accordance with the principles of the invention includes a central synchronizing management unit, at least one synchronization distribution unit, and at least one network element. Each synchronization distribution unit receives synchronization and management information from the central synchronization management unit. This information may be transmitted directly from the central synchronization management unit, or it may be transmitted though another synchronization distribution unit in a group of a daisy-chained synchronization distribution units. The daisy-chained arrangement employs both active and passive optical paths. The central synchronizing management unit may query any synchronization distribution unit within the system to obtain performance statistics.

Abstract: One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.

Abstract: A demodulator for demodulating a modulated input signal transmitted at a carrier frequency includes a current mirror for receiving the modulated input signal and generating a first and a second current-mirror output signals of same amplitude and frequency as the modulated input signal. The demodulator further includes a first and a second switch-controlled sampling circuits connected to the current mirror for receiving the first and second current mirror output signals respectively. The demodulator further includes a switching signal generator provided for generating a first and a second switch control signals having a frequency substantially equals to the carrier frequency with a flexibly adjustable phase difference between the first and the second switch control signals.

Abstract: At the time of ordinary communication, up-mixer 108 combines a signal with a frequency f2 from frequency synthesizer 124 with I and Q signals for transmission that are quadrature modulated in quadrature modulator 105, down-mixer 115 combines the signal with the frequency f2 with a received signal, then only in the case of receiving a signal with a frequency fr′ different from a frequency fr, frequency synthesizer 125 that generates a signal with a frequency f3 different from the frequency f2 is operated, and frequency synthesizer 125 and down-mixer 115 are connected with switch 127, so that down-mixer 115 combines the signal with the frequency f3 with a received signal. It is thereby possible to switch frequencies fast and with low current consumption in receiving a signal with a reception frequency other than a combination of transmission frequency and reception frequency specified in an ordinary radio system.

Abstract: A demodulation system capable of configuring itself responsive to channel conditions. A plurality of detectors may be provided, one or more of which may be better able to handle a particular form of interference than one or more of the other detectors. The detectors estimate source bits from a common signal. One or more signal quality estimators receive the estimated bits for the detectors, and provide performance metrics for each of the detectors. A selector selects or continues the pre-selection of one of the detectors responsive to the performance metrics. A multiplexor outputs the estimated bits from the selected or pre-selected detector.

Abstract: A direct conversion receiver is disclosed that converts RF signal into corresponding quadrature baseband signals without requiring conversion through an intermediate frequency. The direct conversion receiver abates local oscillator leakage, increases dynamic range and increases RF selectivity as compared to conventional direct conversion circuits. The circuit includes an in-phase branch and a quadrature-phase branch, each branch including two mixers instead of the conventional one. Each mixer is provided with balanced control signals that include a primary control signal and a complementary control signal. For each branch, the signals from the mixer pass through an operational amplifier and a low pass filter to extract the corresponding baseband signal component.

Abstract: A clock identification and reproduction circuit which synchronizes a clock signal with an input signal includes a voltage controlled generator for generating a clock signal, a phase comparator for detecting a phase difference between an input signal and a clock signal to generate a phase difference signal according to the phase difference, and a filter for synchronizing a clock signal of the voltage controlled generator in response to a phase difference signal, in which the phase comparator generates a phase difference signal when a specific pulse waveform of a pulse of an input signal changes.

Abstract: Methods and apparatuses for frequency selectivity and frequency translation, and applications for such methods and apparatuses, are described herein. The method includes steps of filtering an input signal, and down-converting the filtered input signal. The filtering and the down-conversion operations are performed in an integrated, unified manner. The apparatus described herein can be implemented as an integrated circuit (IC).

Abstract: A receiving apparatus and method which can prevent second order harmonic interference and beat interference in a direct orthogonal detector is disclosed. When a control signal of the high level is inputted to a control terminal, then a first high frequency switch diode is turned on and a second high frequency switch diode is turned off. In this instance, a filter circuit functions as a low-pass filter. When a control signal of a low level is inputted to the control terminal, then the first high frequency switch diode is turned off and the second high frequency switch diode is turned on. In this instance, the filter circuit functions as a high-pass filter.

Abstract: A pilot phase tracking loop for an OFDM receiver including a phase rotator for receiving an incoming signal, which is coupled to a Fourier transform, which is coupled to a pilot phase error metric for determining a phase error estimate associated with a received OFDM symbol, e.g., a data symbol. The pilot phase error metric is coupled to a loop filter, which is coupled to an oscillator, which is coupled back to the phase rotator. The phase rotator rotates the incoming signal by the filtered phase error estimate for subsequent OFDM symbols to reduce the phase noise of the signaling output from the phase rotator. Thus, the phase noise introduced by a radio portion of the OFDM receiver and an OFDM transmitter is compensated for by the pilot phase error estimation in the baseband portion of the OFDM receiver and improved OFDM signal tracking is accomplished under poor SNR conditions.

Abstract: A receiving circuit mainly available in a digital modulation type communication system having a plurality of channels, which is capable of reducing power in a receiving system, simplifying the circuit and reducing the power consumption. Upside and downside frequencies corresponding to a central value between channels are separately supplied from a local frequency signal generating circuit 4 to first and second frequency converting circuits 2, 3 so that two output signals are developed with respect to one of a desired wave, upside channel and downside channel. The desired wave present in common in the first and second frequency converting circuits 2, 3 is extracted in a common wave extracting circuit 5, and a frequency offset of &ohgr;o existing in the output of the common wave extracting circuit 5 is removed a frequency offset circuit 6 and further an unnecessary frequency component is filtered by a filter 8.

Abstract: This invention discloses a demodulation method. The method includes steps of: A) Receiving a modulated input signal having an input signal frequency. B) Generating a first switch control signal at a first switching frequency substantially equal to the input signal frequency. C) Generating a second switch control signal having the same frequency as the first switch control signal and having a phase that is approximately 90 degrees different from a phase of the first switch control signal. And D) Controlling at least two switching circuits with the first and second switch control signals for obtaining at least two sets of sampled amplitudes of the input signals for generating switching output signals for each of the switching circuits defined by subtracting the sampled amplitudes when the first switch control signal is high by the sampled amplitudes when the first switch control signal is low for each of the switching circuits to generate demodulated output signals for the modulated input signal.

Abstract: An echo cancellation functionality taps a digital transmit signal from a transmit channel for processing through an adaptive filter of an echo channel to generate an echo cancellation signal. The adaptive filter has a transfer function substantially matching an echo transfer function which defines a relationship between the transmit signal and an unwanted echo component corrupting an analog receive signal. The echo cancellation signal is digital-to-analog converted to an analog signal and then subtracted from the analog receive signal to substantially cancel out the unwanted echo component. The echo cancellation functionality may be configured in a training mode to generate an error signal used to adaptively configure the adaptive filter transfer function to substantially match the echo transfer function. When in training mode, certain components of an adaptation loop which contribute to a feedback loop transfer function are selectively by-passed.

Abstract: A method and apparatus providing for a multifrequency receiver with upstream switching of received frequencies. The invention is described in connection with a cable plant having a plurality of modems transmitting at a first frequency. It may be desirable to locate a second frequency having more desirable transmission characteristics and to cause the modems to transmit at the second frequency. It is disclosed to utilize an additional receiver coupled through a switch which may be used to both locate a desirable frequency and to facilitate automatic switching of the cable modems from the first frequency to the second frequency.

Abstract: In a radio receiver for digital transmissions, an adaptive channel equalizer is clocked at a sampling rate higher than symbol rate by a factor k and employs decision feedback for adjusting the coefficients of its component filters. The channel equalizer response as supplied at the sampling rate k times symbol rate is decimated to symbol rate and quantized to generate a signal estimating the symbols transmitted to the receiver. The channel equalizer response as supplied at the sampling rate k times symbol rate is compared to the signal estimating the transmitted symbols as re-sampled to the sampling rate k times symbol rate, in order to develop decision-feedback error signal at the sampling rate k times symbol rate. This decision-feedback error signal has sufficient digital bandwidth to permit fractionally spaced equalization with all coefficients being optimally adjusted.

Abstract: The present invention provides a digital video receiving apparatus for displaying a plurality of digital TV pictures on a plurality of receiving terminal apparatuses. The digital video receiving apparatus includes a tuner for extracting the received digital TV multiplexed signal, a demodulator for decoding the digital signals provided from the tuner, a demultiplexer for demultiplexing the multiplexed signals outputted from the demodulator to obtain a bit stream including a video signal, an audio signal and a data signal. The digital video receiving apparatus further includes a video decoder, an audio decoder and a data decoder for decoding signals outputted from the demultiplexer. The digital video receiving apparatus decodes the input multiplexed digital TV signal and outputs a video signal, an audio signal and a data signal corresponding to respective programs.

Abstract: A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals.

Abstract: A receiving circuit mainly available in a digital modulation type communication system having a plurality of channels, which is capable of reducing power in a receiving system, simplifying the circuit and reducing the power consumption. Upside and downside frequencies corresponding to a central value between channels are separately supplied from a local frequency signal generating circuit 4 to first and second frequency converting circuits 2, 3 so that two output signals are developed with respect to one of a desired wave, upside channel and downside channel. The desired wave present in common in the first and second frequency converting circuits 2, 3 is extracted in a common wave extracting circuit 5, and a frequency offset of &ohgr;o existing in the output of the common wave extracting circuit 5 is removed a frequency offset circuit 6 and further an unnecessary frequency component is filtered by a filter 8.

Abstract: Apparatus and methods for adaptively, reliably, and accurately measuring the frequency of an alerting or other signaling tone. A tone detector measures the frequency of a tone (continuous or pulsed) with a high degree of accuracy (e.g., to within 1 part in 10,000). Two lower order or smaller DFTs measure the energy level in two separate but intersecting frequency ranges. A simple ratio is determined from the relative energy measured from discrete Fourier transforms relating to each of the two separate frequency ranges, and an actual measured frequency is determined.

Abstract: A circuit for demodulating a signal having a temporal mixture of different modulation schemes applied thereto includes a synchronization-word-detection unit which detects synchronization words included in the signal, and generates first and second position signals, based on the detected synchronization words, indicative of respective predetermined positions in the signal, a first selection unit which selects the first position signals during a first period, and selects the first position signals and the second position signals during a second period, and a carrier-reproduction unit which carries out frequency capturing during the first period by using the first position signals selected by the first selection unit, and carries out phase capturing during the second period by using the first position signals and the second position signals selected by the first selection unit, thereby reproducing a carrier.

Abstract: A clock/data recovery device employs a phase-locked loop that supplies a single clock signal and a control voltage signal to at least one clock/data recovery circuit. The clock/data recovery circuit has a voltage-controlled delay line or direct phase controlled voltage-controlled oscillator that generates a multiple-phase clock signal, which is used to recover a clock signal and data from a received data signal. The voltage-controlled delay line or direct phase controlled vottage-controlled oscillator has a cascade or ring of voltage controlled logic gates, with propagation delays controlled by the control voltage signal from the phase-locked loop, and additional logic gates that supply the clock signal from the phase-locked loop to a selectable one of the voltage-controlled logic gates.

Abstract: A demodulation subsystem includes an equalizing demodulator and a non-equalization demodulator, each of which receive a baseband signal, and an output control selector that selects the output of one of the equalizing demodulator and the non-equalizing demodulator based on a bit error rate of the signal.

Abstract: A device for demodulating a binary signal having a predetermined carrier frequency and phase-modulated by encoded pulses. The device includes a phase-locked loop circuit having a phase comparator followed by a low-pass filter and a voltage-controlled oscillator, which is voltage-controlled by the output of the filter. The voltage-controlled oscillator outputs a binary signal that is synchronous with the modulated signal and at a frequency N times the carrier frequency. The phase-locked loop circuit also includes a divider that divides by N the output signal of the oscillator and supplies the divided signal to one input of the phase comparator. Thus, a binary signal synchronous with the modulated signal and having a frequency equal to the carrier frequency is supplied to one input of the phase comparator. The other input of the phase comparator receives the modulated signal.

Abstract: A circuit is designed with a delay circuit (102) coupled to receive a frequency-modulated data signal (100) at a delay input terminal. The delay circuit produces the data signal (103) after a predetermined delay at a delay output terminal. An exclusive OR circuit (104) has a first input terminal coupled to the delay input terminal and has a second input terminal coupled to the delay output terminal.

Abstract: A receiver for input signals generated using a phase-based modulation scheme such as bipolar-phase shift-keying (BPSK) modulation or quadrature-phase shift-keying (QPSK) modulation. The receiver can sample the input signal using one of at least two different sampling frequencies that are selected such that at least one of the sampling frequencies is not harmonically related to the carrier frequency of the input signal by a ratio of small numbers. In this way, the receiver can avoid interference patterns that can result when the sampling frequency and the carrier frequency are harmonically related. In one embodiment, the receivers are hard-limiting receivers that are suitable for use in the remote nodes of fiber-to-the-curb (FTTC) communication systems, where low-power receivers are desirable.

Abstract: A clock recovery circuit includes an A/D converter and samples sampled signals from a received signal of a modulation rate depending on a sampling clock signal with a frequency twice the predetermined modulation rate. An amplitude detector detects an amplitude of a first sampled signal and an amplitude of a second sampled signal following the first samples signal. By comparing the amplitudes of the first and second sampled signals, a smaller one of the first and second sampled signals is selected. A phase of the sampling clock signal is controlled so that the amplitude of the smaller signal is minimized.

Abstract: A baseband demodulator receives inphase and quadrature signals I (116) and Q (117) representing a phase angle and amplitude. The demodulator (114) includes a discrete time continuous amplitude circuit (223, 253, 260) coupled to the quadrature generator to extract a sign information by processing the quadrature components (116 and 118). An accumulator 404 uses the sign information to manipulate predetermined phase angles stored at a memory component 402 to determine the phase angle carried by the I and Q components (116 and 118). As such, the need for up converters or complex analog-to-digital converters is eliminated in direct conversion receivers.

Abstract: In a digital radio communication apparatus which receives PSK modulated signal, a plurality of items of quantized data are sampled at a plurality of points including a central point, which corresponds to one of each rising edge or each decaying edge of a reproduction clock signal, points before the central point and points after the central point. The sampled plurality of items of quantized data are combined so that combined phase data is obtained for each symbol.