Abstract: A digital demodulator which demodulates an analog signal obtained through a quadrature amplitude modulation to produce a digital demodulated signal includes a converter to convert the analog signal into a digital signal and a signal processor to quadrature-demodulating the digital signal from the converter. Assuming that the analog signal has a carrier frequency of f.sub.IF and the signal conversion is accomplished with the sampling frequency fs, the demodulator is set to satisfy fs=4.multidot.f.sub.IF /(2n+1), where n denotes a positive integer. The signal processing section conducts the quadrature demodulation according to a quadrature local oscillation signal having a frequency fc satisfying fc=fs/4.

Abstract: In accordance with the present invention, a receiver of the type receiving both a signal subjected to FM (Frequency Modulation) and a signal subjected to orthogonal modulation is capable dealing with the two different kinds of signal by use of a single demodulator. This successfully scales down the circuitry of the receiver.

Abstract: A receiving circuit mainly available in a digital modulation type communication system having a plurality of channels, which is capable of reducing power in a receiving system, simplifying the circuit and reducing the power consumption. Upside and downside frequencies corresponding to a central value between channels are separately supplied from a local frequency signal generating circuit 4 to first and second frequency converting circuits 2, 3 so that two output signals are developed with respect to one of a desired wave, upside channel and downside channel. The desired wave present in common in the first and second frequency converting circuits 2, 3 is extracted in a common wave extracting circuit 5, and a frequency offset of .omega.o existing in the output of the common wave extracting circuit 5 is removed a frequency offset circuit 6 and further an unnecessary frequency component is filtered by a filter 8.

Abstract: A demodulator for demodulating an MSK signal constituted by a sequence of MSK modulated symbols is disclosed. An exclusive OR signal obtained by delay detection is delayed by delay times shorter than one symbol time. The delayed signals thus obtained are logically processed in parallel. Each symbol thus can be recovered by demodulation in one symbol time.

Abstract: A carrier reproducing circuit for detecting a phase error when an inputted baseband signal is out of phase and bringing the baseband signal into phase even in QAM systems in which normal signal points are located in a non-square pattern in a phase-amplitude signal space. When the baseband signal is out of phase, a first region decision circuit detects a presence of the baseband signal in a first region and outputs a first signal, and a second region decision circuit detects a presence of the baseband signal in a second region and outputs a second signal. If the second signal is not outputted over a predetermined period of time around the time at which the first signal is outputted, then a selective outputting circuit outputs a phase error detected by a phase error decision circuit with respect to the baseband signal at the time the first signal is outputted, to a control signal generator.

Abstract: The invention relates to a transceiver for generating complex I/Q-signals on a transmission frequency (f.sub.TX) and for receiving them on a reception frequency (f.sub.RX). The device comprises a first frequency synthesizer (41) for forming a first mixer signal (f.sub.LI) for the mixer (42) of the first branch that mixes the I-component of the received signal into a lower-frequency I-signal, and a second frequency synthesizer (411, 49, 46) for forming a second mixer signal (f.sub.LQ) for the mixer (421) of the second branch that mixes the Q-component of the received signal into a lower-frequency Q-signal. The device further comprises control means (45) first for directing the phase of the first (f.sub.LI) and the second (f.sub.LQ) mixer signals into the same phase in the mixing effects thereof and, thereafter, into a 90 degree mutual phase shift in the mixing effects thereof when receiving signals for bringing the lower-frequency I- and Q-signals into a 90 degree mutual phase shift.

Abstract: The demodulator is for processing a signal having a carrier modulated by (0, .pi.) phase shifts and sampled at a rate that is at least twice the frequency of the carrier co. It comprises, in cascade: a first multiplier for squaring successive samples e(t), a phase locked loop adjusted to the frequency of the carrier, thereby performing programmable digital filtering; a divider for dividing the frequency by two, reconstituting the carrier from the output of the phase locked loop; a second multiplier receiving the sampled input signal and the output signal from the divider and an output lowpass digital filter. A phase adjustment circuit is placed upstream of one of the inputs of the second multiplier.

Abstract: A high-speed demodulating method of burst data capable of performing demodulation process at high speed in a single hardware structure. An input signal digitally modulated is taken in into an input unit to be sampled and latched therein by a sampling clock from a controller, and a modulation signal from the input unit is taken in into either a first demodulator or a second demodulator for each one burst data depending on the timing of a first control signal or a second control signal output by the controller, respectively, and demodulated, and a first demodulation signal produced from the first demodulator or a second demodulation signal produced from the second demodulator is taken in into an output unit by a third control signal output by the controller, and in the output unit, the first demodulation signal or the second demodulation signal is latched by a latch signal of the controller and supplied as an output signal.

Abstract: A method for correcting an amplitude error between an I signal and a Q signal which are outputted from a quadrature detector including a first multiplier for multiplying a reference signal and a measured signal, a first integrator for smoothing the output of the first multiplier to generate the I signal, a 90-degree phase shifter for generating an auxiliary reference signal from the reference signal, a second multiplier for multiplying the auxiliary reference signal and the measured signal, and a second integrator for smoothing the output of the second multiplier to generate the Q signal. The method includes the step of inputting the auxiliary reference signal, instead of the reference signal, to the first multiplier to obtain a first output signal and inputting the reference signal, instead of the auxiliary reference signal, to the second integrator to obtain a second output signal.

Abstract: A miniaturized FSK demodulation circuit for accurately demodulating a signal having a small modulation index comprises a multiplier for multiplying a FSK modulated input signal by 4, an oscillator for generating a first signal having the same frequency and phase as the input signal, a phase shifter for producing a second signal by phase shifting the first signal by 90.degree.

Abstract: A digital filtering system for filtering a first and a second digital signals inputted from a FSK (frequency-shift-keying) demodulator to generate a first and a second filtered digital signals. The FSK demodulator is used for demodulating a four level FSK signal into the first and second digital signals.

Abstract: A signal demodulation apparatus using a multi-ary sampling for beam formation of a received signal reduces a difference between a sampling point of time of an in-phase signal and a sampling point of time of a quadrature signal due to an existing secondary sampling method. Each of a plurality of analog-to-digital converters produces a first in-phase signal and at least two first quadrature signals adjacent to the first in-phase by sampling each input signal input via a plurality of channels at a sampling point of time having a sampling period of the input signal and other sampling points of time having a sampling interval smaller than the sampling period of the input signal. A quadrature component calculator of each channel produces second quadrature signals in which an error due to a difference between the sampling point of time of the first in-phase signal and the sampling points of time of the first quadrature signal is reduced.

Abstract: A digital phase detector 100 receives a limited input signal 108 and inputs it and a reference oscillation 112 into an EXCLUSIVE NOR gate 102. The output 110 of the EXCLUSIVE NOR gate 102 is input to a gated N-bit counter 104, which produces an N-bit representation of the magnitude of the phase 115 of the signal 108. A sign detector 105 determines the sign of the phase of the signal by sampling the resultant 110 and combines the magnitude of the phase 115 with the sign of the phase to produce a digital numeric representation of the phase of the signal 116.

Abstract: An integrated circuit comprises a variable frequency divider for setting a signal transmitting frequency in accordance with a frequency dividing ratio based on externally-provided data. A data converter converts the externally-provided data to a signal for transmission, and a switch selectively provides the externally-provided data to the variable frequency divider and the data converter. As a result, the number of terminals may be reduced, the IC package may be made more compact, the mounting surface area may be reduced, the equipment may be made smaller, and the interference of the data signal provided to the circuit for setting the frequency dividing ratio or the circuit for transmitting data is reduced.

Abstract: A non-coherent frequency shift keying (FSK) demodulator, for receiving a N-ary FSK modulated input signal, demodulating the signal to obtain output data, in which the N-ary FSK modulation has N symbols, and the output data is constructed by a plurality of symbol intervals. The demodulator includes an A/D converter for converting the input signal in digital form, in which, for the A/D converter sampling, a sampling number M of every symbol interval satisfies an equation M.gtoreq.2K+1, wherein K is the interval number of a carrier of the input signal in each symbol interval. N filter arrays each respectively receive the input signals in digital form, and each one of the N filter arrays has a filtering frequency band, respectively, corresponding to spectrums of N symbols in N-ary FSK modulation. N downsamplers each receive the input signal from the corresponding filter array and reduce the sampling number of the input signal to make each symbol interval include only one sample value.

Abstract: A sigma-delta signal converter is implemented using switched capacitor switching elements in which a first switch (31) serves as a mixer (11). The output of the mixer is directed to the second input of an adder (16), and its second input is the feedback signal (f1) of the sigma-delta signal converter, which is also directed into a base-frequency output signal through a decimator (14) and low-pass filtering (15).

Abstract: A digital mixer-filter-decimator (MFD) is disclosed which is reconfigurable so that it can be used in both modes of operation of a dual mode receiver such as an AM/FM receiver. In either mode of operation the MPD performs filtering and decimation operations on separate data streams containing alternate samples of a digital input data stream. In the FM mode a mixing operation is also enabled to produce a complex output comprising in-phase and quadrature components. The mixing operation is disabled in the AM mode and the filtered and decimated outputs are combined to provide a real output. The same decimator filter can be used in both modes.

Abstract: A receiver (100) is utilized for demodulating a multi-level frequency shift keyed (FSK) signal. The receiver (100) includes a mixer (102) for mixing the multi-level FSK signal to generate an in-phase signal and a quadrature signal, and a demodulator circuit (110) coupled to the mixer (102). The demodulator circuit (110) is adapted to count a sequence of state transitions of the in-phase signal and the quadrature signal and to determine a frequency deviation of the multi-level FSK signal based on the sequence of state transitions counted.

Abstract: An "N" channel receiver system includes "N" A/D converters, one per channel, sampling the data received by their respective channels. The sampling rate of the A/D converters is controlled by a sampling clock signal generated by a timing recovery circuit. One rate of the sampling clock is a function of a timing signal applied to the timing recovery circuit. The system may be configured so that each channel produces N distinct timing signals, corresponding to the data signals received by each one of the N channels. The N distinct timing signals are coupled to a mechanism configured to selectively couple one of the N distinct timing signals to the timing recovery circuit. In a preferred embodiment, the signal-to-noise ratio (SNR) of the N received signals is sensed and the timing signal of the channel having the highest SNR is coupled via the controllable.

Abstract: In a digital data demodulating apparatus, total number of low-pass filters is reduced by supplying variable sampling clock signals to A/D converters coupled to the low-pass filters. The digital data demodulating apparatus for receiving/demodulating a transmission signal that is modulated by digital data in a predetermined modulation manner, includes: a detecting unit for detecting the transmission signal; a low-frequency component passing unit for causing a low-frequency component of the transmission signal detected by the detecting unit to selectively pass therethrough; an analog-to-digital (A/D) converting unit for A/D-converting the output from the low-frequency component passing unit into a digital transmission signal; a demodulating unit for demodulating the digital transmission signal from the A/D converting unit; and a switching unit for switching a frequency of a sampling clock produced from the A/D converting unit in response to an external switching instruction.

Abstract: An infrared remote-control receiver employs at its front end a gyrator-configured transistor operating as a current-to-voltage converter, but derives its data information from a negative-going gyrator output pulse in preference to the more conventionally used positive-going pulse. This negative-going pulse may be wider than the positive-going pulse and reduces the bandwidth demand on subsequent processing circuitry. This enables low-bandwidth, low-current hardware to be used which makes the receiver ideal for use in battery-operated systems. Also, the negative-going pulse is easier to detect, as it directly follows a disturbance known to be in the opposite direction. The result is an increased receiver sensitivity.

Abstract: A clock recovery circuit capable of outputting decision point data without causing any slip of a recovered clock in the case of operation in a continuous mode in a demodulator in which received signals are sampled by a fixed frequency clock to obtain the recovered clock and symbol data are demodulated by using this recovered clock. A shift register stores digital received signals obtained by an A/D conversion of quasi-coherent detection received signals, and a clock phase estimator calculates an estimated phase difference between an output value of a phase generator operated by the fixed frequency clock and a symbol clock of the received signals and outputs timing information and phase information of a decision point for discriminating the data of the received signals. An interpolator inputs the output signal of the clock phase estimator, takes in the digital received signals from the shift register and calculates decision point data by interpolation to output the same.

Abstract: In a first direct conversion receiver for demodulating I and Q signals, having a quadrature relation therebetween, obtained from a received FSK signal through a direct conversion, a first D FF latches a level of the I signal when a sign condition of I and Q signals moves from the same to different sign conditions, a second D FF latches a level of the Q signal when the sign condition of the I and Q signals moves from the different to same sign condition and EXCLUSIVE OR operations are made among the I and Q signals and the outputs of the first and second D FFs to provide a frequent data judgement to improve a receiving sensitivity of an FSK signal having a relative low modulation index. In a second direct conversion receiver, a sign change in the Q signal is detected by a first edge detection circuit 17, a first D FF holds the level of the I signal, and an EXCLUSIVE OR circuit provides a first demodulation result.

Abstract: An inversion prevention device to prevent inversion and provide the best S/N ratio detects a point where the zero crossing is missing from a quantized FM signal. An output is provided by switching between the digital FM signal and the output signal of at least one sideband suppression filter based on a result of the inversion detection. Alternatively, an output is provided by switching between the digital FM signal and a specified value based on a result of the inversion detection. As a further alternative, an output is provided by switching between the digital FM signal, the output signal of a low-sideband emphasis filter and the output signal of a sideband suppression filter based on a result of the inversion detection.

Abstract: A first AFC apparatus receives and detects I and Q signals from a received first FSK signal with a local osc signal; demodulates the I and Q signals; F/V-converts I or/and Q signals into a voltage; compares it with a reference; and detects a frequency deviation direction of the local osc signal from the carrier signal according to the results of comparing and the demodulating. The local osc frequency is controlled by a given amount according to the result of the frequency deviation direction detection. A second AFC apparatus receives and detects I and Q signals using a first osc signal; FSK-modulates the I and Q signals with a second local osc signal having a lower frequency than the first local osc signal; and compares the frequency of the second FSK signal and the second local osc signal to supply a demodulation result. A frequency control for the first local osc signal is obtained by an averaging circuit averaging the modulation result.

Abstract: A clock recovery circuit capable of outputting decision point data without causing any slip of a recovered clock in the case of operation in a continuous mode in a demodulator in which received signals are sampled by a fixed frequency clock to obtain the recovered clock and symbol data are demodulated by using this recovered clock. A shift register stores digital received signals obtained by an A/D conversion of quasi-coherent detection received signals, and a clock phase estimator calculates an estimated phase difference between an output value of a phase generator operated by the fixed frequency clock and a symbol clock of the received signals and outputs timing information and phase information of a decision point for discriminating the data of the received signals. An interpolator inputs the output signal of the clock phase estimator, takes in the digital received signals from the shift register and calculates decision point data by interpolation to output the same.

Abstract: A demodulator (18) which receives digital representations of a received signal converts those signals into analog signals (53) in a pair of multiplying analog-to-digital converters (MDACs) (21, 22) The analog signals are then combined in combiner (26) by subtracting the first analog signal from the second analog signal (54). The summed signal is normalized (55) in quantizer (27). The output from the quantizer (27) is accumulated (56) in an n-bit accumulator (28) as regulated by a clock input (Fclock). The output of the accumulator (28) is used as a programming input (57) to the MDACs (21, 22).

Abstract: A receiver having, arranged in this order, an input section, an FM demodulator, to which a frequency-modulated input signal is applied, and an LF section, which FM demodulator includes a pulse shaper and a low-pass filter, the pulse shaper comprising a series arrangement of at least a load and a capacitance, the base-emitter junction of a transistor being arranged across the capacitance, and further including a switching device for charging and discharging the capacitance. The pulse shaper generates a low-noise pulse in that charging of a capacitance is started upon an edge of the input signal. The capacitance voltage is measured by a single transistor and when the transistor is turned on, the charging current of the capacitance is diverted via the transistor, so that the capacitance voltage is limited. The capacitance is discharged upon a second edge, after which the cycle is repeated. The output signal of the pulse shaper is a signal which varies with the current through the capacitance.

Abstract: A received signal sample sequence is inversely modulated by a symbol sequence forming the trellis state at the immediately preceding time, by which a reference signal is generated. This reference signal and the inner product of the received signal sample at the current time and a candidate symbol phase are used as a branch metric to make a sequence estimation by the Viterbi algorithm.

Abstract: A phase modulated signal demodulation system which is not affected by noise and distortion of an input signal. The system includes a carrier reproduction PLL circuit for generating a reproduction reference clock having a frequency which is N times of a carrier frequency which is synchronized with an N-phase phase modulated input signal, and a clock generation circuit for dividing the reproduction reference clock by 1/N and for generating N clocks, each of which has a different phase offset by 360.degree./N. The system further includes a phase detector which detects a phase of the N-phase phase modulated signal by using the N clocks together with the input N-phase phase modulated signal; and an operating circuit which detects a data edge of the input signal and the reproduction reference clock.

Abstract: The invention relates to a method for demodulating a digitally modulated signal and to a demodulator. According to the method, a signal (S) to be received is mixed essentially to quadrature related I and Q baseband signals. For improving the interference tolerance of the demodulator, for instance, differences (.alpha.) between directional angles (.beta., .gamma.) of sequential shifts of a signal point on I/Q plane are measured from the baseband signals and said difference is utilized for decision-making concerning a received symbol.

Abstract: A serial data receiver includes a clock recovery circuit, a data latch, and a selectable clock inversion mechanism coupled between the clock recovery circuit and the data latch. In one embodiment, the selectable clock inversion mechanism includes an XNOR gate. If a high signal is provided to the XNOR gate, the XNOR gate provides the signal on a recovered clock line to the data latch, thereby placing the window boundaries coincident with, or very near, the rising edges of the input data pulses. The variable phase between these signals is then adjusted for the maximum coincidence of data pulses with the window boundaries. Then, a low signal is provided to the XNOR gate, thereby providing the true signal on the recovered clock line to the data latch. Assuming the symmetry of the recovered clock is truly 50/50, the window moves by exactly 180 degrees.

Abstract: A coherent phase-shift keying (PSK) detector in a receiver generates an unmodulated carrier signal, without attempting to synchronize the unmodulated carrier signal in frequency or phase to the carrier employed at the PSK transmitter. The instantaneous phase of the received PSK signal is detected with reference to the unmodulated carrier signal to create an instantaneous phase signal. Phase rotation due to frequency offset between the two carrier signals is detected and removed from the instantaneous phase signal, then a remaining phase offset is detected and removed. Data are recovered from the resulting instantaneous phase signal.

Abstract: In a signal demodulating and decoding apparatus, plural demodulators and decoders corresponding to plural modulation systems are provided respectively, and these are operated at the same time, and respective decoding results are outputted. Further, the signal demodulating and decoding apparatus evaluates decision error amounts of respective demodulators and selects the decoding data by the demodulator and the decoder having the least decision error amount. When an operation device for adaptively correcting the parameters used within the demodulator is provided so that decision errors on inputting the decision results of the demodulator into the decoder are made small, the decision error amount inputted to the operation device is selected in a manner similar to that above.

Abstract: A clock recovery circuit capable of outputting decision point data without causing any slip of a recovered clock in the case of operation in a continuous mode in a demodulator in which received signals are sampled by a fixed frequency clock to obtain the recovered clock and symbol data are demodulated by using this recovered clock. A shift register stores digital received signals obtained by an A/D conversion of quasi-coherent detection received signals, and a clock phase estimator calculates an estimated phase difference between an output value of a phase generator operated by the fixed frequency clock and a symbol clock of the received signals and outputs timing information and phase information of a decision point for discriminating the data of the received signals. An interpolator inputs the output signal of the clock phase estimator, takes in the digital received signals from the shift register and calculates decision point data by interpolation to output the same.

Abstract: This detector provides a computationally simple digital low power detector of symbol rate, also called baud rate. It uses an approximate Hilbert transform function to create approximate in-phase and quadrature signals. An approximate envelope detector (feature extractor) processes these signals to produce a signal with a strong frequency component at the symbol rate. This signal is then filtered, accumulated, and threshold detected. The approximate in-phase and quadrature signals are formed by a linear sequence of six delay elements, the output of the third delay element being the in-phase signal. A first summer receives the output of the second delay element at a minus input and the output of the fourth delay element at a plus input. A second summer receives the signal input at a minus input and the output of the sixth delay element at a plus input, and drives a right two bit shifter.

Abstract: A digital quadrature demodulator for an intermediate frequency (IF) input signal with an analog-to-digital (A/D) converter having a sampling frequency f.sub.s and an input to which the IF input signal is applied where the IF input signal has a bandwith B<f.sub.s /4 centered about a frequency of f.sub.s /4. The demodulator includes an arrangement to direct even numbered output signals from the A/D converter to an inphase channel and odd numbered output signals from the A/D converter to a quadrature channel where each channel contains a highpass filter and the demodulator includes circuits to decimate by 4 signals of the channels to generate, together with the filters, a quadrature output signal Q(nT) at an output of the quadrature channel and an inphase output signal I(nT) at an output of the inphase channel. The quadrature highpass filter in the quadrature channel has an optimized transform architecture in which the filter coefficients h.sub.

Abstract: A method for demodulating the carrier signal of powerline communication networks. The method involves demodulating an HDLC data body that had been modulated through differential phase shift keyed modulation. Under the method, the data body is split with data input into a single bit digital delay circuit which outputs a delayed or "previous" binary data bit. A "present" binary data bit is input to one input of an XNOR circuit and the previous binary data bit is input into a second input of the XNOR circuit. When the present binary data bit and the previous binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value. When the present binary data bit and the previous binary data bit have like phases, the XNOR circuit outputs a second binary data bit value. Preferably, the demodulated data is input into a post detection filter.

Abstract: Digital FM demodulator and method in which zero-crossings of a frequency modulated input signal are detected, a binary pulse is provided for each of the zero-crossings, and the binary pulse stream is filtered digitally to provide enhanced resolution of the incremental phase (frequency) of the input signal over a period which is asynchronous with the input signal. In the disclosed embodiments, the digital filtering is done with comb decimation filters, with a higher order filter being employed where greater resolution is desired.

Abstract: A QAM demodulator that samples an IF input modulated with data at a fractional complex sampling rate between one and two times the data rate. The use of a fractional sampling rate significantly reduces the number of components necessary to implement the demodulator, particularly in the equalizer section of the demodulator which corrects for channel distortion. The fractional sampling rate demodulator architecture of the invention provides a significant reduction in integrated circuit surface area needed in a VLSI implementation.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier and then subjected to frequency conversion by a frequency converter including: an exclusive OR element; a running average generator consisting of a shift register and an adder; and a comparator. In response to the output of the frequency converter, the phase comparator outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator includes: an exclusive OR element; an absolute phase shift measurement means consisting of an adder and D flip-flop arrays and; and a D flip-flop serving as a phase shift polarity decision means.

Abstract: A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of the digital phase detector is coupled to an analog summing circuit having an output which is coupled to a low pass filter (LPF). The analog output of the LPF is coupled to the input of a voltage controlled oscillator (VCO) which produces a data rate clock. The output of the digital lock detector is coupled to an analog summing circuit having an output coupled to a low pass filter (LPF). The output of the LPF is coupled to a comparator for generating a lock indication signal output. The output of the comparator is also coupled to a sweep circuit which is coupled to an input of the voltage controlled oscillator for resolving frequency uncertainties in the bit synchronizing circuit.

Abstract: To demodulate an analog signal having information modulated by a carrier, the analog signal is chopped by a chopper, the chopped signal is digitized by a sigma-delta analog-to-digital converter to produce a series of digital samples at a sampling frequency, the digital samples are filtered in a digital decimating filter to produce data words, and the data words are modulated by an intermediate frequency signal to produce a detected information signal. The various frequency signals are generated by a phase-lock loop so that the intermediate frequency is the difference between the carrier frequency and the chopping frequency, and both the chopping frequency and the intermediate frequency are sub-multiples of the sampling frequency.

Abstract: A demodulator for demodulating a binary frequency-modulated signal includes a demodulator with a quadrature tank circuit and a duty cycle monitor circuit. The quadrature tank circuit has a voltage-controllable resonant frequency for compensating for shifts in the carrier frequency of the incoming signal and shifts in the tank circuit component values so as to allow the use of a high-Q tank circuit and thereby maximize use of the incoming signal energy. The quadrature tank circuit is a reactive circuit (with both inductive and capacitive elements) which includes a varactor diode having a voltage-controllable capacitance. The duty cycle monitor circuit measures the duty cycle of the demodulated binary output from the demodulator, and provides a control voltage to the quadrature tank circuit for adjusting its center frequency of operation.

Abstract: An FSK radio receiver of direct conversion type, which derives baseband in-phase and phase quadrature signals from a received FSK RF signal in respective mixers by applying local oscillator signals to the mixers differing in phase by 90.degree., in which wide-band baseband 90.degree. phase shifting circuits formed of only digital logic elements phase shift the in-phase and phase quadrature signals to enable a demodulated digital data signal to be obtained by subsequent digital processing. In that processing, signals having a frequency that is double that of the in-phase and phase quadrature signals are derived and used to derive the demodulated data signal, ensuring high accuracy of detection and lowering the accuracy required for the local oscillator frequency.

Abstract: In the modulation and demodulation of a plurality of frequency separated channels on a radio frequency carrier by digitally coded speech or data, the speech or data is modulated on a digitally generated sub-carrier by quadrature phase shift keying and after conversion to analogue form the modulated sub-carrier is mixed with an RF carrier of fixed frequency to produce the signal for transmission. Reception and demodulation of the transmitted signal are effected by the reverse processes. Frequency multiplication is effected after the digital to analogue conversion by producing analogue samples of very short duration and applying them to a suitable filter. Frequency division during the analogue to digital conversion is effected by sub-sampling.

Abstract: AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is v

Abstract: A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.