Abstract: Multiple clocks are interconnected in a network which is fed and controlled by a clock generator. A delay of one or more clock periods less a fixed amount is imposed between any two such clocks excluding the clock generator, to cause the repeated clock so transferred to occur at the appropriate time in the next cycle. Feedback using such delays assures bounded phase differences among these clocks. Thus, skew bounds can be provided for large numbers of clocks, to provide a bounded delay among multiple clocks. There is inserted in each link between a pair of clock nodes a delay line that delays a propogating clock signal by just enough time to cause the repeated clock to occur at the appropriate time in the next cycle, thereby synchronizing the appearance of that clock signal at the various nodes. Self-oscillation of the system, if the clock generator is removed, is avoided by having the delay between any two directly connected nodes be greater than one period of that clock generator.

Abstract: Processing of dispatch calls in a simulcast multi-site communication system begins when a source communication unit transmits a message to one or more network receivers. The received signals are analyzed at the received sites to determine a signal quality metric. Each of the signals are time stamped to identify when they where received. The received signals are transported with their time stamp and signal quality metric to each of the other sites via a digital communication network connecting the sites. Each transmitter site performs a transmit operation by first determining the receiver source with the best quality signal as indicated by the signal quality metric. The determined best quality signal is stored until it is time to transmit the signal in phase with all the other transmitter sites in a simulcast manner. The time stamp allows a time in the future to be chosen to accommodate the worst case expected transport delay through the digital network.

Abstract: Processing of dispatch calls in a simulcast multisite communication system (100) begins when a source communication unit transmits a message to one or more network receivers. The received signals are analyzed immediately at the received sites for signal quality (508). Each of the signals are time stamped (510) to identify when they were received. The signal quality is then compared to the signal quality of previously transmitted highest quality signals (514). If the signal quality is of higher quality than previously transmitted highest quality signals (516), the received signals are transported with their time stamp and signal quality metric to each of the other sites via a digital communication network connecting the sites (522). Each site now performs a transmit operation by first determining the receiver source with the highest quality signal as indicated by the signal quality metric (606).

Abstract: A synchronizing circuit comprises a plurality of substantially identical modules for receiving respective asynchronous input signals and respective local clock signals with the local clock signals of the respective modules being substantially synchronized. Each module of the synchronizing circuit comprises a de-metastabilizer stage, a global synchronizing stage and a majority edge detector and voter network. The de-metastabilizer stage receives the input signal of the module and provides an output signal free of glitches and metastable conditions, synchronized to the local clock signal. The global synchronizing stage receives the output signals of the de-metastabilizer stage of each module and provides respective output signals synchronized to the local clock signal. The majority edge detector and voter network receives the output signals of the global synchronizing stage and outputs a voted output signal synchronized to the other modules' voted output signals and to the local clock signal.

Abstract: A real time clock synchronizing system, provided in each of a plurality of network elements in a synchronous transmission network, comprises: a generating unit for generating, based on a reference clock, self-generated real time information indicating a real time of the network element. The system also includes an extracting unit for extracting reference real time information contained in an overhead area of synchronous signals received by the network element. A selector unit selects as a reference real time information to be transmitted from the network element, one of the self-generated real time information and the reference real time information extracted by the extracting unit. A transmitting unit contains the reference real time information selected by the selector unit, in an overhead area of synchronous signals to be transmitted from the network element.

Abstract: A protocol for transferring audio data and control/status data between audio functional units. The protocol involves multiplexing the audio data and control/status data. The multiplexed data is then transferred between a first audio unit and a second audio unit on two wires, each corresponding to the direction of data flow, and according to a clock rate and a synchronization pattern on third and fourth wires respectively.

Abstract: A digital controller provides digital signals to audio modules; the digital signals include both clock signals and data. All of the logic circuits of the controller and of the modules are clocked on the receipt of a rising edge. However, to avoid interference from regular clock pulses, the clock pulses are altered to have a variable mark-space ratio which means that the clock pulses arrive at random times and have random widths and thus appear to be randomized. Use of randomized clock signals can avoid tones appearing in an audio system, and also avoids interference effects in other electrical systems. The use of randomized clock signals is particularly helpful when designing digital circuits which meet current regulations controlling electromagnetic emissions.

Abstract: Determining transmit time of a received signal in a simulcast multi-site communication system begins when a communication unit transmits a message to one or more network receivers. The receivers transport the received signal with a time stamp to a master transceiver in the network via a digital communication network. The master transceiver then determines a launch time for transmission of a selected received signal, wherein the launch time is based on a previously executed procedure to determine the inbound and outbound delays in the simulcast multi-site communication system. Finally, the master transceiver transports the selected received signal with the launch time to other transceivers assigned to the call, wherein the transceivers transmit the selected received signal at the launch time.

Abstract: A communication system (100) provides simultaneous synchronization between a network controller (106) and numerous radio ports (102) using a single signaling channel. The network controller (106) includes a multiframe synchronization generator (208) which generates a multiframe synchronization packet (302) in response to a series of counters (212) and a timing reference (202). Each radio port (102) includes a multiframe synchronization detector (410) which verifies that the multiframe synchronization packet (302) is error free.

Abstract: An apparatus and method synchronizes a communication frame of a newly added base station, in a Time Division Multiple Access (TDMA) communication network, to communication frames in the existing communication network of base stations by operating the newly added base station to receive down link signals of a neighboring active base station and synchronize its receive slot in the communication frame with a corresponding forward time slot of the communication frame of that base station. The receive time slot of the newly added base station is shifted by an offset reference time to establish it own forward time slot. The offset reference time is determined by the time interval required for the base station to change from a forward to a reverse channel.

Abstract: A world-wide cellular radio telecommunications system utilizing low-earth orbit satellites provides secure transmissions of voice and data even though the length of the signal path of the communications link is dynamic. Crypto-algorithm generators at each end of a communications link are synchronized during a predetermined period of time after the initiation of communications. The crypto-algorithm generators are utilized to encrypt and decode, respectively, transmissions only after the expiration of the predetermined period of time.

Abstract: A network control system for eliminating a relative error among control signals transmitted from nodes provided in radio zones respectively, a mobil station moving among the radio zones, each of the nodes comprising: a relative error detecting unit for detecting a relative error between an after-controlled transmitting control signal to be transmitted to adjacent nodes and a received control signal from an adjacent node; and a control unit for controlling a before-controlled transmitting control signal in such a way that the relative error becomes zero so as to output the after-controlled transmitting control signal.

Abstract: A network control system for controlling a plurality of nodes respectively corresponding to, and provided in, a plurality of radio zones. Each node has a corresponding base station, where a mobil station travels among the plurality of radio zones and communicates with the base station of a respective node when travelling in a radio zone corresponding to the respective node. Each base station transmits a transmission signal for the corresponding node to adjacent nodes, receives transmission signals transmitted from the base stations of adjacent nodes and spatially filters the received transmission signals.

Abstract: A fixed system receiver (107), which includes a forward receiver (305), a reverse receiver (310), and a response timer (215), is for use in a radio communication system (100) having a forward radio channel and a reverse radio channel. A command is transmitted in a forward channel radio signal to a selective call transceiver. The forward receiver (305) is for receiving, demodulating, and decoding the command. The reverse receiver (310) is for receiving and demodulating the reverse channel radio signal. The response timer (215), which is coupled to the forward receiver (305) and the reverse receiver (310), is for determining a response period beginning substantially at a scheduled response time included in the command and having a duration which is substantially a designated length of the data unit included in the command, and for generating a control signal which enables the reverse receiver (310) during the response period.

Abstract: This invention provides a method for substantially reducing the time drift f a network clock in a frequency hopping communications system, without the need for a master unit to keep network time. The automatic network time tracking mechanism of each receiver is disabled when a network time update is received within a critical period of time from the closest synchronization update time or frequency hop time. The critical period is defined as the time between the closest synchronization update time to the local time when reception occurs less one-half the minimum tracking adjustment of the receiver plus the minimum processing or decoding delay, and that closest synchronization update time plus one half the minimum tracking adjustment of the receiver plus the maximum processing or decoding delay.

Abstract: A method and an arrangement for synchronizing two more individual communication networks of the time multiplex type, in order to form a composite network thereof, wherein the individual networks having nodes, in which cyclic transmission of time frames is performed, which include time slots intended for the data transmission. One node in the composite network is assigned the role as a superior master node determining the transmission speed of the individual communication networks. This is obtained by adding a fixed idle pattern to each time frame set out from the superior master node, followed by a fixed triggering pattern as a start of the next time frame. At the receipt of the triggering pattern at a master node in an individual communication network, which synchronizes the data transmission of the communication network, the master node starts sending a new time frame.

Abstract: Circuitry for switching between a first and second clock signal is provided having a first local clock circuit 202, a first synchronizing circuit 200 connected to said first clock circuit 202, a first delay circuit 206a-d connected to said first synchronizing circuit 200 and said first clock circuit 202, a second delay circuit 206e, 210, connected to said first delay circuit 206a-d and said first clock circuit 202, a first logic circuit 220 connected to said first 206a-d and second 206e, 210 delay circuits and said first synchronizing circuit 200, a second local clock circuit 102, a second synchronizing circuit 100 connected to said second clock circuit 102, a third delay circuit 106, 108, 110, connected to said second synchronizing circuit 100 and said second clock circuit 102, a second logic circuit 104 connected to said second clock circuit 102 and a portion of said third delay circuit 106, 108, 110, a third logic circuit 120 connected to said third delay circuit 106, 108, 110, and said second clock circui

Abstract: In a wireless TDMA network a control module (CM) sends a time stamp relative to the beginning of its frame in a synchronization packet allowing each of a plurality of user modules (UM) to maintain synchronization relative to the CM. The CM uses a plurality of directional antennas and transmits the synchronization packets over each antenna over a predetermined number of frames. The UMs use a receive time stamp to identify the beginning of a received synchronization packet. The difference between the time stamps combined with a delay constant is used by the UMs to adjust time synchronization to the CM frame.

Abstract: A network control system for controlling a plurality of nodes respectively corresponding to, and provided in, a plurality of radio zones. Each node has a corresponding base station. A mobil station travels among the plurality of radio zones and communicates with the base station of a respective node when travelling in a radio zone corresponding to the respective node. Each base station transmits a transmission signal to adjacent nodes and receives transmission signals transmitted from the base stations of adjacent nodes.

Abstract: Methods for provision of a sequence of timing signals for one or a plurality of microprocessors, microprocessor peripheral devices or other timing-controlled instruments ("users"), using timing signals determined from a Satellite Positioning System (SPS), such as GPS or GLONASS. In a first embodiment, one or a plurality of users is individually provided with SPS signal antennas and receiver/processors, and timing signals are optionally individually for each user. The timing signals can be periodic, for example, a One-Pulse-Per-Second signal for fine corrections of high frequency timing signals issued by an internal or external clock. The timing signals can also be substantially non-periodic. The timing signals may also be used to determine the time at which selected events occur, such as issuance of interrupt commands in, or directed to, a microprocessor.

Abstract: A method of mobile station synchronization to a system time, wherein the time alignment is attained while the mobile station operates in analog mode. The mobile stations transmits a periodic signal, each period of which has a leading edge. The base station detects the leading edge of the periodic signal and compares it to an indication of system time. The base station generates an error message for the mobile station indicating an update to the phase of the periodic signal. When the mobile station and the base station are time aligned, the base station may send a message indicating the absolute time at some future leading edge of the periodic signal thereby eliminating ambiguities of time due to the finite time required to receive the message.

Abstract: A method for a synchronizing user devices (12) performing handoffs includes providing a set of location synchronizing frequencies and data frequencies selected from a hopping set used by network access points (14). Each AP transmits synchronizing data (36) at the synchronizing frequencies during a portion of a short dwell (32), the short dwells (32) being interleaved between long dwells (30). When a user device (12) attempt a handoff, it tunes to at least one of the synchronizing frequencies and receives synchronizing information (36). The user device (12) then selects one AP (14) for link transfer and synchronizes its operation to the hopping set used by the selected AP (14).

Abstract: A timing recovery apparatus for asynchronous residual time stamping is disclosed. The timing recovery apparatus is placed at the timing domain boundaries for extending the use of synchronous residual time stamping into a new timing domain and for calculating the value indicative of the number of complete source network clock cycles in a predetermined time period which is loaded into a counter. When the counter reaches a predetermined value, a latch connected to a further counter contains a new residual time stamp value.

Abstract: A radio frequency backbone communication system is offered for exchanging, a plurality of communicated signals between a central site (205) and a plurality of communication units (16-18) through a plurality of remote base sites (60-66). The system includes at least one mobile function transceiver (201-204) located at the central site (205), transceiving a communicated signal of the plurality of communicated signals on a shared communication resource of a base site of the plurality of base sites (60-66) and, means for synchronizing a transceiver at the base site to the communicated signal of the at least one mobile function transceiver (201-204).

Abstract: An apparatus and method for clock rate matching in independent networks is disclosed. The apparatus accepts data from a modem (126) into a buffer (400) and determines the difference between the rate of the data entering the buffer (400) at the modem clock rate to the rate of data exiting the buffer (400) at the clock rate used by the apparatus. Depending on the rate difference, the apparatus either speeds up or slows down the data rate accordingly.

Abstract: A multipoint-to-point CDMA communication system comprises a plurality of CDMA transmitting stations and a single CDMA receiving station, all of which are intercoupled to each other over one CDMA channel and one feedback channel. On the one CDMA channel, the plurality of CDMA transmitting stations simultaneously send respective CDMA signals to the receiving station. In the receiving station, respective time differences are measured between a reference clock signal and the spreading codes in the CDMA signals from each of the CDMA transmitting stations; and these time differences are indicated in respective error signals which the CDMA receiving station sends on the feedback channel to each of the CDMA transmitting stations. Each CDMA station responds to its error signals by time shifting its spreading code such that it arrives in the receiving station in synchronization with the reference clock signal.

Abstract: A wireless digital telephone system containing at least one emulated base station plus one or more subscriber stations, the emulated base station comprising a station similar to the subscriber station but having the capability of initiating a synchronization process whereby it is enabled to assign time slots to the subscriber station within the frame pattern of an amplitude signal by means of monitoring for positive edges in the signal.

Abstract: Processing of message transmissions from any node in a simulcast multi-site communication system (100) begins when an initiating communication unit requests (400) to transmit a message to one or more network transceivers. After the request has been assigned by a call processing controller, the initiating unit transports (401) a time stamp message to each transceiver via a digital communication network (202). Each transceiver, after receiving the time stamp message, calculates (402) an outbound delay time and transports the outbound delay time to the initiating unit via the digital communication network. From the outbound delay time, the initiating unit calculates (406) a launch time, wherein the launch time accommodates the worst case expected transport delay through the digital communication network. The message to be transmitted and the launch time is transported to each of the transceivers, such that each transceiver simultaneously transmits the message at the launch time.

Abstract: A radio system has a control center for providing signals for transmission to a plurality of radio transmitters, each connected to the central source by a digital data link. A delay equalizer measures the variable transfer delay of each data link and adjusts the transfer delay of the transfer links to equalize the transfer delays to transmitters, so that the signals from the control can be transmitted from the transmitters substantially in time synchronism.

Abstract: A clock signal distribution system for a digital electronic system operating at high clock speed and short cycle times distributes a primary clock signal which is of relatively low frequency through conventional hardware. A high frequency secondary clock signal is generated using a phase locked loop to maintain high accuracy synchronization with the primary clock. Delay means are provided for both the primary and secondary clock signals to provide compensation of propagation time or to provide desired offsets. The phase locked loop arrangements with delays can be cascaded to provide flexibility of both frequency and phase of signals throughout the system, any or all of which may be maintained in synchronism with the primary clock. A dynamic digital transfer function generator is also used within the phase locked loop to achieve particular synchronization functions.

Abstract: CODECs and various other types of communication devices require timing information to enable them to transmit and receive digital information at the proper time. In the case of multiple CODECs on a single integrated circuit, this has typically required devoting terminals to provide separate transmit and receive frame synchronization pulses for each CODEC. Alternatively, a microprocessor interface may be included so that internal registers can be loaded with transmit and receive timing information. However, that approach limits timing flexibility. In the present invention, a "frame synchronization separation pulse" (FSEP) provides the separation in time between transmit and receive synchronization pulses. In this manner, the number of integrated circuit terminals required for synchronization may be reduced.

Abstract: A clock synchronous serial information transfer apparatus, comprises, a control signal circuit 6 which inputs a clock CLKin, and judges that the same level has continued over a predetermined time to output the judging result as two complementary control signals CLKa and CLKb, latch circuits 9a to 16a operated by a control signal which outputs a high level when the clock CLKin inputted to the control signal circuit 6 has kept the high level, and latch circuits 9b to 16b operated by a control signal which outputs the high level when the clock CLKin inputted to the control signal circuit 6 has kept a low level, whereby data is transmitted and received correctly even when noises occur in the clock CLKin.

Abstract: In a method of synchronizing nodes of a private telecommunication network to the best available clock at all times, each node of the network is normally synchronized by externally originated clock signals which reach it via a point-to-point digital transmission link input. Two node inputs are preselected as main and backup master clock inputs and each node is selectively preselected as a potential supplier of clock signals to each of the nodes to which it is connected by one of its master clock inputs, the nodes of the private network interconnected in this way determining a synchronization tree. In the event of loss of clock signals an exchange of information is instigated between adjacent nodes to reconfigure the synchronization tree that these nodes constitute so that each of them is synchronized to the best available clock.

Abstract: A method and apparatus provide an equalization time delay to synchronize a plurality of paging transmitters in a simulcast paging system. A delay equalization circuit (41 ) appropriate for use with an analog input signal includes a coder/decoder (CODEC) (50) and a digital signal processor (DSP) (58). An analog input signal is digitized or sampled by an analog-to-digital converter (ADC) in the CODEC, producing corresponding digital values that are input to the DSP. The DSP employs a selected finite impulse filter to interpolate between the sampled digital values from the CODEC to provide enhanced resolution in delaying a signal output that is output. The DSP determines a major sample index and an interpolated filter index to achieve the desired equalization time delay. These variables define two delay intervals that are combined to provide the required equalization time delay.

Abstract: A clock signal recovery and synchronization method for the reception of information elements transmitted by an ATM network and a device for the implementation of this method. The clock signal recovery is done by the reception of data elements by means of a local clock signal HL with a frequency equal to the frequency of transmission, the rephasing of the data elements being done only after a wait for the presence, on one and the same phase signal, of several fronts or edges of phase signals of the transmitted data that are coherent with a clock pulse HL and by choosing, as a rephasing signal, the phase signal that meets this condition and that frames the clock pulse. The resynchronization is done by the recognition of the resynchronization word with, possibly, a correction of errors in this word.

Abstract: A method and an arrangement minimizes skew in digital synchronous systems. The arrangement includes N number of driver circuits, each of which has a P number of buffer units, of which each has an input and an output. Each driver circuit has a delay of .delta..sub.1, .delta..sub.2, .delta..sub.3, .delta..sub.4 . . . .delta..sub.N. Of these buffer units, N-1 buffer units are reserved while the inputs of the remaining buffer units P-(N-1) are connected mutually in parallel. The reserved buffer units are used as follows. A signal deriving from a signal source is applied to an input of a first buffer unit in each of the N-number of driver circuits, where the signal is subjected to a delay. The one-time delayed signal from a driver circuit is then delayed once, and only once, in the reserved buffer units of each of the remaining driver circuits. This procedure is repeated for each of the once-delayed signals on the outputs of the first buffer unit in each of the remaining N-1 driver circuits.

Abstract: The present invention involves a device for synchronizing the broadcast frequency of a base station and a microcell linked together by a metallic medium as well as a method for using the device to synchronize the base oscillator and the microcell oscillator. The device comprises a base transmitter which transmits a base time-of-day signal to a microcell comparer, and a microcell clock which sends a microcell time-of-day signal to the microcell comparer. A microcell oscillator provides the microcell clock with a reference frequency. The microcell comparer calculates a time difference which represents a time difference between the base time-of-day signal and the microcell time-of-day signal. The microcell comparer then outputs a correction signal to a digital controller. The digital controller adjusts a microcell oscillator according to the correction signal.

Abstract: An apparatus for controlling synchronization in a system having at least first and second units each having internal circuits includes signal paths through which a control signal output from a second unit is sent to a first unit and a control signal output from the first unit is sent to the second unit. A first preparatory process part carries out a process to place the internal circuits of the second unit in an operating state when the second unit is connected to the system and for outputting a control signal to the signal paths. A first function mask control part is provided for stopping the operation of the internal circuits of the second unit when a control signal from the first unit is not received by the second unit, and for restarting the operation of the internal circuits when the control signal is received.

Abstract: A frequency synchronous circuit has a first selection unit, a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first selection unit is used to select one sampling signal from a first sampling signal having a first sampling time and a second sampling signal having a second sampling time shorter than the first sampling time. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during the sampling time of the selected one sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the selected one sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit.

Abstract: A synchronous optical digital transmission system comprises a local interface unit having a phase locked loop circuit that senses and adjusts the phase of the clock signals arriving from the remote unit to match the phase of the principal or local clock so that arriving data bit streams can be directly applied to the local system for further processing. The system is also designed to transmit and receive high speed and low speed data over a single fiber operating in a diplex mode without adverse crosstalk effects by employing non-standard line coding techniques.

Abstract: A frequency synchronous circuit has a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during a sampling time which is defined by a sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit. The comparison unit, which is connected to the storage/average unit and the second counter unit, is used to compare an output signal of the storage/average unit with an output signal of the second counter unit, and the frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of the comparison unit.

Abstract: Four QCIF video input signals generated by participants in a multiparty video conference are combined in the coded domain to produce a merged CIF video output signal. When the CIF video output signal is transmitted back to each party's video terminal, a combined 2.times.2 image is displayed. A video signal combiner (700) combines the input video signals in the coded domain by time-division multiplexing the inputs at the GOB level. In order to maintain frame synchronization between the inputs which may be arriving at different frame repetition rates, the combiner stores the inputs in buffers (706-709) and processes (710) the temporal reference (TR) numbers associated with each frame in each input before merging the GOBs from each input in accordance with the processed TR number. Specifically, the TR of each input is offset by an initial TR number associated with each input and determined at turn-on. The offset TR in each input is then mapped onto a scale of TR numbers that is common to each input.

Abstract: A local network system is provided using ATM-like framing and cells for data transmission. A bus architecture is defined, making the cost per port relatively low compared to matrix switching. For high performance, the bus is bit parallel instead of being a serial link. Like other LANs, the average bandwidth per interface (per port) is a low percentage of the peak bandwidth. A single physical bus is used to interconnect a potentially large number of ATM interfaces, on the order of hundreds. The system employs a bus master which provides timing and resolves all arbitration requests. Interfaces connected to the bus are allotted at least one cell per frame for sending data, and write to the allotted cell in synchronization with the frame, cell and bit clocks circulated on the bus from the master.

Abstract: Data transfer between subsystems of an information handling system employing a multiple subsystem clock environment architecture, or between multiple information handling systems operating with different clock frequencies, is synchronized using a timing aligned multiple frequency synthesizer with a synchronization window decoder. A frequency generation circuit in circuit communication with a data synchronization circuit functions to produce a synchronized timing signal(s) to permit a central processing unit operating in one subsystem clock environment to function with a peripheral subsystem(s), such as a memory controller, operating in a different subsystem clock environment, or permits information handling systems operating with different clock frequencies to function with one another. Data transfer synchronization delays are reduced and mean-time-to-failure of signal synchronization accuracy is increased by eliminating metastability effects from the synchronization circuitry.

Abstract: Synchronization apparatus in interconnected units of a data processing system resynchronize received bits from a bus with the internal clock of the unit. The synchronization arrangement has two identical synchonization devices which alternately process received strobe pulses which are used for sampling data bits into a first register, generating a gating pulse on one output and a validation pulse on a second output. In response to the gating pulse, bits stored in the first register are transferred to a second register to be available for use by processing logic in synchronism with the internal clock signal. The synchronization devices include two parallel synchronization circuits operating in opposite phase so that the detection of one strobe pulse by one circuit: automatically disables the other one.

Abstract: An optical clock distribution method and apparatus is disclosed that minimizes clock skew in the distribution of clock signals to logic assemblies in a computer system. The logic assemblies convert the optical signals into equivalent electrical signals.

Abstract: A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.

Abstract: A system for controlling traffic in a digital communication network to avoid data loss due to congestion utilizes both credit-based and rate-based traffic control approaches within a common framework, and adjusts the rate at which data is transmitted from a source in accordance with feedback in a form of credit values from a destination reflecting the ability of the network to transmit data and the destination to receive data. In one embodiment, the destination receives the information about network congestion, and, knowing its own capacity to receive more data, generates a credit in the form a numeric value which is fed back to the source so that the source adjusts its transmission rate to avoid data loss due to congestion in the network.

Abstract: A digital switching system comprises a plurality of digital interface cards for connection to a public telecommunications network, each card including at least one digital interface circuit with a synchronization detector for detecting a network synchronization signal. A control unit includes a system clock having a clock synchronization input. A a system bus carries data through the switching system and is connected between the interface cards and the control unit. A switch in the interface cards is operative in response to control data from the control unit and carried over the system bus in an overhead channel to connect the synchronization detector of a selected active digital interface circuit to the clock synchronization input of the system clock over a clock synchronization line so as to pass detected synchronization signals on the active circuit directly thereto. The system clock can thus be brought directly into synchronization with the detected synchronization signal of the active interface unit.

Abstract: A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency, have a different phase, and are shifted one clock period apart. The clocking signals are transferred over a first set of signal lines of equal length and impedance to computing systems components that are connected to a synchronous bus. Each component includes at least one clock repeater chip to convert the clocking signals (e.g., change these signals to a 5 volt CMOS level) to a different format. The converted clocking signals are then transferred over a second set of signal lines of equal length and impedance to the gate arrays. The gate arrays includes direct drive circuitry that receives the converted clocking signals and transmits these signals to internal driver circuitry. These signals are transferred over low skew lines.