Abstract: Automatic switching between clock sources in synchronous networks is accomplished using Synchronous Status Message transmitted over the network and a control circuit positioned between SASE (Stand Alone Synchronization Equipment) and a network element (SDH-NE, Synchronous Digital Hierarchy Network Element).

Abstract: In a method for radio communication of exchanging a transmission signal, which has been modulated by a prescribed method based on information data, between plural communication terminals and controlling the plural communication terminals by a control terminal, the control terminal generates a first code sequence to synchronize with the plural communication terminals, and transmits it to the plural communication terminals. The communication terminal synchronizes with the control terminal based on a reference timing obtained by receiving the first code sequence, generates a second code sequence representing the demodulation timing for the transmission signal and transmits it to another communication terminal out of the plural communication terminals, and then transmits the transmission signal to the other communication terminal.

Abstract: The present invention provides a PHS mobile radio station, which can efficiently attain resynchronization when the wave interference between radio control signals sent from base stations (BS) occurs and no synchronization therebetween cannot be established. The PHS mobile radio station of the present invention has a memory unit for latching the time difference between the transmission times of control signals through logical control channels respectively corresponding to two control frequencies.

Abstract: The present invention is a method for adjusting a timing of at least one first base station to maintain synchronization with a neighboring base station. An estimation of a timing accuracy associated with each said at least one first base station with respect to said neighboring base station is determined. For each of the first base station having its timing accuracy over a threshold, a first message to transmit a communication burst is received by the first base station. The communication burst is then received by the neighboring base station and a measurement of an estimated time difference between the first base station and the neighboring base stations in response to a second message is made. The first base station's timing is then adjusted in response to the measurement.

Abstract: When a route hub receives device data synchronized with a device reference clock set in a source device connected to the route hub from the source device, the route hub modulates the device data to communication data synchronized with a transmission reference clock; adds a phase information to be used to demodulate the modulated communication data into the device data, to an empty area which is equivalent to a difference between a number of bits of each unit block of the device data and a number of bits of each unit block of the communication data synchronized with the transmission reference clock, at the time of the modulation.

Abstract: Repeater units in a stack are identical. Each repeater unit has an internal repeater and an internal bridge. The repeater stack is dual-speed, with each repeater connecting to a 10 Mbps (10M) backplane bus and to a 100 Mbps (100M) backplane bus in the stack's chassis. The internal repeater has a 10M repeater circuit that connects 10M ports to the 10M bus, and a 100M repeater circuit that connects 100M ports to the 100M bus. Ports are configured for either 10M or 100M operation. Data from 10M ports is repeated to all other 10M ports and to the 10M bus, but not to 100M ports or the 100M bus. Instead, a 10M port is connected to the internal bridge, which is also connected to a 100M port. The internal bridge stores and forwards packets to and from the 10M port and the 100M port. Only one internal bridge in the stack is configured to link the 10M and 100M ports. Other internal bridges are configured to connect a cascading port to the internal repeater. The cascading port is buffered by the internal bridge.

Abstract: A method and system integrated into and carried out in conjunction with a public transit vehicle arrival information system. The system of the invention comprises at least the receiver portion of a display module which is positioned adjacent a central computer and which provides a received signal indication to the central computer. The received signal indication is, within a fraction of a millisecond, the indicator for signal reception by all receivers in an entire transit system. The central computer uses the received signal indication to calculate the time delay between calculation of arrival times and receipt of the broadcast arrival time data at a plurality of remotely located display modules. The central computer then generates a correction signal which is queued for broadcast to the remote display modules and which instructs the display modules to subtract the calculated time delay from the previously transmitted arrival time.

Abstract: A serial communication system for two IC devices has a separate master chip connected to both of the IC devices, the master chip having a clock generator and circuitry for affecting serial data transmission and control between the master chip and the devices. There is a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. In a preferred embodiment all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip. Also in a preferred embodiment each slave periodically checks phase between data stream and clock stream received, and inserts a correction code in the data stream sent back to the master chip, so the master chip can regularly correct the phase for clock and data sent to each slave.

Abstract: A method and apparatus for controlling bit slips in a high-speed, two-way, communications channel. More particularly, the entire communications system, comprising, inter alia, a receiver, a transmitter and the physical communications channel is operated as a feedback loop. That is, the detection of bit slips is performed continuously in the receiver and a bit slip signal is generated that indicates the number of bit slips and the direction, i.e., forward or backward, of the bit slip. Thus, the bit slip signal is communicated to the transmitter and certain actions are performed to introduce bit adjustments in the bit stream to eliminate the effects of any future bit slips. The bit slip signal contains an indication of the number of bit slips which have occurred, the time between bit slips, and the direction of the slip. As a function of this information from the bit slip signal, bit adjustments are made in the communications stream to correct for the bit slips and mitigate any effect in future transmission.

Abstract: Synchronization is effected in a cellular telecommunications network (20) between a master timing unit (60) located at control node (30) of the network and a slave timing unit (STU) located either at the control node or a controlled node, e.g., base station (22), of the network. In accomplishing the synchronization, one of the master timing unit or the slave timing unit serves as an initiating timing unit for transmitting a synchronization analysis command message including a first parameter (t1) to the other of the timing units which serves as a responding timing unit. In response, the responding timing unit sends a synchronization analysis response message which includes at least second parameter (t2) and preferably a third parameter (t3) to the initiating timing unit. The initiating unit uses e.g., parameters extracted from the synchronization analysis response message to determine a synchronization adjustment value for the slave timing unit.

Abstract: An apparatus which can achieve a synchronous dubbing and can record new data at a position just after data previously recorded without an unnatural gap and without using a buffer memory with large capacity. A reference signal from a cylinder servo circuit/tape transport servo circuit of a transmitter is converted into an isochronous packet. The packet is sent out from a digital interface transmitting circuit to a 1394 cable. On the reception side, an isochronous packet converter circuit restores a received isochronous packet into an original reference signal and sends it to the cylinder servo circuit/tape transport servo circuit. By so doing, the transmitter and the receiver are synchronized with each other, and it becomes possible to achieve a synchronous dubbing and to record new data at a position just after data previously recorded without an unnatural gap. Then the transmitter sends out dubbing data and the receiver receives it.

Abstract: A mobile radio (10) with a synchronization apparatus (14) executes a method (60) for time synchronizing the radio (10) and a base station (12). Base station (12) and radio (10) have internal timers (26, 16). A control unit (18) in the radio (10) receives a signal (29) from the base station (12) and determines the difference F between timers (26, 16, 30) in the base (12) and mobile (10). The control unit (18) writes instructions I(i) and their execution times T(i) to a memory (42) within the radio (10). One of these instructions I(N) reloads the radio timing counter (30) with a corrected value C=f(F,B) at a predetermined time T(N)=B which avoids conflicts with other operations of the radio (10).

Abstract: A two-way multi-carrier transmission system, such as a DMT system. If there are dynamic changes in the transmission parameters, synchronization must be maintained between the transmitter and the receiver when the transmission parameters changed. The first stage of such a process requires that the changes of parameter be notified by one transceiver to others involved in an active communication process over a slow transmission channel such as the control channel. Subsequently, the synchronization transceiver is adjusted simultaneously, i.e., from a predetermined DMT symbol. Such adjustments in time synchronization must be achieved with a minimum of overhead.

Abstract: To synchronize clock signals in spatially distributed nodes in a large, synchronous electronic, optical, optoelectronic or wireless system, a master node generates two identical pulse trains and propagates them to a plurality of slave nodes via first and second propagation channels, respectively, so that a pair of pulses, one from each pulse train, arrive at each slave node simultaneously, travelling in opposite directions. Each slave node generates a clock signal event when the pair of pulses arrive substantially simultaneous. When the pulses in the two channels do not arrive simultaneously, the slave node adjusts delays in each propagation channel so as to adjust arrival times of subsequent pairs of pulses. The delays may comprise pre-delays upstream of the detection point and post-delays downstream of the detection point, any increment in a pre-delay being compensated by an equal decrement in the post-delay in the same propagation channel.

Abstract: An apparatus for and method of serially transmitting a message between first and second devices coupled to a data or clock line in a process control device is disclosed. A first transition of the data or clock signal is generated during a signal cycle. A second transition of the signal is generated during the first signal cycle in order to control the duty cycle of the signal during the first signal cycle. If the duty cycle of the signal during the first signal cycle has a first value, then the first signal cycle is representative of a first data state transmitted between the first and second devices. If the duty cycle of the signal during the first signal cycle has a second value, then the first signal cycle is representative of a second data state transmitted between the first and second devices.

Abstract: The present invention is a system and method for time synchronizing a plurality of base stations in a wireless communication system. The system determines an estimate of a timing accuracy associated with each base station. When a base stations's timing accuracy is over a threshold, the system determines if there is a neighboring base station with a better timing accuracy. The base station over the threshold is adjusted in response to an estimated difference between that base station and the neighboring base station.

Abstract: A clock control system in a network switching node including an internal reference clock of a low level Stratum and receiving a plurality of high level Stratum clocks (CLOCK 1, CLOCK 2, CLOCK n) from connection lines, one of these high level Stratum clocks being currently used to generate a Master Clock; the device selecting another high level Stratum clock when the clock currently used to generate the Master Clock fails and comprising for each high level Stratum clock, means (12, 16, 20) for phase locking the reference clock on the selected high level Stratum clock and obtaining a plurality of phase locked (PLL) reference clocks (SOURCE 1, SOURCE 2, SOURCE n).

Abstract: A synchronous network having a multiplicity of nodes which can transmit data to one another in a predefined sequence for a predefined duration is described. The described network is distinguished by the fact that a plurality of nodes, or all the nodes, can output a synchronization signal which defines a reference time for the synchronization of the nodes.

Abstract: A method of synchronizing a base station and a remote station is presented. The base station is communicatively coupled with the remote station and a reference network. The base station clock signal is compared with a reference clock signal derived from the reference network and adjusted accordingly. The adjusted base station clock signal is then used to generate timing information in the form of a preamble, which is periodically transmitted from the base station over a wireless communication network to the remote station where a clock signal is generated. The remote station compares the clock signal with the timing information and adjusts the clock signal accordingly. This is done without reference to an external clock.

Abstract: The invention relates to the provision of a means for preventing interference and the occurrence of “sliding collisions” when two or more DECT communication systems are used in relatively close proximity The invention provides for the connection of the DECT systems to a data communication network along which a timing reference signal is carried such that the DECT systems connected to the network are synchronised. In one embodiment further steps can be taken to adapt the timing reference signal to take into account changes in the distance from the respective DECT systems to the data communication system head end at which the timing reference is generated.

Abstract: SYNC parsing for Cable Modem Clock Synchronization is implemented using software processing with hardware assist in a manner that achieves the cost benefits of software SYNC parsing with the time accuracy of hardware SYNC parsing. Hardware scans for the arrival of new MPEG frames. Whenever any MPEG frame arrives, the NPEG frame is processed to extract MAC packets. If a SYNC packet is discovered during this processing, the software determines the SYNC arrival time, a comparison is made between the time the SYNC arrival time and the SYNC time value, and the software uses the difference to adjust the Cable Modem clock. Implementation variations include different approaches to when timestamps are recorded, the calculation of the SYNC arrival time, the use of software to process the MPEG frame and MAC packets, and the use of software to perform the time comparison.

Abstract: In a multiplex transmission method, a plurality of digital signals having different frame lengths and bit-synchronized at the same signal rate are transmitted after the signals are multiplexed in a predetermined order. The received multiplexed signal is demultiplexed. A predetermined sync pattern is detected from each digital signal obtained by demultiplexing. The output position of each digital signal is determined on the basis of the sync pattern detection result. A multiplex transmission system is also disclosed.

Abstract: Users or subscribers of a spread spectrum synchronous communications system provide signals to the central station or base unit of that system, and receive signals therefrom. Proper synchronization among those users (and their signals) is needed to ensure proper operation of the system. To ensure proper synchronization among those users, the signal produced by each user is checked for presence and amount of any offset error. This is accomplished by using three despreaders for the signal for each user. For one such user, each such despreader for that user receives the spreading code for that user. However, the spreading code as received by any one such despreader is time-delayed with respect to the spreading code as received by the other two despreaders. Each such despreader receives the spreading code with a different amount of delay imposed on that spreading code. The outputs of the three despreaders are digitally combined (e.g. compared), or compared, to produce the offset estimate for that user.

Abstract: Memory modules and a controller are arranged and two clock lines are provided to go and return along the arrangement of the memory modules and the controller. A first basic clock and a second basic clock having twice the cycle period of the first basic clock are transferred over the go portions of the respective clock lines to the memory modules and the controller. After passing through the turnaround point, the first and second basic clocks are transferred as return clocks over the return portions of the clock lines to the memory modules and the controller. The first and second basic go clocks and the first and second basic return clocks are fed into the memory modules and the controller. The input/output operation of data is controlled synchronously with these clocks.

Abstract: A mechanism for synchronizing transmission of frames in a telecommunications network comprising a mobile station (MS), a radio network controller (SRNC), at least one base station (BS1, BS2). The mobile station (MS) and each base station (BS1, BS2) have a corresponding timing reference (MSFN, BSLFN, BS2FN). The mechanism comprises or performs the steps of 1) establishing a connection-specific timing reference (CFN) which is common to all nodes (MS, BS1, BS2, RNC) involved in the connection; 2) determining, for the base stations (BS1, BS2) an offset (OFS) between the timing reference of the base station in question and the CFN; and 3) using the offset (OFS) in the base stations (BS1, BS2), to compensate for the difference between the timing references.

Abstract: The invention relates to a synchronization method in a telecommunication system that includes a transmitting unit, a receiving unit and a transmission link between these two. The information to be transmitted in the telecommunication system is transferred from the transmitting unit to the receiving unit in a data frame that includes an information section and a synchronization section. The bits of the synchronization section are in each consecutive data frame always in the same state as in the previous data frame, and the synchronization section consists of at least one synchronization bit in a selected logical state. In the method, the transmitting and receiving units of the data frame are mutually synchronized with synchronization bits.

Abstract: The invention relates to a method for creating a synchronization network in a telecommunications network, comprising several nodes (D . . . M) interconnected with links and sending synchronization status messages indicating the quality level of the corresponding signal relative to the synchronization. At least one master clock (PRC) is used as a synchronization source for the network nodes, and the synchronization network is established by selecting, in accordance with a topology defined by the links, synchronization chains formed by successive nodes, through which chains the signal of at least said main clock is distributed to the nodes in the chain, and by defining for the different nodes in the chain a node-specific priority list including node interfaces at different priority levels, determining the synchronization source to be selected by the node when signals of equal quality levels are received on the node connections.

Abstract: Methods and systems are provided which store frequency settings before switching frequencies, for example, before assignment to the traffic channel when switching between a ground station and another mobile station), thus, making it possible to recall the previous frequency setting and then only perform a second pass of the synchronization process or no synchronization at all. By storing the frequency setting, either as an offset to a given frequency or as an absolute frequency for each system to be monitored, the stored frequency setting can be re-used when subsequently monitoring a system.

Abstract: The present invention provides methods of transmitting information within a personal handy-phone system wireless local loop and personal handy-phone system wireless local loops. One embodiment of a personal handy-phone system wireless local loop according to the present invention comprises: a base station; a repeater station configured to transmit a plurality of uplink radio signals to the base station and receive a plurality of downlink radio signals from the base station; and a portable station configured to transmit the downlink radio signals to the repeater station and receive the uplink radio signals from the repeater station.

Abstract: Symmetrical cross coupled PLL circuits provide pseudo-synchronization between two independent clock signals, especially for use in fault tolerant applications. Independent oscillators provide input signals to each of the PLL circuits. The PLL circuits include divide circuitry that provide output signals at some sub multiple of the input clock signals. The phase relationship between the output clock signals from the cross coupled PLL circuits is monitored by phase detector circuits. If the phase of one output clock signal is determined to be advanced relative to the other output clock signal, the phase of that output clock signal is retarded by temporarily increasing the divide ratio of the PLL circuit producing the phase advanced signal.

Abstract: An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal.

Abstract: The present invention is directed to managing power consumption in a wireless frequency hopping communication among a plurality of nodes. For example, the present invention is directed to features such as reducing power consumption of an individual node within a wireless communication system by powering on the transmitter/receiver of the node only when actual transmission/reception is required.

Abstract: A radio communication apparatus capable of solving a problem involved in a conventional apparatus in that in addition to a first receiver, a second receiver must be provided for establishing synchronization with a contiguous base station, which causes an increase in a circuit scale and consumed power of a mobile station. The present radio communication apparatus switches, when carrying out handoff from the current base station to a contiguous base station, a receiving frequency of a receiver from the frequency of the current base station to that of the contiguous base station, and a counter to be corrected by a synchronization manager from a first counter to a second counter that is used to establish synchronization with the contiguous base station.

Abstract: A method and apparatus for synchronizing a clock between first and second logic blocks (20,21) connected via an asynchronous bus (22). The second logic block includes a clock signal generator (9) responsive to an input synchronizing signal to generate a clock signal synchronized with the synchronizing signal. Data is transferred in blocks from the first logic block (20) to the second logic block (21) across the asynchronous bus (22), the receipt of a data block by the second logic block (21) being used to generate the synchronizing signal.

Abstract: An approach for synchronizing operation of a first communications terminal with operation of a second communications terminal involves establishing a communications link between the first communications terminal and the second communications terminal, the communications link being defined by a communication standard; and synchronizing a first clock coupled to the first communications terminal with a second clock coupled to the second communications terminal by receiving a time standard signal into the first communications terminal independently of the communication standard. This approach can be implemented using a first clock; a first communications terminal coupled to the first clock; a second clock; a second communications terminal coupled to the second clock; a communications link defined by a communication standard; and a transmitter transmitting a time standard signal independently of the communication standard to the first clock and setting the first clock in response to the time standard signal.

Abstract: An apparatus and method for receiving a bitstream containing timing information and respective program information, the program information is processed and associated with locally generated timing information to form an output bitstream, the locally generated timing information is synchronized to the received timing information so that the timing relationships of the received program information are preserved even after the program information is processed.

Abstract: A wireless digital telephone system containing at least one emulated base station plus one or more subscriber stations, the emulated base station comprising a station similar to the subscriber station but having the capability of initiating a synchronization process whereby it is enabled to assign time slots to the subscriber station within the frame pattern of an amplitude signal by means of monitoring for positive edges in the signal.

Abstract: A method of switching a communication channel when a mobile station moves from one service area to another service area is disclosed. The mobile station determines a difference between the transmission phase of a frame synchronizing signal received from a first base station currently holding a communication channel with the mobile station and the transmission phase of a frame synchronizing signal received from a second base station expected to newly set up a communication channel with the mobile station. The mobile station sends phase difference information representative of the above difference to the first base station via the communication channel. The first base station having received the phase difference information transfers the information to the second base station, causing it to correct the phase of data thereof to be sent to the mobile station. This successfully implements soft handover while guaranteeing the phase synchronization of frames sent from the two base stations.

Abstract: A wireless digital telephone system containing at least one emulated base station plus one or more subscriber stations, the emulated base station comprising a station similar to the subscriber station but having the capability of initiating a synchronization process whereby it is enabled to assign time slots to the subscriber station within the frame pattern of an amplitude signal by means of monitoring for positive edges in the signal.

Abstract: In a method of synchronizing a local oscillator to a main oscillator signal in a network, the local oscillator signal has a phase shift relative to and upon appearance of the main oscillator signal. The phase shift is used as a reference phase shift between the local oscillator signal and the main oscillator signal to synchronize the local oscillator signal. Initially the reference phase shift is fixed.

Abstract: As part of a preferred communication protocol, base stations which are synchronized to a PSTN of a wireless communication network, periodically transmits a preamble. A remote detects the preamble and, upon verification of the data contained in the base station transmission, sets its counter to an initialized state based on the received preamble. An early/late analysis of each subsequently received base station timing pulse is used to adjust both the mobile station timing and to adjust the output frequency of the mobile station master clock and codec clock to effectively maintain end to end synchronization with the respective base station and the PSTN throughout the duration of an established communication link.

Abstract: A local clock used for synchronizing events in an industrial control system may be synchronized with a master clock according to synchronization signals received at a first period. Updating of the local clock is performed on a more frequent basis than the receipt of the update signals. By using the update signals to derive an error value which is incrementally applied to the clock at a much higher rate, the maximum deviation is reduced. The system works with clocks having discrete frequency outputs by adjusting the update rate so as to effectively produce a continuously variable output frequency for the local clock over an interval equal to the update rate.

Abstract: An improvement to a half duplex multipoint communication environment wherein a pilot tone enables a control modem to maintain synchronization with a plurality of remote modems. By employing a VCXO in a remote modem, a low jitter timing pulse is generated thus allowing a control modem to maintain synchronization with a plurality of remote modems.

Abstract: A serial communication system for two IC devices has a separate master chip connected to both of the IC devices, the master chip having a clock generator and circuitry for affecting serial data transmission and control between the master chip and the devices. There is a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. In a preferred embodiment all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip. Also in a preferred embodiment each slave periodically checks phase between data stream and clock stream received, and inserts a correction code in the data stream sent back to the master chip, so the master chip can regularly correct the phase for clock and data sent to each slave.

Abstract: A digital cordless telecommunication system capable of maintaining the enhanced frequency stability of radio transmission signals from stationary base stations by use of a specific clock signal including either a high-precision clock or a reference clock as generated by main equipment.

Abstract: A clock signal distribution network for a high-speed microprocessor includes a clock synthesizer coupled to receive an externally generated clock signal. The clock synthesizer deskews the external clock to generate an internal clock signal, which is then distributed about the semiconductor die by a conductivity tree. A set of local deskewing clock generators are coupled to branch interconnects of the tree and function as a zero-delay buffers for driving proximally located circuitry.

Abstract: A selective call device (106) for monitoring at least two communication systems. The selective call device (106) has a receiver (204) for receiving information from a first communication system (110), a processor (206) for referencing a time slot assignment on the first communication system (110) to a common time base. The processor (206) calculates timing information relating a common time base and a transmitter (222) transmits the timing information to the second communication system (120) informing the second communication system (120) when to transmit information to the selective call device (106) with reference to the common time base.

Abstract: A synchronization message detecting unit detects a synchronization message from a line signal received from a line terminating unit. A synchronization message processing unit controls whether or not to select a clock reference received from the line as an active reference according to a quality level represented by the synchronization message. In this case, when an installed state detecting unit has determined that the synchronization message detecting unit has not been installed, the synchronization message processing unit does not select a clock reference corresponding to the synchronization message detected by the synchronization message detecting unit determined as a non-installed unit as the active reference.

Abstract: A clock distribution apparatus with active phase alignment which makes the incidence of a timing event occur essentially simultaneously at multiple physically remote destinations. The circuit uses traces configured as reflective transmission lines with a matched impedance input. The propagation time of a transmission line is determined by monitoring the current into the transmission line. Variable delays are determined for each transmission line by measuring the actual propagation time and reducing a predetermined maximum delay time by that amount. The variable delay values are stored and used to retard clock edges by the varying amounts so that all clock edges arrive at respective remote destinations at a time equal to the maximum delay time.

Abstract: A modem that operates reliably at a symbol rate that corresponds to twice its bandwidth even when it is coupled to a receiving A/D converter that operates under control of a clock is realized by synchronizing the modem's operation to the A/D's clock. The superior operation of this modem advantageously extends to A/D clock frequencies beyond the frequency of twice the modem's bandwidth. To minimize quantization noise, the modem's output is conditioned to minimize intersymbol interference by adjusting the modem's output to the A/D converter's sampling times and slicing levels. When the A/D's clock is higher than twice the bandwidth of the modem's output signal, some intersymbol interference cannot be avoided. In accordance with this invention, the position and value of this interference is computed at the receiver and subtracted from the received signal.