Abstract: Received signals are digitized by a comparator, and sampled by regenerated clock signals synchronized to a carrier. Biphase symbol data are demodulated based on the sampling data. A biphase decoder circuit performs subtraction of the biphase symbol data to be paired. The subtraction result is compared with threshold values by data judgment circuitry which then judges inversion of the biphase signals to be paired. An RDS-ID detector circuit detects inversion of RDS signals by detection of either continuity or a ratio of signals received for a certain length period. Alternatively, RDS signals are detected by stability of output from the pair judgment circuit to detect a combination of biphase symbols.

Abstract: Before digital data impulses are transmitted from a transmitter to a receiver that includes a data acquisition signal generator, at least one synchronizing impulse (syn1, . . . ) is transmitted for synchronizing the transmitter with the receiver with regard to a sync frequency that is repeatedly updated to provide a current accepted sync frequency. The at least one synchronizing impulse and the data impulses are Manchester encoded which combines timing (synchronizing) and data signals. An impulse flank change occurring centrally in an impulse width is used as a synchronization point of time. Stepping pulses occurring between two consecutive synchronization points of time are counted and the resulting count is used to determine the sync frequency in response to the occurrence of a synchronizing impulse and at a synchronization point of time. A time shift or delay occurs between data impulses and synchronization points of time.

Abstract: Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a post-mixer tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The MOSFET-implemented resistance is controlled by the same control current that establishes the output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and independent of absolute processing parameters and temperature.

Abstract: An improved acquisition and tracking system for Global Positioning System (GPS) signals. The system relies on block adjustment of the synchronizing signal of the bi-phase shift keying (BPSK) signal in order to obtain correct carrier frequency and phase angle. This improved system has the advantages of being more robust in the presence of noise than conventional approaches and also of lending itself to simplified implementation since synchronization of the Coarse/Acquisition (C/A) code need only be within half of a chip in order to maintain lock.

Abstract: Disclosed is a clock extraction circuit for extracting a clock signal which furnishes timing for discriminating a data signal, from the data signal. The clock extraction circuit has a timing extraction unit for extracting the clock signal from the data signal, and a filter, which is provided in front of the timing extraction unit, having an upper limited frequency sufficiently lower than the bit rate of the data. The data signal is input to the timing extraction unit via the filter.

Abstract: A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Abstract: An encoding system including an encoder that Manchester encodes a data value to produce a coded data value and produces a first invalid Manchester encoded sequence as a start of frame. Also produced is a second invalid Manchester encoded sequence as an end of frame. A transmission packet is produced including the start of frame followed by the coded data value followed by the end of frame. The start of frame is a sequence of "110110" and the end of frame is a sequence of "001000".

Abstract: A delay-locked loop which phase-locks the reference clock of crystal oscillation by certain identical delay units for generating certain precise time-sharing phase signals. These time-sharing phase signals can be utilized to recover the clock/data. The advantages of the invention, when comparing with the typical phase-locked loop, are: (1) it can be easily stabilized; (2) the phase error does not accumulate; (3) the loop filter requires only one capacitor, which reduces the area of chip; (4) no additional loop filter is need in multiport application, which further reduces the area of chip.

Abstract: A data receiver is arranged to receive data comprising a sync word having a predetermined data frequency (f.sub.tx) and predetermined value. A clock signal (SCLK) is generated which is substantially synchronised with the received data. The n clocks (CLK1-CLK8) are generated, each of the n clocks having a frequency (fclk) which is substantially the predetermined data frequency (f.sub.tx) and is out of phase with an adjacent clock of the n clocks by 1/n of a clock period. The sync word is sampled using each of the n clocks to determine which one of the n clocks is optimally synchronised with the sync word and to provide the determined one of the n clocks at an output (18). The determined one of the n clocks provides the clock signal (SCLK).

Abstract: A clock encoding circuit, e.g., for Manchester encoding, for high speed data transmission (IEEE 1394) and a circuit for controlling data and encoded clock transmission. The clock encoding circuit includes two parallel to serial shift registers, a DATA register and a STROBE register, receiving data in parallel and shifted out at 100 MHz, 200 MHz or 400 MHz. The STROBE register receives every other bit of the data inverted. When both registers are clocked at the data transmission rate, data is shifted out of DATA register and the transmission clock is encoded in STROBE, shifted out of the STROBE register. Bit inversion may be with invertors receiving data as it is passed to the DATA register, or alternatively, after it is loaded into the DATA register. The circuit for controlling DATA and STROBE transmission includes the clock encoding circuit, a frequency matching register array and a loopback shift register.

Abstract: A data decoding circuit of the present invention can regenerate a bit synchronization signal from a data received by using a code such as a split-phase code and Manchester code in which a binary value can be detected through a transition of voltage at a central area of a bit cell and transform the received data into a serial binary data. The data decoding circuit includes an edge detection section for detecting a transition point in the received data; a pulse generating section for generating a phase comparing timing signal having a pulse width of substantially 1/(4.times.fs) when fs is a data transfer frequency and a received data regenerating signal having a pulse width of substantially 1(2.times.

Abstract: A method of phase synchronization of a bit rate clock signal generated on a receiver side with a biphase-modulated digital RDS signal that is demodulated on the receiver side with both signals having the same bit rate. The bits of both the RDS signal and the bit rate clock signal are each composed of two half bits having different digital potential values. The first or the second RDS half bit has a high digital value and the other RDS half bit has a low digital value based on which one of two logic values "1" and "0" is represented by the respective RDS bit. At a first time coinciding with the time of a rising and/or falling edge of a bit of the RDS signal, the digital value of the bit rate clock signal is measured as a first sample value, and at a second time shifted from the first time by a delay time that is shorter than a half bit duration, the digital value of the bit rate clock signal is measured as a second sample value.

Abstract: A data and clock recovery circuit includes a front end circuit for receiving a data signal encoded with a Manchester or other bi-phase level code having a sequence of bit frames, and for outputting a recovered data signal and a recovered clock signal in accordance with transitions in the data signal that overlap with a window signal. A window generation circuit generates the window signal in accordance with a delay control signal, and includes circuitry that delays and transforms the recovered clock signal into the window signal. A delay control circuit generates and adjusts the delay control signal. A phase comparison circuit compares the recovered clock signal with leading and lagging portions of the window signal, and generates signals that adjust the delay control signal when the recovered clock signal overlaps with either of the leading and lagging portions of the signal.

Abstract: A circuit for decoding an input signal includes a measurement circuit having an input to receive a timing clock signal that is asynchronous with clocking of the input signal, to measure duration of a plurality of pulses received on the input signal in relation to frequency of the timing clock signal and a decode circuit to decode the input signal into digital data. In one embodiment, the circuit may include a servo mechanism for generating the timing clock signal to have a frequency that varies in response to variations in frequency of clocking of data on the input signal. The servo mechanism may include a digitally controlled oscillator and a feedback circuit, to control the digital frequency of the digitally controlled oscillator in response to variation of clocking of data on the input signal. The invention permits use of all digital components for decoding digital audio data encoding using biphase-mark encoded data according to the SPDIF or AES/EBU standards.

Abstract: A digital phase lock loop and system for data extraction and clock recovery of Ethernet data reduces power consumption, area, and noise sensitivity. In one aspect, a digital phase lock loop (PLL) includes a data extraction and end of transmission delimiter (ETD) circuit, an edge detection comparator coupled to the data extraction and ETD circuit, an up/down counter coupled to the edge detection comparator, and a phase adjustment oscillator coupled to the counter and to the data extraction and ETD circuit for producing phase adjustments in a reference clock signal in accordance with shifts in the frequency of the data. In a system aspect of the present invention, the system receives the data in a digital PLL circuit, and adjusts a phase of a reference clock and a sample clock to track transitions in the data through the digital PLL.

Abstract: The present invention relates to a data communication system (12) which includes a receiver (14) capable of receiving serially transmitted signals and generates a receiver enabled signal and received data signal in response. A phase locked loop (16) generates a recovered clock signal in response to the received data signal and a first circuit (20) generates digitized data symbols in response to received data signals and the recovered clock signal. A nibble packetizer (28) forms data packets from the digitized data symbols and synchronizes transmission of the data packets in response to the receiver enabled signal, the digitized data symbols and the recovererd clock signal.

Abstract: A bi-phase signal is output from BPSK demodulator; by a pair determining circuit and a clock reproducing circuit, a clock signal corresponding to a former half bit of two half bits constituting a data pair of the bi-phase signal is reproduced; a carrier pulse immediately following the clock signal is generated by a carrier extracting circuit; using the carrier pulse and a carrier pulse obtained by delaying the pulse signal by a half bit period as a sampling clock, the bi-phase signal is subjected to AD conversion by AD converting circuit; two AD converted data values different in time are input to a subtraction circuit, and a result of subtraction between data pairs of bi-phase signals is obtained; thus sign of a bi-phase signal is determined.

Abstract: A clock recovery unit for recovering a clock embedded in a data communication is disclosed. The clock recovery unit includes an oscillator (50) operating at a frequency close to that of the clock embedded in the data communication. The clock recovery unit also includes an edge detector (30) that produces a synchronization pulse with each transition in the data communication. The edge detector is coupled to the oscillator to force a transition in the oscillator in synchronization with the synchronization pulse produced by the edge detector. A start-up latch (10) that starts and stops the oscillator also forms part of the clock recovery unit. The start-up latch starts the oscillator at the beginning of the data communication, with no preamble bits required. For low-power consumption in stand-by mode, a counter (40) coupled to the start-up latch stops the oscillator after data has been determined not to be present for a preset period of time.

Abstract: A method and apparatus for recovering clock and data signals from a Manchester code is provided. The present invention uses a phase lock loop with a digital delay line wherein an adjustable delay is introduced into the Manchester coded signal for synchronizing the coded signal with the local clock of the decoding apparatus. This delaying technique enables the present invention to successfully receive Manchester coded signals having substantial jitter. The present invention also conserves energy by reducing power consumption when no signals are present.

Abstract: An optical wireless communication method and apparatus configured to distinguish optical LAN data from optical noise is disclosed. The apparatus communicates using Manchester coded data via a connector connected to a personal computer. The Manchester coded data from the computer are converted to NRZ transmission data to be temporarily stored and read out. A frame of the read out data is appended with a head leader, and end data, at the head and end of the frame respectively to be convened to the DMI transmission optical data. The optical data inserted between the head leader and END data are receivable and can be distinguished from optical noise. The DMI received data removed from the head leader and end data are convened to data of the Manchester code in contrast with the transmission side to be delivered as the Manchester data via the connector. As the optical data with the head leader and end data are distinguishable from optical noise, high sensitive optical receivers are available.

Abstract: A dual clock tracking decoder for use in a local station of a token ring local area network extracts the mostly repetitive bit-cell transitions corresponding to the imbedded clock of a received phase encoded message from which a short term and a long term moving average estimate is made of the clock transitions relative to a local stable clock. The short term moving average adjusts rapidly to short term jitter and is used to sample the received phase encoded message twice each bit-cell and generate an intermediate phase encoded message that is resynohronized with a clock derived from the long term moving average of the estimated imbedded clock transition and having a rate that is twice the bit-cell rate of the received phase encoded message. This provides a mechanism for sampling the states of the incoming message with a clock that is adaptive to fast short term jitter while restoring an imbedded clock that is only responsive to slow longer term jitter.

Abstract: The circuit and method for detecting data collisions in a communication network, the circuit including: a data transition detecting section for receiving Manchester encoded data signals RXD, and detecting a transition at the center of the bit cell of the encoded data signals, and outputting a transition detecting signal Z having a certain pulse width; a delayer for delaying received clock signals RXC having a certain cycle synchronized with the received data signals RXD, and outputting delayed clock signals DRXC; and a data collision detecting section turning to an active mode in accordance with a data receiving status signal CRS illustrating the receiving status of the received data signals, and shifting the status of output signals in accordance with the transition detecting signal Z upon clocking of the delayed clock signal DRXC.

Abstract: A digital audio signal demodulator which demodulates an input digital audio interface format signal inputted with asynchronous serial bits to a non-return to zero (NRZ) signal, corrects error per frame, and provides the error-corrected NRZ signal, being synchronized with a digital-to-analog conversion control signal. According to the demodulator, data in the digital audio interface format signal except a header region is demodulated in a demodulating section and the demodulated NRZ data is converted into parallel NRZ data by a serial-parallel conversion section. The even parity error of the parallel NRZ data is corrected in accordance with error check pulses from an error detecting and latch section, and the error-corrected parallel NRZ data is converted into serial data by a parallel-serial conversion section to be provided to a following digital-to-analog converter.

Abstract: A phase-locked loop circuit recovering original clock information and original stream of binary data both from Manchester-coded data is disclosed. The phase-locked loop circuit comprises first, second, and third exclusive-OR circuits each with two inputs and an output. The phase-locked loop circuit further comprises a controlled oscillator that generates two local clock signals that are phase shifted from each other, preferably by an amount of 90.degree., with the first being at 0.degree. phase shift. The 0.degree. clock signal is applied to one input of the first exclusive-OR circuit having Manchester-coded data at its other input. The 90.degree. phase shifted clock is applied to one input of the second exclusive-OR circuit having Manchester-coded data at its other input. The output of each of the first and second exclusive-OR circuits, after passing through associated circuitry, is applied to the third exclusive-OR circuit.

Abstract: An arrangement comprising a controllable clock signal source (1), a decision circuit (8) for determining the polarity of a received biphase signal at two successive sampling instants in a single symbol interval, and a phase detector (35) with a first comparator (16) to compare the polarity samples at the two sampling instants with each other. The phase detector generates a control signal for adjusting the frequency and phase of the adjustable clock signal source (1) in response to the output signal of the first comparator. A second comparator (28) compares polarity samples at the same relative sampling instant in two successive sampling instants with each other. The second comparator (28) inhibits phase detector (35) in response to the output signal of this second detector. In the case of false synchronization, the output of phase detector (35) will continue to present the same signal value, so that automatically an adjustment is made of the instant of correct synchronization.