Self-synchronizing Signal (self-clocking Codes, Etc.) Patents (Class 375/359)
  • Patent number: 10396803
    Abstract: A clock and data recovery (CDR) circuit operates to recover a clock and sample data from full-rate and sub-rate data signals. The CDR circuit selectively shifts one or more of the sampling clocks based on the rate of a received data signal, facilitating accurate sampling of sub-rate data signals. A masking circuit selectively masks data output bits clocked by a selection of the sampling clocks, thereby outputting relevant sampled data.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: August 27, 2019
    Assignee: Marvell International Ltd.
    Inventors: Scott E. Meninger, Ethan Crain, Mark Spaeth
  • Patent number: 10176824
    Abstract: Increasing the level of the consonant segments relative to the nearby vowel segments, known as consonant-vowel ratio (CVR) modification, is reported to be effective in improving speech intelligibility by listeners in noisy backgrounds and by hearing-impaired listeners. A method along with a system for real-time CVR modification using the rate of change of spectral centroid for detection of spectral transitions is disclosed. A preferred embodiment of the invention using a 16-bit fixed point processor with on-chip FFT hardware is also presented for real-time signal processing. It can be integrated with other FFT-based signal processing in communication devices, hearing aids, and other systems for improving speech perception under adverse listening conditions.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: January 8, 2019
    Assignee: Indian Institute of Technology Bombay
    Inventors: Prem Chand Pandey, Ammanath Ramakrishnan Jayan, Nitya Tiwari
  • Patent number: 9978395
    Abstract: A communication component modifies production of an audio waveform at determined modification segments to thereby mitigate the effects of a delay in processing and/or receiving a subsequent audio waveform. The audio waveform and/or data associated with the audio waveform are analyzed to identify the modification segments based on characteristics of the audio waveform and/or data associated therewith. The modification segments show where the production of the audio waveform may be modified without substantially affecting the clarity of the sound or audio. In one embodiment, the invention modifies the sound production at the identified modification segments to extend production time and thereby mitigate the effects of delay in receiving and/or processing a subsequent audio waveform for production.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 22, 2018
    Assignee: Vocollect, Inc.
    Inventors: Keith Braho, Russell A. Barr, George Joshue Karabin
  • Patent number: 9516595
    Abstract: Methods, devices, and computer program products for synchronization of wireless devices in a peer-to-peer network are described herein. In one aspect, a method for synchronizing a wireless communication apparatus is provided. The method includes receiving one or more synchronization messages, each synchronization message having timing information and a cluster identifier, the timing information comprising anchor timing information, the cluster identifier being the same value as a cluster identifier of the apparatus. The method further includes determining whether a difference between a time value when a received synchronization message last received anchor timing information and a time value maintained for the apparatus is greater than a threshold. The method further includes discarding the received synchronization message if the difference exceeds the threshold.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: December 6, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Santosh Paul Abraham, George Cherian, Alireza Raissinia, Guido Robert Frederiks
  • Patent number: 9482740
    Abstract: A data processor estimates the location of the receiver or estimated range from multicarrier signal. The data processor determines phase compensation data for each ranging subcarrier in the multipath signal. The phase compensation data comprises an adjustment to the estimated range based on a difference between an observed phase of the observed signal vector and a direct path phase of a direct path vector, where the direct path phase is estimated based on one or more prior measurements of a certain observed signal vector when an average amplitude of all (or a majority of) ranging subcarriers converge to substantially the same value.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 1, 2016
    Assignee: DEERE & COMPANY
    Inventor: Richard G. Keegan
  • Patent number: 9425779
    Abstract: A delay circuit may include a delay path including a fine delay line and a coarse delay line, a replica delay path including a replica fine delay line and a replica coarse delay line, and a tuning unit that compares a phase of a first signal obtained by delaying an input signal through the delay path with a phase of a second signal obtained by delaying the input signal through the replica delay path, and generates a tuning code in a tuning mode.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: August 23, 2016
    Assignee: SK Hynix Inc.
    Inventor: Inhwa Jung
  • Patent number: 9215676
    Abstract: A base station clock apparatus, a base station system, and a method for clock synchronization are provided in embodiments of the present invention. The base station clock apparatus includes: a first-standard clock module based on a first standard, configured to generate a first frequency synchronization clock signal, a first phase synchronization signal, and a first system clock signal according to a first external clock signal, where the first system clock signal includes the first frequency synchronization clock signal and the first phase synchronization signal; a second-standard clock module based on a second standard that is different from the first standard, configured to receive the first frequency synchronization clock signal and the first phase synchronization signal from the first-standard clock module, and generate a second system clock signal, where the second system clock signal includes the first frequency synchronization clock signal and the first phase synchronization signal.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: December 15, 2015
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Weidong Yu, Yuhong Chu
  • Patent number: 9042499
    Abstract: Radio frequency (RF) receivers having whitened digital clocks and related methods are disclosed. Disclosed embodiments generate whitened clocks having random variations that are used to operate digital processing blocks so that interference created by the whitened clocks is seen as white noise within the received RF signal spectrum. RF input signals are received by RF front-ends (RFFEs) that output analog signals associated with channels within the RF input signals. These analog signals are converted to digital information and processed by digital receive path circuitry that outputs digital data associated with the channel. The digital receive path circuitry includes a whitened clock generator that generates a whitened clock having random variations and which a digital processing block that operates based upon the whitened clock. Further, the RFFE and the digital receive path circuitry are located within a single integrated circuit.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: May 26, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Michael R. May, Scott T. Haban
  • Publication number: 20150117499
    Abstract: A method of generating a BOC correlation function based on partial correlation functions, an apparatus for tracking a BOC signal, and a spread spectrum signal receiver system using the same are disclosed herein. The apparatus includes a frequency offset compensation unit, a local code generation unit, a mixer, a delay lock loop (DLL), a phase lock loop (PLL), and a data extraction unit. The frequency offset compensation unit outputs a compensated received signal with respect to a received signal. The local code generation unit generates a delay-compensated local code based on a code delay value. The mixer mixes the delay-compensated local code with the frequency offset-compensated received signal. The DLL repeatedly tracks and calculates a code delay value. The PLL repeatedly calculates a carrier frequency compensation value. The data extraction unit extracts spreading data from a mixture of the delay-compensated local code and the compensated received signal.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Keun Hong CHAE, Seok Ho YOON
  • Patent number: 9020087
    Abstract: The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 28, 2015
    Assignee: Exar Corporation
    Inventors: Sadettin Cirit, Jose Antonio Salcedo
  • Patent number: 9021095
    Abstract: Disclosed is an improved approach for implementing an on-demand scheduler in a mobile device and the structures to support realtime on-demand schedulers. A lightweight word-based structure is disclosed for storing scheduling-related data on the mobile device. Using this lightweight word-based structure enables on-demand and real-time scheduling. This type of lightweight structure also permits scheduling activities to be performed in a disconnected mode, which can then be later synchronized with the server to confirm the booking In addition to appointment scheduling, this technique can also be implemented for scheduling of any type of resource.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 28, 2015
    Assignee: Oracle International Corporation
    Inventors: Hari Krishna Gutlapalli, Suhas R. Mehta
  • Patent number: 9014285
    Abstract: An object of the present invention is to provide a receiving apparatus and a receiving method capable of preventing phase rotation of a signal after FFT from occurring on a frequency domain. Further, the receiving apparatus according to the present invention is provided with: a window control unit configured to control a position of an FFT window in which FFT is performed to the time domain signal, and output FFT data corresponding to the FFT window; a signal delaying unit configured to generate, from the time domain signal, a plurality of delay signals with different delay amounts; and a signal switching unit having a switch for outputting by switching between two of the time domain signal and the plurality of delay signals based on a predetermined switch timing, the signal switching unit being configured to output the FFT data including the output signal of the switch.
    Type: Grant
    Filed: September 5, 2011
    Date of Patent: April 21, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukihiro Kadota, Takashi Fujiwara
  • Patent number: 8989298
    Abstract: In one embodiment, a data encoder for a component (such as an integrated circuit) may encode data to be transmitted from the component to another component in a system. The encoder may avoid one or more data patterns that, if transmitted by the component, may cause noise to occur at one or more specified frequencies (or frequency bands). The specified frequencies may be frequencies that are in use for wireless communication by the device. By avoiding noise at the specified frequencies, the desense that might otherwise occur may be reduced or eliminated. Quality and speed of the wireless communication may be increased.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 24, 2015
    Assignee: Apple Inc.
    Inventor: Christopher J. Herrick
  • Patent number: 8983012
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
  • Patent number: 8964922
    Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Matthew Felder, Mark Summers
  • Patent number: 8942300
    Abstract: A digitizer system (DS) may include one or more input channels to receive sample data, and an acquisition state machine (ASM) to organize the sample data into one or more acquisition records according to events of interest, and generate framing information corresponding to the one or more acquisition records. The events of interest may be identified by a trigger circuit in the DS, and relayed to the ASM for organizing the sample data. The DS may further include a data interface capable of receiving the one or more acquisition records and the framing information, encoding the one or more acquisition records and the framing information into encoded data, and transmitting the encoded data to an expansion module. The expansion module may receive the encoded data, decode the encoded data, and recover the sample data from the decoded data according to the framing information and the one or more acquisition records.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 27, 2015
    Assignee: National Instruments Corporation
    Inventors: Rafael Castro Scorsi, Kunal H. Patel, Hector Rubio
  • Patent number: 8923705
    Abstract: One embodiment is a Poisson-based communication system. The system includes a receiver that comprises a photodetector that receives photons and generates pulses based on the received photons, a sampling event counter that counts the number of generated pulses by the photodetector and a demodulator. The demodulator samples the sampling event counter at predetermined time intervals to determine an occurrence of a first state when light pulse energy has been transmitted by a transmitter and received by the photodetector and an occurrence of a second state when light pulse energy has not been transmitted by the transmitter and received by the photodetector.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Oliver W Saunders, Russell Kadota
  • Patent number: 8924449
    Abstract: A method for implementing variable symbol rate, presetting counters M and N, and M=1, N=0, f being the preset output symbol rate, fs being the frequency of input clock, the method comprises: triggering to judge whether N×f is greater than M×fs at the rising edge of the input clock, if it is, letting the counter M add 1 and outputting a clock pulse; else further judging whether the value of the counter N is equal to fs?1; when N=fs?1, letting the counter N return to 0, and waiting for the next rising edge of the input clock; when N?fs?1, waiting for the next rising edge of the input clock after letting the counter N add 1; letting the output clock pulse be the system clock, controlling the data to be output to set the symbol rate output.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 30, 2014
    Assignee: Shenzhen Coship Electronics Co., Ltd.
    Inventor: Wei Luo
  • Patent number: 8917759
    Abstract: A transceiver is described. The transceiver includes a first injection-locked oscillator and a second injection-locked oscillator. The transceiver also includes a first phase-locked loop coupled with the first injection-locked oscillator. The first phase-locked loop is configured to generate a first frequency reference. Further, the transceiver includes a second phase-locked loop coupled the second injection-locked oscillator. The second phase-locked loop is configured to generate a second frequency reference. The transceiver includes a mixer configured to receive the first phase-locked loop output and configured to receive said second injection-locked oscillator output. The mixer is also configured to generate a carrier frequency signal based on the first injection-locked oscillator output and the second injection-locked oscillator output. And, the transceiver includes a modulator configured to receive said carrier frequency signal.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 23, 2014
    Assignee: Innophase Inc.
    Inventor: Yang Xu
  • Publication number: 20140362961
    Abstract: Embodiments of a method and/or system of transmitting and/or receiving data is disclosed.
    Type: Application
    Filed: January 7, 2014
    Publication date: December 11, 2014
    Applicant: Robert T. and Virginia T. Jenkins as Trustees for the Jenkins Family Trust Dated Feb, 8, 20002
    Inventor: Jack J. LeTourneau
  • Patent number: 8907812
    Abstract: The present technology relates to protocols relative to utility meters associated with an open operational framework. More particularly, the present subject matter relates to protocol subject matter for advanced metering infrastructure, adaptable to various international standards, while economically supporting a 2-way mesh network solution in a wireless environment, such as for operating in a residential electricity meter field. The present subject matter supports meters within an ANSI standard C12.22/C12.19 system while economically supporting a 2-way mesh network solution in a wireless environment, such as for operating in a residential electricity meter field, all to permit cell-based adaptive insertion of C12.22 meters within an open framework. Cell isolation is provided through quasi-orthogonal sequences in a frequency hopping network. Additional features relate to apparatus (both network and device related) and methodology subject matters relating to uplink routing without requiring a routing table.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: December 9, 2014
    Assignee: Itron, Inc.
    Inventors: Hartman Van Wyk, Gilles Picard, Fabrice Monier, Arnaud Clave, Jerome Bartier
  • Patent number: 8902952
    Abstract: A method for acquiring a code phase shift between an input sequence and a reference sequence is provided. The method is to be implemented using an acquisition device that includes a mapping unit configured to transform the input sequence and the reference sequence respectively into an input signal and a reference signal each with a complex phase, a comparison unit configured to compare the input signal with the reference signal so as to obtain a phase coherent indicator, and calculating unit configured to obtain the code phase shift between the input sequence and the reference sequence based on a phase of the phase coherent indicator and a number of bits of the input sequence.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: December 2, 2014
    Assignees: National Chiao Tung University, National Applied Research Laboratories
    Inventors: Ming-Seng Kao, Chieh-Fu Chang, Wan-Hsin Hsieh
  • Publication number: 20140348280
    Abstract: A clock-embedded serial data transmission system is disclosed. The clock-embedded serial data transmission system includes a combinational logic circuit. The combinational logic circuit includes a clock window generator and a clock generator. The clock window generator is used to generate a first clock window according to two clock phases. The clock generator is coupled to a clock window generator and used to select a periodic data within the first clock window from a serial data signal according to the first clock window and generate a recovery clock accordingly.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Applicant: RAYDIUM SEMICONDUCTOR CORPORATION
    Inventor: Da-Rong HUANG
  • Publication number: 20140328442
    Abstract: A method comprising modulating a plurality of synchronized signals by an orthogonal probe sequence (OPS) to generate a plurality of modulated synchronized signals, wherein the OPS comprises a zero element (0-element) column that indicates a start or an end of the OPS, and concurrently transmitting, using one or more transmitters, the plurality of modulated synchronized signals over a duration of a number of discrete multi-tone (DMT) symbols, wherein each of the plurality of modulated synchronized signals is intended for one of a plurality of receivers that are remotely coupled to the one or more transmitters via a vectored group of subscriber lines, and wherein the 0-element column causes all of the plurality of modulated synchronized signals to have a zero-amplitude during a first or a last of the DMT symbols.
    Type: Application
    Filed: December 18, 2013
    Publication date: November 6, 2014
    Applicant: Futurewei Technologies, Inc.
    Inventors: Jianhua Liu, Amir H. Fazlollahi
  • Patent number: 8879680
    Abstract: A transmitting interconnect interface inserts clock mismatch compensation symbols into a transmitted data stream so as to allow the receiving interconnect interface to compensate for clock frequency mismatch between transmit-side and receive-side clocks. The transmitting interconnect interface adjusts the rate of insertion of these symbols based on a determination of the clock frequency mismatch. The transmitting interconnect interface can incrementally adjust the insertion rate to change substantially proportionally with changes in the clock frequency mismatch. Alternatively, the transmitting interconnect interface can set the insertion rate to one of two levels. By adapting the insertion rate to the current measured clock frequency mismatch, the bandwidth penalty incurred by transmitting clock mismatch compensation symbols in excess of that necessary to permit receiver clock tolerance compensation can be reduced, thereby permitting more transmit bandwidth to be used for transmitting data.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: November 4, 2014
    Assignee: ATI Technologies ULC
    Inventors: Michael Tresidder, Gordon F. Caruk
  • Publication number: 20140301514
    Abstract: A signal delay estimator includes an adjustable delay element for delaying a first signal to obtain a delayed first signal, a delay amount estimator for estimating a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal, and a leading signal determiner for determining whether the delayed first signal leads the second signal or vice versa, and for generating a corresponding binary signal. A selective inverter is provided for selectively inverting the delay amount depending on the binary signal. The signal delay estimator also includes a feedback element to the adjustable delay element for controlling a delay based on an output of the selective inverter. Another exemplary signal delay estimator includes a closed control loop with an adjustable delay element and separate first and second processing paths for absolute delay amount and delay direction, respectively.
    Type: Application
    Filed: June 23, 2014
    Publication date: October 9, 2014
    Inventor: Alexander Belitzer
  • Patent number: 8854550
    Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Pyeong Kim, Han-Kyul Lim, Cheon-Oh Lee
  • Patent number: 8848849
    Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 30, 2014
    Assignee: Avnera Corporation
    Inventors: Samuel J. Peters, Eric P. Etheridge, Victor Lee Hanson, Alexander C. Stange
  • Patent number: 8848835
    Abstract: An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventor: Takayuki Shibasaki
  • Publication number: 20140270028
    Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: Avnera Corporation
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hanson, Alexander C. Stange
  • Patent number: 8831159
    Abstract: One embodiment of the present invention relates to a method and apparatus for performing both phase modulation (PM) and amplitude modulation (AM) downstream of a controlled oscillator (e.g., by providing a baseband signal having no phase modulation to a controlled oscillator and performing phase modulation on a high frequency RF signal output from the oscillator), wherein the amplitude modulation is synchronized with the phase modulation. In one particular embodiment, the method and apparatus synchronize modulation of AM and PM signal paths in a manner that provides a polar modulated signal having an amplitude of zero at a symbol boundary (e.g., a transition between different symbols) having a phase of zero (e.g., a phase that crosses through a zero crossing point).
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: September 9, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventor: Grigory Itkin
  • Patent number: 8823562
    Abstract: A first multiplexer, at each given cycle, outputs a second input data signal, after outputting a first input data signal. A second multiplexer, at each given cycle, outputs a fourth input data signal, after outputting a third input data signal. The second multiplexer outputs the third input data signal at a timing that coincides with the timing at which the second input data signal is output from the first multiplexer. At each given cycle, a third multiplexer, after outputting the first input data signal and the second input data signal output from the first multiplexer, outputs the third input data signal and the fourth input data signal output from the second multiplexer.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: September 2, 2014
    Assignee: Fujitsu Limited
    Inventor: Shigeto Suzuki
  • Patent number: 8823451
    Abstract: Disclosed is a high-frequency signal processing device capable of reducing transmission power variation and harmonic distortion. For example, the high-frequency signal processing device includes a pre-driver circuit, which operates within a saturation region, and a final stage driver circuit, which operates within a linear region and performs a linear amplification operation by using an inductor having a high Q-value. The pre-driver circuit suppresses the amplitude level variation of a signal directly modulated, for instance, by a voltage-controlled oscillator circuit. Harmonic distortion components (2HD and 3HD), which may be generated by the pre-driver circuit, are reduced, for instance, by the inductor of the final stage driver circuit.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tomoumi Yagasaki
  • Patent number: 8817933
    Abstract: Methods and apparatus are presented for obtaining clock data from Manchester coded serial data streams, in which received data is sampled at a sample rate higher than the serial data baud rate, multi-bit groups of transition bits are generated which individually indicate data transition locations in a corresponding multi-bit sampled data bit group, and clock data is derived using the multi-bit groups of transition bits without requiring receipt of synchronization data or receipt of a separate clock.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: August 26, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Darshini H. Mehta, Alan Campbell
  • Patent number: 8811454
    Abstract: Provided are a method for dynamically acquiring a PN synchronization of a blink signal in a reader according to a channel state when a tag transmits a direct sequence spread spectrum (DSSS) blink signal having a predetermined period and the reader receives the blink signal in a 2.4 GHz RTLS system which complies with an ISO/IEC24730-2 standard, and a method for synchronizing a frame using a preamble.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: August 19, 2014
    Assignee: LSIS Co., Ltd.
    Inventor: Jae Wook Kim
  • Patent number: 8811559
    Abstract: A timing recovery circuit includes a clock generation circuit which generates clock signals having different periods in different modes, i.e., a first and a second operation mode, phase interpolation circuits each of which outputs a sample timing signal having a phase adjusted to fall between the phases of two clock signals in the first operation mode, and outputs one of the two clock signals as a sample timing signal in the second operation mode, sampler circuits which latch a data signal using the sample timing signals, and a phase control circuit which gives an instruction to select a clock signal or adjust the phase of a sample timing signal.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: August 19, 2014
    Assignee: Panasonic Corporation
    Inventors: Yukio Arima, Akinori Shinmyo
  • Patent number: 8798208
    Abstract: Disclosed is an apparatus and method for detecting a code. The code detecting apparatus may include a detector to detect symbol synchronous timing information associated with a PSS code from a first signal received during a predetermined first period, a compensator to extract and buffer the PSS code and the SSS code based on the symbol synchronous timing information detected from a second signal received during a predetermined second period, and compensate for a frequency offset with respect to the buffered PSS code, and a processor to re-detect the symbol synchronous timing information based on the PSS code in which the frequency offset is compensated for, and extract the buffered SSS code using the re-detected symbol synchronous timing information.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun Jeong Shin, Dae Ho Kim
  • Patent number: 8787513
    Abstract: Disclosed herein is a digital re-sampling apparatus. The digital re-sampling apparatus includes a sample buffer, a sample buffer control unit, a filter bank, a first delay bank, a fractional delay constant table, a combiner bank, and a second delay bank. The sample buffer temporarily stores an input sample in synchronization with an input sampling frequency. The sample buffer control unit controls writing and reading operations. The filter bank includes a number of digital filters equal to the number of stages, and filters the input sample. The first delay bank differentially delays a filter output value. The fractional delay constant table stores information about re-sampling time. The combiner bank includes a number of adders and multipliers, performs an operation, and outputs a re-sampled value. The second delay bank causes a delay so that output of each combiner can be synchronized with each output of the fractional delay constant table.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: July 22, 2014
    Assignee: Innowireless Co., Ltd.
    Inventors: Jinsoup Joung, Kyeongmin Ha, Joohyeong Lee
  • Patent number: 8781052
    Abstract: A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Bernard Arambepola, Shaul Shulman, Naor Goldman, Amos Klimker, Noam Tal
  • Patent number: 8781043
    Abstract: Techniques for recovering a desired transmission in the presence of interfering transmissions are described. For successive equalization and cancellation (SEC), equalization is performed on a received signal to obtain an equalized signal for a first set of code channels. The first set may include all code channels for one sector, a subset of all code channels for one sector, multiple code channels for multiple sectors, etc. Data detection is then performed on the equalized signal to obtain a detected signal for the first set of code channels. A signal for the first set of code channels is reconstructed based on the detected signal. The reconstructed signal for the first set of code channels is then canceled from the received signal. Equalization, data detection, reconstruction, and cancellation are performed for at least one additional set of code channels in similar manner.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: July 15, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Byonghyo Shim, Inyup Kang, Farrokh Abrishamkar, Sharad Sambhwani
  • Patent number: 8781048
    Abstract: An apparatus for synchronizing audio data and visual data and a method therefor are provided. The apparatus includes a splitter, a synchronization unit coupled to the splitter, an audio control unit coupled to the splitter and the synchronization unit, and a visual data processing unit coupled to the splitter and the synchronization unit. The splitter receives an application layer data frame including audio data and visual data and splits the visual data from the audio data. The synchronization unit receives audio timing information of the audio data and acquires synchronization information according to the audio timing information and external timing information. The audio control unit receives and temporarily stores the audio data and outputs the audio data according to the synchronization information. The visual data processing unit analyzes and temporarily stores the visual data and outputs the visual data together with the audio data according to the synchronization information.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 15, 2014
    Assignee: KeyStone Semiconductor Corp.
    Inventors: Shao-Hsuan Hung, Shih-Wei Chang
  • Patent number: 8774336
    Abstract: Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 8, 2014
    Assignee: TeraSquare Co., Ltd.
    Inventors: Hyeon Min Bae, Hyo Sup Won, Joon Yeong Lee, Jin Ho Park, Tae Ho Kim
  • Patent number: 8775701
    Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 8, 2014
    Assignee: Altera Corporation
    Inventor: Ryan Fung
  • Patent number: 8767900
    Abstract: A signal transition detection circuit is provided. The signal transition detection circuit comprises a counter module, a DAC, a comparator and a digital sampling module. The counter module generates a digital step signal. The DAC converts the digital step signal into an analog input signal and transmits it to an under-test circuit such that the under-test circuit generates an output signal transiting from a first stable level to a second stable level, wherein a transition section is located between the first and the second stable level. The comparator receives and compares the output signal with a default value to generate a normalized output signal. The digital sampling module samples the normalized output signal to retrieve impulses such that when the number of the impulses is accumulated to be larger than a reference value, a corresponding step of the digital step signal is determined to be a transition point.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Test Research, Inc.
    Inventors: Yu-Chen Shen, Kuei-Chang Yang
  • Patent number: 8750445
    Abstract: The present invention relates to a communication method, system and signal, and in particular to a method and system for communicating information in a digital signal. It has particular application to satellite or terrestrial packet-based multi-user radio communication systems. A method for communicating information in a digital signal comprising data symbols is disclosed, wherein the information is encoded in a sequence characteristic of pilot symbols distributed amongst the data symbols, such that a receiver is able to determine the sequence characteristic and retrieve the transmitted information. The invention allows information to be encoded into a sequence characteristic of pilot symbols, rather than relying on modulating such information onto the pilot symbols themselves. This allows a significantly larger number of pieces of information to be transmitted than hitherto possible, and the technique is more resistant to large frequency errors than prior techniques.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: June 10, 2014
    Assignee: EMS Technologies, Inc.
    Inventors: Michael Robert Peake, Mark Rice, Timothy Clifton Giles
  • Patent number: 8750444
    Abstract: A method for providing timing recovery from a received digital data stream where the digital data stream is a series of consecutive data samples. The method separates the data stream into a series of consecutive observation periods where each observation period includes the same number of consecutive data samples. The method also includes identifying a series of consecutive timing recovery data samples in each observation period where the timing recovery data samples are used for timing recovery and other data samples in the observation period are not used for timing recovery, and where the number of data samples used for timing recovery in each observation period is less than the number of data samples that are not used for timing recovery in the observation period. The method then uses the timing recovery data samples for timing recovery in each observation period.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: June 10, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Michael Paul Fitz, Scott Warren Enserink
  • Patent number: 8737552
    Abstract: A method of and apparatus for synchronous data transfer are described. The method may include encoding a clock period and data into an encoded signal, transmitting the encoded signal from a master device to a slave device, and recovering the data at the slave device without using a local oscillator. The apparatus may comprise a first integrated circuit including a master device configured to transmit an encoded signal of a clock period and data on a first port, and a second integrated circuit including a slave device where the slave device is configured to receive the encoded signal on a second port coupled to the first port and to recover the data without using a local oscillator.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: May 27, 2014
    Assignee: Xilinx, Inc.
    Inventor: Nicholas J. Sawyer
  • Patent number: 8723651
    Abstract: A method for detecting a pattern in a signal according to one embodiment includes determining a time between symbol transitions in a signal derived from a radio frequency signal; determining ratios of relational times between consecutive symbol transitions; and comparing a sequence of the ratios to a target pattern for determining whether the sequence corresponds to the target pattern. Such methodology may also be implemented as a system using logic for performing the various operations. Additional systems and methods are also presented.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: May 13, 2014
    Assignee: Intelleflex Corporation
    Inventor: Dean Kawaguchi
  • Patent number: 8724761
    Abstract: Provided is a symbol synchronization apparatus and method of a passive RFID reader. The symbol synchronization apparatus includes: an edge clock detector generating edge clocks by detecting phase inversion positions of a received signal; a preamble detector detecting a preamble section by analyzing the generation times of the edge clocks; a symbol decision time extractor extracting a symbol decision time by averaging distances between the edge clocks consecutively generated in the preamble section, when the preamble section is detected; and a symbol decider deciding a symbol by analyzing the magnitude of the received signal, when the time reaches the symbol decision time.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: May 13, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Ji Hoon Bae, Dong Han Lee, Kwang Soo Cho, Won Kyu Choi, Man Sik Park, Chan Won Park, Cheng Hao Quan, Gil Young Choi, Jong Suk Chae
  • Patent number: 8726062
    Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: May 13, 2014
    Assignee: Synopsys, Inc.
    Inventor: Jose Angelo Rebelo Sarmento