Abstract: A method and apparatus for determining synchronization and loss of synchronization in a high speed multiplexed data system. The system also includes a plurality of justification control bits and a backwards compatibility flag that allows the system to operate with older systems that have fewer justification control bits.

Abstract: The present invention relates to a synchronization method and to a system for establishing in a signal receiving unit (4) a time position of a significant bit position occurring among received information-carrying bit positions (40a, 40b) into which a predetermined number of uniformly distributed line-code related bit positions are inserted.

Abstract: Variable length LAN frames can be segmented into fixed length cells to allow the data in the frames to be transported through an intermediate cell-based system, such as an ATM network. Where transport through the intermediate system results in time gaps between data units extracted from the cells, special symbol combinations can be inserted into the time gaps to permit frame-representing data to be forwarded toward its destination as a "stretched frame" without waiting for all the cells representing the frame to arrive. When a stretched LAN frame is received at a "stretch-aware" LAN station, the special symbol combinations are detected and removed to recover at least the data payload of the original LAN frame.

Abstract: A wireless digital telephone system containing at least one emulated base station plus one or more subscriber stations, the emulated base station comprising a station similar to the subscriber station but having the capability of initiating a synchronization process whereby it is enabled to assign time slots to the subscriber station within the frame pattern of an amplitude signal by means of monitoring for positive edges in the signal.

Abstract: An encoder for encoding binary data bits supplied by a data source into pulse amplitude modulated multilevel symbols. The encoder includes a bit stuffer for receiving the data bits from the data source at a first data bit rate, which at most equals a maximum data bit rate. The bit stuffer then adds descriptive bits to the data bits at a descriptive bit rate, which at most equals a maximum descriptive bit rate. The encoder also includes a multilevel pulse amplitude modulator for receiving the data and descriptive bits from the bit stuffer and for converting the data and descriptive bits into pulse amplitude modulated multilevel symbols. When these multilevel PAM symbols are transmitted, they have a spectral energy characteristic which is below a predetermined low level threshold at a predetermined baseband bandwidth frequency. In addition, these multilevel PAM symbols have a symbol rate (i.e.

Abstract: An apparatus and method for converting a serial data signal into a parallel data signal based on sync signals contained within the serial data signal are provided. The serial-to-parallel data conversion apparatus includes a signal input end, a true sync signal identifier for individually identifying whether the sync signals contained in the serial data signal are true sync signals having the same positions as those of original sync signals, based on predetermined sync patterns, a false sync signal removal unit for removing from the serial data signal false sync signals which are sync signals that are not identified by the true sync signal identifier as true sync signals, and a clock generator for generating a clock signal for performing serial-to-parallel conversion of the serial data signal by using the sync signals contained in the serial data signal output from the false sync signal removal unit.

Abstract: A synchronous digital transmission system has network nodes each operating at a respective fixed internal clock rate, each with a justification device for adapting an incoming signal to the respective fixed internal clock rate thereof by positive or negative justification actions, and for controlling a memory device which stores payload bytes of a frame of the incoming signal and outputs the payload bytes at the internal clock rate of a respective network node. The justification device has a first circuit (10) for counting incoming/outgoing frame bytes and calculating at sampling instants (T.sub.i) a difference value (.DELTA..sub.i) and a change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i), has a second circuit (20) for calculating a control value (OFFSET) which is dependent on the change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i) and on a correction factor (LEAK), and has a third circuit (30) for comparing at the sampling instants (T.sub.

Abstract: A data receiving apparatus receives data into which a stuff pulse for frequency synchronization is inserted. The data receiving apparatus is provided with a frame alignment information detecting unit for detecting frame alignment information to establish a frame alignment from the received data, a stuff pulse insertion position detecting circuit for detecting the insertion position of the stuff pulse which has been inserted into the received data, and a frame pattern rearranging circuit for rearranging the frame pattern of the received data so that the insertion position of the stuff pulse is fixed at a predetermined position, on the basis of the detection output of the frame alignment information detecting unit and the detection output of the stuff pulse insertion position detecting circuit.

Abstract: A data transmission link is especially designed to meet new FCC regulations setting 5 KHz band widths for transmitting control signals to industrial systems. The new band width creates timing distortions which are overcome by inserting a new timing pulse into a data pulse stream. The center of that inserted timing pulse is taken as an axis of reference for retiming each pulse in the data pulse stream so that the fluctuations of a time frame synchronizing pulse become irrelevant. The retiming process is repeated for each data time frame.

Abstract: The invention provides a synchronous circuit which prevents occurrence of a step-out condition even when an error in padding occurs. The synchronous circuit is applied to a digital transmission system wherein the number of bits in a frame varies periodically and bit number information is included in a frame. Making use of the fact that the bit number information has a periodicity, bit number information for one period is generated by a padding bit generator based on information from a synchronism detector to prevent occurrence of a step-out condition caused by an error in received bit number information.

Abstract: A new data format used in a communication system employing binary phase shift keying modulation and demodulation is described. The data format provides for a frame comprising a plurality of variable data bits and synchronization bits. The number of variable data bits in the data format of the present invention is more than the number of synchronization bits. The data format preferably includes a CRC field for error detection. In order to uniquely decode the information contained in the frame, the inverse of frame should not be a valid frame. A method for detecting invalid frames is also disclosed.

Abstract: A slip buffer includes a first-in-first-out memory, an input address generating means, an output address generating means, and a slip buffer control logic. The input address generating means generates addresses into which data is read into the first-in-first-out memory. The output address generating means generates addresses from which data is read from the first-in-first-out memory. The slip buffer control logic includes a first latch, a second latch and a slip address generation means. A first boundary address of a first frame boundary is stored in the first latch. The first latch includes a first validity bit which indicates whether the first boundary address is valid, A second boundary address of a second frame boundary is stored in the second latch. The second latch includes a second validity bit which indicates whether the second boundary address is valid.

Abstract: In a computer system having two processors both of which are used to process frames, a method for synchronizing a first set of frames corresponding to the first processor with a second set of frames corresponding to the second processor. A value stored in a register is initialized at frame boundaries of the second set of frames. This register value is repeatedly incremented during the frames of the second set of frames so that it increases within the frames. The value in the register is read. A timer value which provides a timing reference for each frame of the first set of frames is read. The value stored in the register when a frame boundary of the second set of frames had occurred is computed, based on the read register value and the read timing value. Based on the computed values, a frame length of the first set of frames is adjusted to maintain or improve frame synchronization between the two frame sets. Furthermore, data synchronization is provided in a similar fashion.

Abstract: A pointer processor circuit substantially eliminates the pointer gap during justification of an outgoing SONET/SDH frame relative to an incoming SONET/SDH frame. The pointer interpreter circuit PI is constructed to receive an incoming frame, interpret the pointer H1H2, and write data payload bytes of the incoming frame into a FIFO memory. An input clock CLK1 controls the writing of data payload bytes into the FIFO. The FIFO stores only data bytes. A pointer generator circuit PG is coupled to the FIFO and is constructed to read out data payload bytes from the FIFO, create an outgoing frame, and calculate a new pointer. An output clock CLK2 controls reading of data from the FIFO to form an outgoing frame. The PI, FIFO and PG cooperate for justification of the outgoing frame relative to the incoming frame.

Abstract: A two stage desynchronizer is provided to receive a gapped data component of an STS-3C (STM-1) signal and provide therefrom an ungapped DS-4NA (E4) data signal. The first stage includes a data byte formation block which takes the gapped STS-3C payload data and formulates the data into bytes, a first FIFO which receives the bytes, and a first FIFO read controller which utilizes the STS-3C clock signal and causes bytes of data to be read out according to a schedule which reads bytes eight or nine times out of every ten STS-3C clock cycles. For each row (270 byte times) of the STS-3C frame, either 241 or 242 bytes are read out of the FIFO according to a slightly gapped schedule where the reading of the 242nd byte at least partially depends upon the number of stuffs in the signal and the pointer movements received. The second stage of the desynchronizer includes a second FIFO, a FIFO fullness measurement block, and a VCXO.

Abstract: A jitter/wander reduction circuit is provided for a desynchronizer deriving an output clock signal from an independent clock signal and phase adjustment signals. Phase adjustment signals relate to a deviation of the independent clock signal from an input clock signal. The circuit includes a frequency offset estimation circuit receiving phase adjustment signals and providing a frequency offset estimation signal. A phase controller receives the frequency offset estimation signal, provides a feedback signal to the frequency offset estimation circuit, and provides a phase difference signal. A clock generator circuit receives the independent clock signal and the phase difference signal. The independent clock signal is adjusted based on the phase difference signal to provide an output clock signal.

Abstract: A unique word detector for use in detecting a unique word received by a demodulator in one of a plurality of windows offset in time is provided. The unique word detector includes a correlator for receiving successive sequences of binary data related to one of the windows. The correlator compares each of the successive sequences with the unique word to generate a measure of correlation between the sequences of binary data and the unique word. The unique word detector also includes a window detector interfaced with the correlator for comparing each of the measures of correlation to a predetermined threshold to determine whether the unique word has been received. A method of detecting the unique word in one of the windows is also provided.

Abstract: Apparatus and method for realizing a parallel implementation of run length coding. The system encodes control and data information into the respective link control and data streams and merges the same onto the communication link for transmission. In addition, the system separates link data information from control information upon receipt of the information stream and decodes the received link data and control information into the original information.

Abstract: In a frame transmission system for transmitting multi-frames of a DS3.C-bit parity frame system as prescribed in American National Standard and also in Proposed Contribution to CCITT (ITU-T), C1-bits assigned to the prior art DS3.C-bit parity frame, i.e., 3.times.3=9 C-bits (fixed bits) for the 2nd, 6th and 7th channels, are used as control bits of DS2 level signal for intrinsic purposes. These bits may be processed in their entirely in the same manner as with the prior art control bits.

Abstract: A high-performance clock synchronizer for transferring digital data across the asynchronous boundary between two independent clock domains operating at hardware-limited clock speeds. The external clock signal latches each incoming data word in a boundary register. An external clock divider produces several prolonged clock signals synchronized to the external clock signal for use in distributing the incoming data words into a bank of several external buffer registers, where each word stabilizes for more than one full internal clock interval before transfer across the asynchronous boundary to a bank of corresponding internal buffer registers synchronized to the internal clock signal. A special logic inserts and deletes pad words to equalize data flow rates. Another special logic reassembles the data words in proper sequence after transfer to the internal buffer register bank. Flag latches are used to avoid asynchronous sampling of more than one bit in each data word.

Abstract: A desynchronizer (10) for eliminating output mapping jitter includes a demapper circuit (12) for reading asynchronous data and a clock rate of an embedded signal within a synchronous channel (14). Payload data from the embedded signal is buffered within an elastic store circuit (17). The demapper circuit (12) outputs bit stuff and pointer justification timing adjustments to an overhead gapfill circuit (19) and a pointer justification leaky accumulator circuit (20). The overhead gapfill circuit (19) calculates overhead gaps within the payload data in order to generate a gapfill value (34). The pointer justification leaky accumulator circuit (20) determines the bit stuffs and pointer justifications occurring in the payload data in order to produce an accumulated value (36).

Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.

Abstract: A synchronous transmission system including a circuit arrangement for determining the data bytes of a signal to be received or to be transmitted. The circuit arrangement includes a control circuit (2, 14) which includes at least a counter (11, 19) for marking the pointer bytes of each high bit rate transport unit that can occur and which circuit arrangement includes at least a counter (6, 17) for marking with a count the data bytes of each high bit rate transport unit that can occur. The control circuit (2, 14) further includes for each group of low bit rate transport units that can occur in each maximum bit rate transport unit that can occur at least a position counter (6, 17), which counter is provided for marking with a count the data bytes in a low bit rate transport unit of the group. The control circuit (2, 14) is additionally provided at least for identifying the payload bytes and the pointer bytes on the basis of the counts and the information about the transport units of the signal.

Abstract: A serial data clock receiver circuit (11) is provided that synchronizes a clock signal to data. The serial data clock receiver circuit (11) comprises a control circuit (21), a dual oscillator circuit (19), and a phase locked loop circuit (22). The control circuit (21) arms the dual oscillator circuit (19) for being enabled during an idle period. The phase locked loop circuit (22) provides a reference voltage for the dual oscillator circuit (19). The dual oscillator circuit (19) is responsive to both the data and control circuit (19) for providing a clock signal.

Abstract: A desynchronizer for processing pointer movements and stuff bit information associated with payload data transmitted within a synchronous digital communication network. The desynchronizer includes a payload extractor (58) for removing payload data and storing it in an elastic store (32). The extractor also removes the pointer and stuff bit information which is passed through a digital low pass bit leaking module (36). The difference between the write and read addresses of the elastic store is determined (modules 48 and 50) and algebraically combined with the output of the bit leaking module (36) so as to provide the necessary data for adjusting the instantaneous frequency of a variable controlled oscillator (44) that generates the timing base for the read clock for reading the payload from the elastic store in a manner that minimizes jitter.