Frequency Or Phase Control Using Synchronizing Signal Patents (Class 375/362)
  • Patent number: 10379211
    Abstract: Disclosed is a method for generating a quality measure for a frequency set. The quality measure indicates the quality of the frequency set for use in a multi frequency ranging method for estimating the range to an object. The method for generating a quality measure comprises the steps of determining the smallest distance between any two range lines of a set of range lines in an N-dimensional phase space. The N-dimensional phase space comprises at least a first dimension representing a first phase difference, and a second dimension representing a second phase difference. The N-dimensional phase space has a dimension equal to the number of phase differences used by the multi frequency ranging method. The range lines represent all theoretical possible combinations of the phase differences.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: August 13, 2019
    Assignee: Weibel Scientific A/S
    Inventor: Jens Jørgen Nielsen
  • Patent number: 10263766
    Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where a pulse in the first clock signal is generated in response to an earliest-occurring transition between the first and second symbols in one of three difference signals representative of differences in state between two wires, determining direction of voltage change of a first transition detected on a first difference signal, providing a value selected based on the direction of voltage change as value of the first difference signal in the second symbol, and providing a value of a second difference signal captured during the first symbol as the value of the second difference signal when the second difference signal does not transition between the first symbol and the second symbol.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: George Alan Wiley, Chulkyu Lee
  • Patent number: 10250378
    Abstract: According to one embodiment, a base station apparatus includes: a radio equipment control that generates a baseband signal including data; a microwave apparatus that modulates the baseband signal to a microwave to transmit by radio; a microwave apparatus that demodulates the received first microwave to the baseband signal, then extracts a clock from a cycle of the data included in the baseband signal, imports the baseband signal in synchronization with the clock, and plays back the data; and a radio equipment that modulates the data played back by the microwave apparatus to a high-frequency signal, and the microwave apparatus outputs dummy data instead of the played back data when a frequency fluctuation amount of the clock exceeds a predetermined range.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: April 2, 2019
    Assignee: NEC CORPORATION
    Inventor: Hiroto Iizuka
  • Patent number: 10243703
    Abstract: Systems and methods are disclosed for detection of a selected signal pattern, such as a servo sector preamble, and for frequency offset determination. A circuit may be configured to divide a signal into detection windows of a selected size, and sample the signal a selected number of times within each detection window. The circuit may then determine an error value for each detection window based on values of the samples for each detection window, and determine the preamble is detected when a threshold number of most-recently sampled detection windows have error values below a threshold value. The circuit may then organize the sample values corresponding to the preamble into groups, and calculate phase estimates representing a phase at which the groups were sampled. The circuit may determine a frequency offset based on the phase estimates, and modulate the sampling frequency according to the frequency offset.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: March 26, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jason Vincent Bellorado, Marcus Marrow
  • Patent number: 10205541
    Abstract: An integrated circuit is described herein. According to one or more embodiments, the integrated circuit includes a local oscillator with a voltage-controlled oscillator (VCO) that generates a local oscillator signal. Further, the integrated circuit includes a frequency divider coupled to the VCO downstream thereof. The frequency divider provides a frequency-divided local oscillator signal by reducing the frequency of the local oscillator signal by a constant factor. A first test pad of the integrated circuit is configured to receive a reference oscillator signal. Further, the integrated circuit includes a first mixer that receives the reference oscillator signal and the frequency-divided local oscillator signal to down-convert the frequency-divided local oscillator signal.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Oliver Frank, Guenter Haider, Jochen O. Schrattenecker
  • Patent number: 9941952
    Abstract: A satellite terminal and a machine-implemented method are provided for encoding a burst header of a burst for transmission on an inroute. One component of a group of satellite terminal components consisting of an ASIC, a FPGA, and a DSP, generates a burst header having five information bits encoded therein. The five information bits may be encoded using a Reed-Muller code, a (32, 5) block code or a convolutional code having a code rate of either 1/5 or 1/10. The five information bits may represent one or more of a modulation type for a payload of the burst, a code rate for encoding the payload, a code type, and a spreading factor for spreading the payload during transmission. A satellite gateway and a machine-implemented method are also provided for decoding a burst header of a burst received on an inroute as described above.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 10, 2018
    Assignee: Hughes Network Systems, LLC
    Inventors: Yezdi Antia, Mustafa Eroz, John Alfred Schmid
  • Patent number: 9929732
    Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: March 27, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9848286
    Abstract: A method and apparatus for adjusting device-to-device (D2D) timing in a wireless communication system is provided. The method includes detecting a signal on a second D2D group, and adjusting D2D timing of the first D2D group based on the detected signal on the second D2D group. The first D2D group includes a first device and a second device which perform D2D operation in the first D2D group, and the second D2D group includes a third device and a fourth device which perform D2D operation in the second D2D group.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: December 19, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Youngdae Lee, Sunghoon Jung
  • Patent number: 9832093
    Abstract: A method of operating a data processing system to generate a jitter-injected signal from an input signal that is a function of time is disclosed. A time offset corresponding to a first time is generated according to a jitter specification that specifies the offset as a function of time. The jitter-injected signal at the first time is generated by evaluating the input signal at a time equal to a sum of the time offset and the first time. If the jitter specification only provides offsets at signal crossing times, interpolation is used to derive time offsets at non-signal crossing times.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: November 28, 2017
    Assignee: Keysight Technologies, Inc.
    Inventors: Chia Jui Hsu, Fangyi Rao
  • Patent number: 9692672
    Abstract: A communication system for interfacing a transmitting circuit with a receiving circuit includes a transmission interface for receiving data from the transmitting circuit and transmitting the data received over at least one data line in response to a transmission clock signal. The communication system also includes a reception interface configured for receiving the data in response to a reception clock signal and transmitting the data received to the receiving circuit. In particular, the system is configured for generating a plurality of clock signals that have the same frequency but are phase-shifted with respect to one another. In addition, during a calibration phase, the system is configured for selecting one of the clock signals for the transmission clock signal or reception clock signal via selecting at least one of the clock signals for transmission of test signals via the transmission interface and verifying whether the test signals received via the reception interface are correct.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: June 27, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Salvatore Pisasale
  • Patent number: 9680562
    Abstract: A satellite terminal and a machine-implemented method are provided for encoding a burst header of a burst for transmission on an inroute. One component of a group of satellite terminal components consisting of an ASIC, a FPGA, and a DSP, generates a burst header having five information bits encoded therein. The five information bits may be encoded using a Reed-Muller code, a (32, 5) block code or a convolutional code having a code rate of either 1/5 or 1/10. The five information bits may represent one or more of a modulation type for a payload of the burst, a code rate for encoding the payload, a code type, and a spreading factor for spreading the payload during transmission. A satellite gateway and a machine-implemented method are also provided for decoding a burst header of a burst received on an inroute as described above.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: June 13, 2017
    Assignee: Hughes Network Systems, LLC
    Inventors: Yezdi Antia, Mustafa Eroz, John Alfred Schmid
  • Patent number: 9673962
    Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: June 6, 2017
    Assignee: Analog Devices Global
    Inventors: Muhammad Kalimuddin Khan, Kenneth J. Mulvaney, Philip P. E. Quinlan, Shane O'Mahony
  • Patent number: 9613679
    Abstract: A controller includes first and second functional units, first and second clock-signal sources that provide corresponding first and second clock signals that drive the first and second functional units respectively. The second clock-signal generates its second clock-signal based on the first clock-signal. The clock-retardation unit dynamically causes the second clock-signal to have a target time-domain offset relative to the first clock-signal.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: April 4, 2017
    Assignee: Cavium, Inc.
    Inventors: David Da-Wei Lin, Edward Wade Thoenes
  • Patent number: 9601181
    Abstract: An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a clock-retardation unit. The clock-retardation unit is configured to cause the second clock-signal to sustain a temporal offset that causes an offset between the first and second clock-signals to step toward a target time-domain offset between the first and second clock-signals.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: March 21, 2017
    Assignee: Cavium, Inc.
    Inventors: David Da-Wei Lin, Edward Wade Thoenes, Vasudevan Kandadi
  • Patent number: 9553635
    Abstract: A method, an apparatus, and a computer program product for data communication over a multi-wire, multi-phase interface are provided. The method may include providing a sequence of symbols to be transmitted on a 3-wire interface, each symbol in the sequence of symbols defining one of three voltage states for each wire of the 3-wire interface, driving all wires of the 3-wire interface to a common voltage state during a transition from a first transmitted symbol to a second transmitted symbol, driving each wire of the 3-wire interface in accordance with the second transmitted symbol after a predetermined delay. Each wire may be in a different voltage state from the other wires of the 3-wire interface during transmission of the each symbol. The common voltage state may lie between two of the three voltage states.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: January 24, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Dhaval Sejpal, Chulkyu Lee, George Alan Wiley
  • Patent number: 9444566
    Abstract: Methods of performing time-of-day synchronization in a packet processing network include accumulating timestamps transmitted in packets between master and slave devices, which are synchronized to respective master and slave clocks and separated from each other by the packet processing network. Operations are also performed to determine whether first timestamps accumulated in a first direction across the packet network demonstrate that a first packet delay variation (PDV) sequence observed from the first timestamps is stationary. A phase offset between the master and slave clocks is then adjusted using a time-of-day (ToD) estimation algorithm. This adjusting can include evaluating a location-dependent statistic of the first PDV sequence.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: September 13, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Frederic Mustiere, Felix Duong, Alain Trottier, Russell Smiley, Peng Xiao
  • Patent number: 9418495
    Abstract: A locking device comprising: a code generation means for generating a plurality of access codes in a first series and a second series, each access code being valid for a predetermined period of time, a code input means for receiving an input code, and a code comparison means, wherein the code comparison means is configured to unlock the lock in response to input of a code that corresponds to a currently valid access code, wherein the period of validity of each access code in first series partially overlaps the period of validity two adjacent access codes in the second series.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: August 16, 2016
    Assignee: PARCELHOME LIMITED
    Inventors: Gregory Mackin, Jean-Michel Huten, Julien Vassallo
  • Patent number: 9397764
    Abstract: A carrier frequency offset calibration method and a carrier frequency offset calibration system are provided. The carrier frequency offset calibration method is adapted to calibrate the carrier frequency offsets of a transmission signal which includes a primary carrier and a secondary carrier. In the carrier frequency offset calibration method, the transmission signal is analyzed according to known carrier frequencies, a primary feedback value and a secondary feedback value, so as to obtain a primary carrier offset value and a secondary carrier offset value. The relationship between the primary carrier offset value and the secondary offset value is considered to determine whether to adjust the primary feedback signal and the secondary feedback signal.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: July 19, 2016
    Assignee: Novatek Microelectronics Corp.
    Inventor: Yuan-Hau Yang
  • Patent number: 9374754
    Abstract: A method for synchronising a receiving device with a transmitting device in a wireless communication network comprising forming a synchronisation sequence that has a frequency spectrum comprising peaks at multiple discrete fundamental frequencies, a signal power of the synchronisation sequence being concentrated at those frequencies, and transmitting said synchronisation sequence from the transmitting device to the receiving device.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: June 21, 2016
    Assignee: Neul Ltd.
    Inventor: Robert Young
  • Patent number: 9356853
    Abstract: A device is disclosed including a memory configured to store a user data frame. The user data frame includes a first portion that includes traffic data. The user data frame also includes a second portion that includes a set of stuff bits arranged in a detectible pattern wherein a count of the set of stuff bits is associated with a measure of transport utilization of a data communication channel over which the user data frame is transported.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 31, 2016
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Arvind R. Mallya
  • Patent number: 9225505
    Abstract: The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: December 29, 2015
    Assignee: SK Hynix Inc.
    Inventor: Keun Soo Song
  • Patent number: 9184904
    Abstract: A communication system includes: a plurality of lanes; a plurality of transmission circuits respectively outputting data to the lanes in accordance with a transmission clock; and a plurality of reception circuits respectively receiving data from the lanes, each reception circuit includes: a clock data recovery circuit extracting own clock information from received data: a clock information switch circuit selecting either one of the own clock information of the reception circuit or another own clock information of an another reception circuit; a phase shifter generating a phase adjusted clock from a common reception clock source in accordance with clock information selected by the clock information switch circuit; and an input circuit taking in transmitted data in accordance with the adjusted clock, and the clock information switch circuit selects the own clock information in a normal operation and selects the another own clock information in an eye-opening measurement operation.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: November 10, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Yoshiyasu Doi
  • Patent number: 9077594
    Abstract: A system including a midamble detection module and a processing module. The midamble detection module is configured to detect a midamble of a packet transmitted via a channel, where the packet includes (i) a preamble, (ii) the midamble, and (iii) a plurality of data fields, where the preamble includes (i) a first short training field, (ii) a first long training field, and (iii) a signal field, where the midamble includes (i) a second short training field and (ii) a second long training field, and where the midamble follows the preamble and is between two or more of the data fields. The processing module is configured to determine that the channel is busy in response to detecting the midamble in the packet.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 7, 2015
    Assignee: Marvell International LTD.
    Inventors: Raja Banerjea, Hongyuan Zhang
  • Patent number: 9071327
    Abstract: Methods are presented herein for estimating at least a frequency (offset) for a block of received symbols using two or more estimation stages. These methods may allow reducing the computational complexity of a frequency estimator while maintaining large frequency offset coverage and high frequency estimation accuracy. Also presented herein are satellite communication systems employing a burst transmission or continuous transmission, and configured to estimate at least a frequency (offset) for a received burst or a block of received symbols using two or more estimation stages. In some embodiments, a received burst or a received block of symbols may include a Unique Word located at or about the center of the received burst or the block of symbols.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: June 30, 2015
    Assignee: Gilat Satellite Networks Ltd.
    Inventors: Uzi Ram, Oded Bialer
  • Patent number: 9065630
    Abstract: Systems and methods are provided for detecting a received synchronization signal. The method includes receiving, at a receiver, a signal from a transmitter, where one or more portions of the received signal include the received synchronization signal. The method includes processing the one or more portions of the received signal to obtain a differential signal, and processing the differential signal and a plurality of candidate differential synchronization signals to obtain a plurality of cross-correlation signals. Each candidate differential synchronization signal is associated with one cross-correlation signal.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: June 23, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Chusong Xiao, Qing Zhao, Manyuan Shen, Leilei Song, Hui-Ling Lou
  • Patent number: 9036759
    Abstract: A method performed by a device for performing synchronization between devices for a Device-to-Device (D2D) communication is provided. The method includes setting, according to a process of the device, the device to a group of devices for performing a dynamic switching; outputting a synchronization signal corresponding to the set group as a signal for setting synchronization in a physical layer; controlling, upon receiving another synchronization signal from another device, the outputting of the synchronization signal by applying a time offset according to a relation between the set group that includes the device and the group that includes the another device; and setting, if the synchronization signal and the another synchronization signal are converged, synchronization of the device based on a time point where the synchronization signal is output.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: May 19, 2015
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Seung-Hoon Park, Chi-Woo Lim, Nam-Yoon Lee, Kyung-Kyu Kim
  • Patent number: 9037092
    Abstract: A method of determining at a receiver whether a received signal comprises a pure tone signal component. The method comprises: measuring a received signal over a measurement period; calculating, using maximum likelihood hypothesis testing, a likelihood ratio value for the measured signal and, determining, based on said likelihood ratio value, whether the measured signal comprises a pure tone signal component. The likelihood ratio value is a value indicative of the ratio of a likelihood LFSC that the measured signal comprises a pure tone signal component, and a likelihood LnoFSC that the measured signal does not comprise the pure tone signal component.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 19, 2015
    Assignee: BROADCOM CORPORATION
    Inventors: Morten R. Hansen, Lars P. B. Christensen
  • Patent number: 9031181
    Abstract: A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to generate a plurality of information communication clock signals based on the reference clock signal by staggering a phase of each of the information communication clock signals. The phase controller includes a delay-locked loop configured to generate a plurality of delay-locked loop signals based on the reference clock signal, and a plurality of time delay elements. Each time delay element is configured to produce a respective one of the information communication clock signals by adding a respective delay to a respective one of the delay-locked loop signals. The system includes information communication devices each including a respective transmitter. Each of the transmitters is configured to operate in response to a respective one of the information communication clock signals.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 12, 2015
    Assignee: Marvell International Ltd.
    Inventor: Pierte Roo
  • Publication number: 20150124916
    Abstract: Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.
    Type: Application
    Filed: January 6, 2015
    Publication date: May 7, 2015
    Applicant: INTEL CORPORATION
    Inventors: Fangxing Wei, Subratakumar Mandal
  • Publication number: 20150124917
    Abstract: A clock synchronization circuit is configured to capture an input data bit according to an input clock signal, and to synchronize and output the input data bit. The clock synchronization circuit includes a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line. The clock synchronization circuit further includes a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal. The clock buffer includes an inverter core portion and an electric current suppressing portion. The inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal. The electric current suppressing portion is configured to suppress an amount of the electric current.
    Type: Application
    Filed: January 8, 2015
    Publication date: May 7, 2015
    Inventor: Kenji ARAI
  • Publication number: 20150110231
    Abstract: Systems and methods are disclosed herein to provide improved clock synchronization between wireless data communication transmitters and receivers, including Orthogonal Frequency Division Multiplexing (OFDM) communication systems. In accordance with one or more embodiments, a clock synchronization system is disclosed that includes an adaptive threshold function operative in conjunction with a synchronizer that adjusts the frequency and phase of a receive clock oscillator. Such a synchronization system may offer improved capabilities such as resistance to radio frequency (RF) channel impairments and noise, rejection of mis-decoded clock synchronization signals, and handling of multiple transmitters.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 23, 2015
    Inventors: Thomas Alexander, David Jennings Wicker, JR.
  • Patent number: 9014285
    Abstract: An object of the present invention is to provide a receiving apparatus and a receiving method capable of preventing phase rotation of a signal after FFT from occurring on a frequency domain. Further, the receiving apparatus according to the present invention is provided with: a window control unit configured to control a position of an FFT window in which FFT is performed to the time domain signal, and output FFT data corresponding to the FFT window; a signal delaying unit configured to generate, from the time domain signal, a plurality of delay signals with different delay amounts; and a signal switching unit having a switch for outputting by switching between two of the time domain signal and the plurality of delay signals based on a predetermined switch timing, the signal switching unit being configured to output the FFT data including the output signal of the switch.
    Type: Grant
    Filed: September 5, 2011
    Date of Patent: April 21, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukihiro Kadota, Takashi Fujiwara
  • Publication number: 20150098541
    Abstract: Embodiments of a system and method for synchronizing chains in a transceiver using central synchronization signals are generally described herein. In some embodiments, an RF signal having a reference frequency in a differential mode and a synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are produced at a oscillator generation circuit. The RF signal having a reference frequency in a differential mode and the synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are provided over each of a plurality of LO lines to a plurality of local LO generation circuit chains. Each synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode is extracted at the plurality of local LO generation circuit chains.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Inventor: Assaf Ben-Bassat
  • Patent number: 9001949
    Abstract: A method in a QAM receiver (100) for performing timing recovery. The QAM receiver (100) is configured to receive a sequence of symbols. Each symbol is represented by a respective IQ pair comprising a respective inphase component I and a respective quadrature component Q. The QAM receiver (100) samples the respective I component and the respective Q component with a relative timing offset between the sampling of the respective I component and the respective Q component. The QAM receiver (100) establishes a first value associated to a quality of the I component samples, and a second value associated to a quality of the Q component samples, and compares the first value and second value to determine if the sampling timing should be advanced or delayed to improve the sample quality. The QAM receiver (100) adjusts subsequent sampling by advancing or delaying a sampling timing based on the comparison.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 7, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Christer Svensson
  • Patent number: 9001275
    Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 7, 2015
    Inventors: Andrew Joo Kim, David Anthony Stelliga
  • Patent number: 9001955
    Abstract: A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; a first mode of operation in which the frequency divider is configured to operate in dependence on a first division control signal such that the resultant oscillating output signal has a first frequency and first phase, a second mode of operation in which the frequency divider is configured to operate in dependence on a second division control signal such that the resultant oscillating output signal has a second frequency and second phase, the first division control signal being generated independently of the oscillating output signal such that the first phase is maintained when the phase-locked
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: April 7, 2015
    Assignee: Cambridge Silicon Radio Limited
    Inventors: Pasquale Lamanna, Nicolas Sornin
  • Patent number: 8995596
    Abstract: Circuits and techniques for operating an integrated circuit are disclosed. A disclosed method includes receiving a data packet with a first operating frequency rate with first and second receiver circuits. The data packet may include a plurality of preamble bits. The first and second receiver circuits may operate at second and third operating frequency rates, respectively. A portion of the data packet received at the first receiver circuit is transmitted to a control circuit. The plurality of preamble bits within the portion of the data packet is identified with the control circuit. A clock circuit is then calibrated based on the plurality of preamble bits. The first and second receiver circuits may be clocked with first and second clock outputs from the clock circuit.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 31, 2015
    Assignee: Altera Corporation
    Inventors: Keen Yew Loke, Siew Leong Lam
  • Patent number: 8995583
    Abstract: A technique for decoding a signal in a communication network is provided. A method implementation of the technique comprises the steps of receiving a signal; identifying a position in the signal; initializing a Viterbi state metric; and decoding the encoded signal by means of a wrap-around Viterbi algorithm. The received signal comprises information, wherein the signal is encoded by a tail-biting convolutional code. The identified position relates to a known portion of the information. The initialized Viterbi state metric is consistent with the known portion of the information. The decoding uses the initial Viterbi state metric, wherein the decoding starts at a decoding step following the identified position.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 31, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Stefan Mueller-Weinfurtner, Matthias Kamuf
  • Patent number: 8994571
    Abstract: An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: March 31, 2015
    Assignee: Marvell International Ltd.
    Inventors: Hossein Zarei, Chieh-Yu Hsieh
  • Patent number: 8989321
    Abstract: Systems, methods, and other embodiments associated with preamble detection based on repeated preamble codes are described. According to one embodiment, an apparatus is provided that wirelessly receives a signal and calculates a differential output corresponding to a multiplication of the signal and a delayed version of the signal. A cross correlation is performed between the differential output and a known preamble pattern to produce a cross correlation output. One or more peaks are detected in the cross correlation. The detected peaks are used in subsequent processing to detect the known preamble pattern in the wirelessly received signal.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Marvell International Ltd
    Inventors: Quan Zhou, Songping Wu, Daxiao Yu
  • Publication number: 20150078427
    Abstract: A clock data recovery circuit including a recovery unit and a loop control unit is provided. The recovery unit generates a recovery clock signal according to an original data signal. The recovery unit locks a frequency of the recovery clock signal to a correction frequency through a first loop, and locks the frequency of the recovery clock signal to a sampling frequency through a second loop. The correction frequency is smaller than the sampling frequency. The recovery unit adjusts the frequency of the recovery clock signal according to a reference clock signal and a first dividing signal in the first loop. The loop control unit switches the recovery unit to the first loop or the second loop according to a frequency difference between the reference clock signal and a second dividing signal.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventor: Shih-Chun Lin
  • Patent number: 8982926
    Abstract: Disclosed is a spectrum spread communication system which is hardly influenced by noises, and in which a frame structure can be identified at a receiving side without use of a frame synchronization signal. A spread code generator switches spread codes (“Scai” and “Scbi”) in each frame, and outputs it to a spread modulation unit. The spread modulation unit performs spread modulation of transmission data, and transmits it to a direct current power line. A reference code generator generates reference codes (“Scai” and “Scbi”) in the same code phase. Spread demodulation units performs spread demodulation of the received signal with use of the reference codes (“Scai” and “Scbi”), and output it to a selection unit. A frame synchronization detection unit identifies a frame structure on the basis of switching of a synchronization state of a code phase in a code phase synchronization detection unit.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: March 17, 2015
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yuji Kasai, Masahiro Murakawa, Tetsuya Higuchi
  • Publication number: 20150071394
    Abstract: A wireless communication device includes a BBIC for performing baseband signal processing, an RFIC for performing radio-frequency signal processing, and a quartz resonator. The RFIC has a storage unit which stores an adjustment value for adjustment of a clock frequency that is based on an oscillation frequency of the quartz resonator, and outputs the adjustment value when its resetting active state is canceled; a frequency adjusting unit for adjusting the clock frequency according to the adjustment value; and an RF signal processing unit which operates based on the clock signal and performs the radio-frequency signal processing.
    Type: Application
    Filed: December 25, 2013
    Publication date: March 12, 2015
    Applicant: PANASONIC CORPORATION
    Inventors: Kenji Miyanaga, Noriaki Saito, Takayuki Tsukizawa
  • Patent number: 8964922
    Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Matthew Felder, Mark Summers
  • Publication number: 20150043695
    Abstract: A reception circuit has: a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector.
    Type: Application
    Filed: July 18, 2014
    Publication date: February 12, 2015
    Inventors: Shigeto SUZUKI, Hirotaka TAMURA
  • Patent number: 8953581
    Abstract: A system for synchronizing nodes in a wireless network comprises a first node and a second node. The first node comprising a transmitter, a receiver, and a first time keeper. The second node comprising a transmitter, a receiver, a second time keeper, a timing error measurer for making a timing error measurement between the first time keeper and the second time keeper. The second timekeeper is adjusted to target minimizing the timing error measurement.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: February 10, 2015
    Assignee: Dust Networks, Inc.
    Inventors: Gordon Alexander Charles, Lance Robert Doherty, Thor Nelson Juneau, Mark Alan Lemkin, Jonathan Simon, Zhenqiang Ye
  • Publication number: 20150036774
    Abstract: A CDR circuit includes an AD converter that converts an analog input signal to a digital output signal according to an operation clock signal; a phase adjuster that subtracts a first phase from a first clock signal having a first frequency equal to a frequency of the input signal to output a second clock signal having a second frequency as the operation clock signal to the AD converter; a phase detector that detects a second phase in the output signal of the AD converter; a filter that obtains a third phase by performing a filtering process based on the first phase, the second phase, and the third phase output from the filter; an adder that adds the first phase and the third phase to obtain a fourth phase; and a decision circuit that obtains recovered data from the output signal of the AD converter using the fourth phase.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 5, 2015
    Inventor: YANFEI CHEN
  • Patent number: 8948159
    Abstract: A transmitter includes an amplitude adjustment unit multiplying an amplitude adjustment sequence value for adjusting amplitude with a synchronization channel transmitted from a base station for establishing synchronization with a mobile station.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: February 3, 2015
    Assignee: NTT DOCOMO, INC.
    Inventors: Motohiro Tanno, Kenichi Higuchi, Mamoru Sawahashi, Yoshihisa Kishiyama
  • Publication number: 20150023459
    Abstract: A reception circuit includes: a plurality of block circuits that each include a phase control circuit that controls a phase of a first clock, and a plurality of internal circuits that are driven by a second clock generated based on the phase-controlled first clock, wherein the phase control circuit in each of the block circuits is controlled by means of a control signal from an operation phase control circuit in such a way that an error rate for reception data due to the plurality of block circuits decreases.
    Type: Application
    Filed: June 26, 2014
    Publication date: January 22, 2015
    Inventor: Yoshiyasu DOI
  • Patent number: 8913705
    Abstract: A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Oracle International Corporation
    Inventor: Bruce J. Chang