Abstract: A data receiving method and receiver are provided. A receiver determines the length of a pre-tail and the length of a post-tail of a frame by obtaining a start time and an end time of the main part of the signal of the frame at a fixed time, and determines a start time and an end time of a frame receiving window according to the start time and the end time of the main part of the signal of the frame and according to the length of the pre-tail and the length of the post-tail; and receiving a frame between the start time and the end time of the frame receiving window, so that the receiver can accurately and completely receive the main part of the signal and the pre-tail and post-tail of each frame to accurately and completely receive signals.

Abstract: An edge interval measuring block measures a first same-edge interval. A bit number detector detects the number of bits in the first same-edge interval based on reference bit length information and detects a first number of bits in a same-value interval between consecutive bits of the same value by subtracting the number of bits in the known bit stream from the number of bits in the first same-edge interval. The edge interval measuring block then measures a second same-edge interval. The bit number detector detects the number of bits in the second same-edge interval based on the reference bit length information and detects a second number of bits in a bit stream of consecutive bits of the same value opposite to the value in the same-value interval by subtracting the first number of bits from the number of bits in the second same-edge interval.

Abstract: A method for operating an automation system with a plurality of communication users linked for communication purposes via a serial connection, of which at least one functions as sender and at least one as a receiver, includes determining at a sender an offset value between an occurrence of a synchronous signal and a communication clock cycle, transmitting the determined offset value in a data transmission to the at least one receiver, waiting at the at least one receiver until a time period commensurate with the offset value has elapsed, and generating at the at least one receiver an output signal after the time period has elapsed.

Abstract: Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.

Abstract: Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.

Abstract: Disclosed is an apparatus and methodology for synchronizing data received at a central location that has been collected at plural remote locations and separately transmitted to the central location. A plurality of remote sensors is provided and configured to be simultaneously triggered to begin a data collection sequence and to subsequently transmit the collected data along with remote sensor identification data and timing information to the central location. Timing information may include a specifically transmitted time reference or may be derived based on successive transmissions from the individual remote sensors.

Abstract: A timing synchronous detection device includes: a first autocorrelator that performs autocorrelation using a received signal and a first delay signal in which the received signal is delayed; a second autocorrelator that performs autocorrelation using the received signal and a second delay signal in which the received signal is delayed; an average-normalization device that obtains an average value of an output signal of the first autocorrelator and an output signal of the second autocorrelator; a comparator that compares the average value and a threshold value and that outputs, if the average value is larger than the threshold value, the average value; and a maximum value search device that searches for a maximum value of the average values that are output from the comparator.

Abstract: A method of demodulating at a receiver a plurality of symbols bk comprised in a e.g. UWB, received signal y(t), said receiver having knowledge of a time hopping sequence vector c of the transmitted signal, said method comprising the step of: generating a plurality of frequency-domain samples from the received signal y(t). It further comprises the steps of: from said plurality of frequency-domain samples and said time hopping sequence vector c, applying a coarse estimation stage (7) for identifying the beginning of a first complete symbol (formula A) in an acquisition interval; applying a stage for fine estimation (8) of the time delay (formula B) of each symbol bk, wherein k denotes the k-th symbol, by searching a relative maximum at which a signal energy distribution exceeds a certain threshold Pth; from said fine estimation of the time delay (formula B) of each symbol bk, demodulating (formula C) said symbols bk.

Abstract: A source device counts a clock CLKpixel for pixel data using a transmitting counter, adds a counted value Csource(t) of the transmitting counter at a timing of transmitting a video packet Pvideo to the sink device to a header part of the video packet Pvideo as a time stamp value Csource(t), and transmits the video packet Pvideo to the sink device. The sink device receives the video packet Pvideo, extracts the time stamp value Csource(t) from the header part of the video packet Pvideo, generates a fixed reference clock CLKref based on the counted value Csource(t) of the transmitting counter using a first PLL, circuit, and generates the clock CLKpixel for the pixel data of the source device based on the reference clock CLKref using a second PLL circuit.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.

Abstract: A transmitting method has steps of modulating carrier waves having frequencies set at ½N?n (n?N; n is a positive integer) of a reference frequency with transmission signals to produce modulated signals, multiplexing the modulated signals by frequency division multiplexing to produce an input signal, and transmitting the input signal to a synchronous detector in which the transmission signals are extracted from the input signal by calculating a moving average of the input signal every sampling period of time corresponding to the reference frequency and performing an addition and subtraction calculation corresponding to the cycle of each carrier wave for the moving averages. The frequency of each carrier wave, modulated with one transmission signal having a first signal level, is equal to or lower than the frequency of any carrier wave modulated with another transmission signal having a second signal level higher than the first signal level.

Abstract: Described is an apparatus for suppressing spurious spectral lines in a frame based bit-serial data stream, in which frames include payload data and frame markers. The apparatus includes means (16) for randomizing first frame marker elements (START) in a first position within each frame and means (18) for correlating second frame marker elements (STOP) in a second position within each frame with the randomized first frame marker element.

Abstract: A method is provided of characterising a data stream of binary symbols, the method comprising sampling the stream at a predetermined rate sufficient to capture at least two samples per binary symbol, identifying the shortest continuous run of samples having the same logic level and assigning a symbol rate to the stream on the basis that the identified run is one symbol in length.

Abstract: The present invention is an improved system and method for detecting the leading edge of a waveform. More specifically, the invention relates to detecting the leading edge of an ultra wideband waveform. The invention requires locking to the ultra wideband waveform at a lock reference time, and sampling the ultra wideband waveform during one or more time windows relative to the lock reference time to identify one or more leading edge candidate times based on one or more detection criterion. The ultra wideband signal is sampled at a band limited Nyquist rate that avoids aliasing within a band of interest of the ultra wideband waveform, but allows aliasing outside of the band of interest to minimize the number of samples for leading edge detection processing.

Abstract: An oscillation circuit, a driving circuit thereof, and a driving method thereof are provided. The driving circuit generates a second enable signal according to an output signal of an oscillator and a first enable signal. The second enable signal is transmitted to the oscillator. When a number of waves of the output signal within a predetermined period is smaller than a predetermined value, the driving circuit adjusts a voltage level of the second enable signal. A voltage level of the first enable signal is equal to an enable voltage level. Through variations in voltage levels of the second enable signal, the oscillator is triggered to oscillate.

Abstract: A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for detecting a phase error from sampling data and the sampling clock, the sampling data being sampled from the input data at timing of the sampling clock; frequency error detection means for detecting, based on a differential coefficient obtained as a result of detecting the phase error, a frequency error; and frequency correction means for correcting a frequency of the sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of the PLL circuit, the frequency correction value being calculated based on the frequency error.

Abstract: Serial data communication methods and apparatus using a single line are provided. The data communication methods may include: setting a rising edge of a serial pulse signal so that a cycle of the serial pulse signal begins therefrom; setting a falling edge of the serial pulse signal within the cycle of the serial pulse signal according to a data value recorded within the cycle of the serial pulse signal; and transmitting a packet formed by combining at least one cycle of the serial pulse signal in series via a single line.

Abstract: A method for detecting a delimiter pattern (SOF) in a signal stream containing a carrier or subcarrier modulated by the delimiter pattern comprises: specifying an expected delimiter occurrence time (t1) of an occurrence of the delimiter pattern and a tolerance zone (tz) within which the expected delimiter occurrence time (t1) may jitter; approximating, within the tolerance zone (tz), a zero of a cross correlation function (CCF) of the data stream with the delimiter pattern, or detecting the phase (?) of the carrier or subcarrier in respect to an arbitrarily defined reference position within the tolerance zone (tz), e.g.

Abstract: A method is disclosed, including identifying a preamble in a frame, where the preamble has a preamble length 1. M data items received in succession are stored. The m data items once divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n: m>n, m>1, n>1. The n portions are respectively correlated to the expected values to form component correlation results. Delaying the component correlation results, with at least two component correlation results being delayed by different lengths. The method also includes combining the delayed component correlation results to form a total correlation value. The total correlation value is used to determine whether the m received data items contain the preamble of a frame.

Abstract: An asynchronous serial communication method and the apparatus including a sender transmitting a one bit of serial data by firstly making a signal transition on the data line, secondly putting the one bit of serial data on the data line after a predetermined time T1 yet before another predetermined time T1+T2, and a receiver receiving the one bit of serial data by firstly detecting the signal transition on the data line and secondly capturing the one bit of serial data after a predetermined time T3 (where T3>T1+T2).

Abstract: Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.

Abstract: Provided is a data delivery system including a transmitter which transmits data stream via a network, and a receiver which receives the data stream and stores it into a reception buffer thereof, and decodes the stored data stream. The network has predetermined therein a necessary amount of data stored in the reception buffer for decoding the received data stream continuously irrespectively of a variation of a time taken for data transfer from the transmitter to the receiver. The receiver starts, after reception of the latter and before the data has been stored up to the predetermined necessary stored amount, decoding of the data stream at a rate lower than assumed at the time of data encoding at the transmitter. When the data has been stored into the reception buffer up to the predetermined necessary stored amount, the receiver changes the decoding data to the assumed rate for decoding further data.

Abstract: Disclosed are a method of and a system for controlling frame synchronization for European Digital Audio Broadcast (DAB), the method including the steps of generating a frame synchronization start-signal with respect to an incoming signal which is input when power is supplied, keeping symbol count values with the value “0” after the frame synchronization start-signal is input, transmitting a frame offset value with respect to the incoming signal, and restarting symbol counting for frame synchronization depending on the frame offset value after the frame offset value is input, wherein the frame synchronization unit may preferably transmit the frame offset value after estimating the frame offset value. In accordance with the method and system described herein, it is possible to achieve frame synchronization in short time, thereby reducing a startup time of a DAB receiver and power consumption which is needed for the frame synchronization.

Abstract: A special data including communication wire continuous dominant levels of a number of N more than the transceiving bit number of n of communication wire continuous dominant levels, set in a character as one unit of communication data, can be transceived by a widely-used serial communication interface such that a predetermined transmission rate is changed to n/N times the transmission rate only when the special data is transmitted, whereby the special data can be easily transceived at a low cost.

Abstract: A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, which generates low frequency timing signals, and a secondary clock generation system that provides a high frequency clock that is used by the wireless transceiver to produce high resolution timing signals to control the timing of the wireless transceiver. The high resolution timing signals are commenced responsive to a low resolution timing signal.

Abstract: The present invention relates to a method and a device for data extraction from a data stream containing at least one data packet. First, comparing a bit stream derived from a received digital data stream with an expected bit sequence is performed by packet detector to determine a correlation value (CorrVal) for detecting a data packet. Then, a data extraction unit is started for data extraction when the correlation value (CorrVal) exceeds a threshold value (CorrThres) indicating that a data packet has been detected. Therefore, comparing the received bit stream with the expected bit sequence to determine a new correlation value (CorrVal) is continued by the packet detector. Finally, restarting data extraction is initiated by a sync-control module when the new correlation value (CorrVal) exceeds the form correlation value (MaxCorrVal).

Abstract: Detecting a boundary within a transmitted packet is disclosed. A first symbol of the transmitted packet is received in a band. A second symbol of the transmitted packet is received in the band. The first and second symbols are compared. The boundary within the transmitted packet is detected based at least in part on the comparison of the first symbol and the second symbol and the band.

Abstract: The apparatus contains a counter that is synchronized to the reference time in the mobile station. The counter counts sampled chips of the radio signal to produce a count. The apparatus further includes a controller that controls the processing of the radio signal, activates the processing of the radio signal when the count matches a begin count, and deactivates the processing of the radio signal when the count matches an end count, wherein the begin count and the end count are determined by a signal processor as a function of the time frame offset of the radio signal with respect to the reference time in the mobile station.

Abstract: A method for synchronizing video signals is provided wherein a synchronization state signal is generated which is descriptive for the synchronization of an output of fields/frames with the respective input of respective fields/frames of an underlying video data screen in particular on the basis of a time difference which is given by respective counted times and/or temporal changes and/or variations thereof.

Abstract: A method for determining a presence of a preamble for an orthogonal frequency division multiplexed (OFDM) complex valued sample stream may include capturing a portion of the OFDM complex valued stream and autoconvolving the portion of the OFDM complex valued sample stream to generate an autoconvolved portion. The method may further include determining a presence of a preamble in the OFDM complex valued sample stream if a peak is detected in the autoconvolved portion.

Abstract: A wireless device, method, and signal for use in communication of a wireless packet between transmitting device and a wireless receiving device via a plurality of antennas, wherein a signal generator generates wireless packet including a short-preamble sequence used for a first automatic gain control (AGC), a first long-preamble sequence, a signal field used for conveying a length of the wireless packet, an AGC preamble sequence used for a second AGC to be performed after the first AGC, a second long-preamble sequence, and a data field conveying data. The AGC preamble sequence is transmitted in parallel by the plurality of antennas.

Abstract: A phase controlling apparatus is disclosed. The phase controlling apparatus controls phases of signals which are output from a plurality of signal sources corresponding to first phase information which indicates a phase of a predetermined signal. The phase controlling apparatus includes a phase information storing section and a phase controlling section. The phase information storing section stores second phase information which indicates a phase of a signal which is output from each of the plurality of signal sources. The phase controlling section changes a phase of a signal which is output from at least one of the plurality of signal sources corresponding to the second phase information stored in the phase information storing means to control the difference of phases of signals which are output from the plurality of signal sources.

Abstract: A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal outputted from each of the group of data lanes is respectively detected and respective elapsed times from the detection of the predetermined data element outputted from each of the group of data lanes to the detection that the predetermined data element has been outputted from all of the group of data lanes are measured. The group of serial data signals are then de-skewed by respectively delaying them in accordance with their respective measured elapsed times. The test signal may include the predetermined data element, a lane identifier, and a predetermined number of additional data symbols, the predetermined data element being a predetermined data character.

Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.

Abstract: In a DSRC communications controller equipped with a plurality of reception means for DSRC communications according to the invention, a reception reservation storage section 104 comprises means for detecting a communications frame start signal (unique word 1) of DSRC communications by using reception means not engaged in communications among the plurality of reception means and means for storing the control information of DSRC communications where the communications frame start signal is detected. On completion of DSRC communications by way of reception means, a controller uses the control information stored in the reception reservation storage section to establish next communications. This allows continuous reception of information from a plurality of roadside machines to be made efficiently even in case a plurality of communications areas overlap one another.

Abstract: A bit synchronizer (16) that includes a tapped delay line (38) connected to a plurality of timing hypothesis circuits. A control and adjudication circuit (50) is connected to the timing hypothesis circuits, and compares outputs of the timing hypothesis circuits and selects one. Each of the timing hypothesis circuits includes a sum-and-dump summer (112) that is connected to outputs of the tapped delay line (38). The timing hypothesis circuits further include an absolute value circuit (46) and an averaging circuit (48). A select switch (60) is connected to the summers (112) and receives a switch control signal from the control and adjudication circuit (50). A threshold test circuit (62) compares the selected output signal to a threshold value and outputs a mark or space symbol.

Abstract: An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol group” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from the buffers having start symbols is temporarily suspended.

Abstract: There is provided a data re-synchronization apparatus for suppressing occurrence of a jitter in a high-speed serial signal transmitted over a long distance to improve a reliability of re-synchronized data. In the apparatus, a shift register serial-parallel conversion circuit inputs the serial signal ant converts an input data signal to parallel data signals of a predetermined number of parallel bits. An input data extension circuits extend the parallel data signals by a predetermined clock length time-axially to provide extended data signals. An input pattern detection circuit sends an input take-in signal so that data can be taken in at roughly a center of variation points of the extended data signals, while a re-synchronized data take-in signal generation circuit latches the input take-in signal in synchronization with an output clock signal.

Abstract: A transmitter apparatus has a modulator for modulating a carrier wave to produce a modulated wave having communication data superimposed thereon and a transmitter for transmitting the modulated wave to a receiver apparatus. Before starting communication, the transmitter apparatus transmits a predetermined dummy pulse to the receiver apparatus so as to bring the communication data restored by demodulation in the receiver apparatus into a logic state in which the communication data should be kept when no communication is taking place. This makes it possible to perform correct communication even if the communication data demodulated in the receiver apparatus before the start of communication is not kept in the logic state in which it should be kept when no communication is taking place.

Abstract: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start of the period, which includes generating a first reference signal having a first reference signal frequency and a first reference signal phase synchronized with the start of the period, and detecting a first time interval required for the input signal phase to have a first specified relationship to the first reference signal phase. The technique includes similarly determining a relative ending phase of the input signal at the end of the period. The technique includes determining an input signal temporal characteristic from the number of transitions and the relative beginning phase and the relative ending phase.

Abstract: There is provided a method of detecting a block sync signal in which a sync signal and code sequence can be distinguished from each other to recognize the head of a block composed of a plurality of code words at the time of data reading or reception. A sync word detector (10) is supplied with a window signal Sync_window generated based on a parity OK signal supplied from a parity check circuit (12) and indicating a period between the sync word included in signal read from the medium (1) and the ID information, and detects the sync word as to a bit string detected by a PRML Viterbi detector (6) with the use of the Sync_window signal.

Abstract: A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal outputted from each of the group of data lanes is respectively detected and respective elapsed times from the detection of the predetermined data element outputted from each of the group of data lanes to the detection that the predetermined data element has been outputted from all of the group of data lanes are measured. The group of serial data signals are then de-skewed by respectively delaying them in accordance with their respective measured elapsed times. The test signal may include the predetermined data element, a lane identifier, and a predetermined number of additional data symbols, the predetermined data element being a predetermined data character.

Abstract: The invention relates to a method for the asynchronous serial data transmission between a transmitter and a receiver over a radio transmission link, whereby a synchronization data frame and a carrier recognition frame is arranged in front of the useful data frame. The data frames are each enframed at the beginning and end by a start bit and a stop bit at the beginning and end. The coding of all data frames results such that, in addition to the start and stop bits, an equal number of zero and one bits exists.

Abstract: The invention relates to an electronic ballast and to a controller which drives this ballast, in which two communication protocols are provided for the digital drive.

Abstract: A transmission and reception method permits simultaneous use of multiple remote controllers at the same frequency to a single receiver without mutual interference. A transmission period consists of a transmission enabled period for transmitting a transmission signal from a remote controller, and a transmission disabled period for disabling the signal transmission. Individual remote controllers can repeat the transmission. For the individual remote controllers, one period of the transmission period is 2i (“I” is a natural number equal to or more than 3, and is set to a proper number different from one channel to another) times a unit transmission period.

Abstract: Determination and processing for fractional-N programming values. The present invention is operable to receive a clock signal (CLK) and to transform that CLK into a new CLK, when necessary, for use by various circuitries within a system. The present invention is operable to generate two different CLKs for use by a radio frequency (RF) circuitry and a baseband processing circuitry in certain embodiments. The present invention employs a measurement circuitry and to characterize a first CLK and uses a fractional-N synthesizer to perform any necessary processing to generate the one or more CLKs to the other CLKs within the system. The first CLK may be received from an external source or it may be generated internally; in either case, the present invention is able to modify the CLK into another CLK for use by other circuitries within the system or for use by another external device.

Abstract: A method and apparatus for determining the appropriate timing interval for each bit or data symbol in serial data communications. A sending device transmits a predetermined bit sequence, such as a binary pattern corresponding to one byte, either on its own initiative or in response to an action of a receiving device. A microprocessor in the receiving device measures a calibration time interval between the leading edge of a start bit and a subsequent marker transition, either between subsequent data bits or between the final data bit and the stop bit. This measured interval may be mathematically converted to units useful to calibrate a function or device that conducts input/output operations. Optionally, the process may be repeated periodically to compensate for clock rate drift. This invention may be used for autobaud data rate detection, or matching the actual data rate of a remote serial device, and permits accurate communications without precision timing references.

Abstract: A digital subscriber line network allows a plurality of remote modems to communicate without interfering with the communication to the central office. Each symbol of a superframe is converted to a tone vector, and the tone vectors are integrated over a plurality of superframes. The tone vectors of the data symbols are random, and tend to cancel each other out. The tone vector of the synchronization symbol remains constant among the plurality of superframes, and the sum of these tone vectors over a plurality of superframes becomes large. By identifying the largest integrated tone vectors, the network may identify the position of the synchronization symbol. The modems may then align using the position of the synchronization symbol.