Including Memory Patents (Class 377/26)
  • Patent number: 10181001
    Abstract: A compensating initialization module may be automatically inserted into a design to compensate for register retiming which changes the designs behavior under reset. The device configuration circuitry may provide an adjustment sequence length as well as a start signal to the initialization module to properly reset the retimed user logic implemented on the integrated circuit after initial configuration and unfreezing of the integrated circuit. The auto initialization module may control the c-cycle initialization process and indicate to the user logic when c-cycle initialization has completed. The user logic may subsequently begin a user-specified reset sequence. When the user-specified reset sequence ends, the user logic implemented on the integrated circuit may begin normal operations. Additionally, a user reset request may also trigger the auto initialization module to begin a reset process.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Mahesh A. Iyer
  • Patent number: 10096369
    Abstract: A semiconductor device including a voltage generation circuit, and voltage generation circuit generates a required voltage according to internal data requested in response to an operation are provided. The voltage generating circuit includes a plurality of registers A-1, B-1, C-1, D-1, voltage generating blocks A-2, B-2, C-2 and a voltage switch. The registers A-1, B-1, C-1, D-1 hold data provided from control logic. The voltage generating blocks A-2, B-2, C-2 generate voltage based on voltage control data held by the registers A-1, B-1, C-1. The voltage switch selects voltages based on selection control data held by the register D-1. The connecting element includes signal lines for sequentially transmitting the voltage control data or the selection control data, signal lines for sequentially transmitting a clock signal CLK and signal lines for controlling output of data held by the registers.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: October 9, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Hiroki Murakami, Makoto Senoo
  • Patent number: 10033569
    Abstract: An example managed network device includes a control unit and a storage medium that stores a file that includes a variable value. The control unit provides an execution environment for a simple network management protocol (SNMP) engine operable by the control unit to establish, based on a set of authentication parameters, secure SNMP communication with a network management system, determine whether the file is corrupted, determine whether the variable value stored in the file is readable, determine whether the variable value is greater than or equal to a maximum value, and, responsive to determining that the file is corrupted, that the variable value is not readable, or that the variable value is greater than or equal to the maximum value: re-initialize the variable value, notify a network management system, and maintain the secure simple networking management protocol communication with network management system using the set of authentication parameters.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: July 24, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: Ashish Kumar Singh, Appasaheb Ajit Ghali, Tibin Antony
  • Patent number: 9666290
    Abstract: A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: May 30, 2017
    Assignee: Proton World International N.V.
    Inventors: Ronny Van Keer, Youssef Ahssini
  • Patent number: 9008260
    Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Proton World International N.V.
    Inventors: Michel Dawirs, Jean-Louis Modave
  • Patent number: 8964931
    Abstract: A counter is provided, where, as the number of events that occur increases, the frequency in which the events are counted is scaled.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Joseph Daniel Gleason
  • Patent number: 8949493
    Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: February 3, 2015
    Assignee: Altera Corporation
    Inventors: Curt Wortman, Chong H. Lee, Huy Ngo
  • Patent number: 8941408
    Abstract: Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: January 27, 2015
    Assignee: Altera Corporation
    Inventors: Jun Pin Tan, Kiun Kiet Jong
  • Patent number: 8848858
    Abstract: Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Christopher B. Wilkerson, Scott Robinson, Shih-Lien Lu
  • Patent number: 8761332
    Abstract: A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: June 24, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Lothar K Felten, Lars Lotzenburger
  • Patent number: 8755484
    Abstract: Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: June 17, 2014
    Assignee: Tabula, Inc.
    Inventors: Brad L. Hutchings, Jason Redgrave, Dai Huang, Steven Teig
  • Patent number: 8693615
    Abstract: Methods and structures that implement an event counter in a RAM are provided. A method includes providing a count-RAM, a carry-RAM, and a pre-counter corresponding to an event source. A column in the count-RAM and a column in the carry-RAM represent a value of a value of the event counter. The method further includes storing a count of the event counter received via the pre-counter in the count-RAM and the carry-RAM in a transposed, bit-serial format, such that location zero of the count-RAM and the carry-RAM counts the least significant bit (LSB) of the event counter.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Narasimha R. Adiga, Peter H. Hochschild, Ashutosh Misra
  • Patent number: 8693614
    Abstract: A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: April 8, 2014
    Assignee: NXP B.V.
    Inventors: Craig A. MacKenna, Neil E. Birns
  • Patent number: 8660233
    Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: February 25, 2014
    Assignee: Proton World International N.V.
    Inventors: Michel Dawirs, Jean-Louis Modave
  • Publication number: 20140037042
    Abstract: Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Inventors: James W. Tschanz, Christopher B. Wilkerson, Scott Robinson, Shih-Lien Lu
  • Publication number: 20140009297
    Abstract: A transient electrical energy strike detector is disclosed. The detector may be integral with the circuitry of a fire alarm panel of a fire alarm system and may identify and record transient electrical energy strikes sustained by the electrical protection circuitry of the system. Particularly, voltage fluctuations in the fire alarm panel circuitry that are outside of a predefined operating voltage range may be identified by the pulse detector as representing transient electrical energy strikes. The pulse detector may increment a counter upon the occurrence of each identified transient energy strike, and may maintain a comprehensive record of such strikes in a memory unit, including a magnitude, duration, time, and date of each strike.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Applicant: SIMPLEXGRINNELL LP
    Inventors: Mark P. Barrieau, Daniel Cianfrocco
  • Patent number: 8589641
    Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: November 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Brian Huber, Frank Ross, David R. Brown
  • Publication number: 20130156146
    Abstract: Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.
    Type: Application
    Filed: October 4, 2012
    Publication date: June 20, 2013
    Applicant: TABULA, INC.
    Inventor: Tabula, Inc.
  • Patent number: 8438414
    Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicates a first one of the increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: May 7, 2013
    Assignee: Dell Products, LP
    Inventors: Nikolai Vyssotski, Allen C. Wynn, John Hentosh
  • Patent number: 8413004
    Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michele Franceschini, John Peter Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mark N. Wegman
  • Publication number: 20130054195
    Abstract: The present invention is directed to a system and apparatus employing an ultralow power, pulsed data collection apparatus having multiple detector channels, such as 64 channels. The system and apparatus has a small volume and power requirements, enabling launch and deployment from commercial spacecraft, such as pursuit to the CubeSat and other nanosatellite protocols.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicants: National Aeronautios and Space Administration
    Inventors: Hollis H. Jones, Federico A. Herrero, Duncan M. Kahle
  • Publication number: 20130028369
    Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 31, 2013
    Applicant: Proton World International N.V.
    Inventors: Michel Dawirs, Jean-Louis Modave
  • Patent number: 8345816
    Abstract: Methods and structures that implement an event counter in a RAM are provided. A method includes providing a count-RAM, a carry-RAM, and a pre-counter corresponding to an event source. A column in the count-RAM and a column in the carry-RAM represent a value of a value of the event counter. The method further includes storing a count of the event counter received via the pre-counter in the count-RAM and the carry-RAM in a transposed, bit-serial format, such that location zero of the count-RAM and the carry-RAM counts the least significant bit (LSB) of the event counter.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Narasimha R. Adiga, Peter H. Hochschild, Ashutosh Misra
  • Publication number: 20120321032
    Abstract: A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Inventors: Bo Liu, Jongmin Park, Chen Chen, Tien-chien Kuo
  • Patent number: 8327091
    Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: December 4, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Brian Huber, Frank Ross, David R. Brown
  • Patent number: 8295428
    Abstract: Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: October 23, 2012
    Assignee: Tabula, Inc.
    Inventors: Brad Hutchings, Jason Redgrave, Dai Huang, Steven Teig
  • Publication number: 20120230460
    Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicates a first one of the increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.
    Type: Application
    Filed: May 18, 2012
    Publication date: September 13, 2012
    Applicant: DELL PRODUCTS, LP
    Inventors: Nikolai Vyssotski, Allen C. Wynn, John Hentosh
  • Patent number: 8195973
    Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicating a first increment field of the plurality of increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: June 5, 2012
    Assignee: Dell Products, LP
    Inventors: Nikolai Vyssotski, Allen C. Wynn, John Hentosh
  • Patent number: 8189732
    Abstract: A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the “not current” binary counter with the final write operation being to the linear counters. The linear counter write operations can be in program-only mode so that a power failure will not result in a loss of counts.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: May 29, 2012
    Assignee: Atmel Corporation
    Inventors: Randall Wayne Melton, Brad Phillip Garner, Kerry David Maletsky
  • Patent number: 8175213
    Abstract: A system and method for configuring threshold values for fixed time delay counters of a System on a Chip (SoC) uses a reference clock signal and one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal. A frequency sub-range of the reference clock signal is determined using the frequency sub-range control signals and the determined frequency sub-range is used to select a counter threshold value. The selected counter threshold value is provided to a counter and the counter then is updated at each cycle of the reference clock signal for a predetermined count based on the counter threshold value.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: May 8, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Deepak Jindal
  • Publication number: 20120027159
    Abstract: A system and method for configuring threshold values for fixed time delay counters of a System on a Chip (SoC) uses a reference clock signal and one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal. A frequency sub-range of the reference clock signal is determined using the frequency sub-range control signals and the determined frequency sub-range is used to select a counter threshold value. The selected counter threshold value is provided to a counter and the counter then is updated at each cycle of the reference clock signal for a predetermined count based on the counter threshold value.
    Type: Application
    Filed: July 28, 2010
    Publication date: February 2, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventor: Deepak JINDAL
  • Patent number: 8064567
    Abstract: A method for the incrementation of counter statuses in memory cells, which are arranged respectively in rows and columns of a first memory adds a “1” to the memory content of a memory cell of a second memory, which corresponds to the memory cell at the start of a sequence of memory cells to be incremented in a row or column of the first memory in the case of every incrementation of a sequence of memory cells of the first memory, and adds a “?1” to the memory content of a memory cell of the second memory, which corresponds to the memory cell immediately following the memory cell at the end of the sequence of memory cells to be incremented associated with the start of the sequence, in the case of every incrementation of a sequence of memory cells of the first memory.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: November 22, 2011
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Kurt Schmidt
  • Patent number: 8027425
    Abstract: The disclosed embodiments relate to an asynchronous down counter, which can be loaded with any value N and then decrement exactly N times. The counter comprises an array of cells, wherein each cell is configured to hold a digit in a redundant base-k representation of a number contained in the array of cells. Each cell further comprises a finite state machine that defines state transitions between states, where these states are held on wires and state transitions are synchronized between neighboring cells. Each cell is further configured to asynchronously borrow, if possible, from a more significant adjacent cell to increase a value of a digit in the cell. This asynchronous borrowing improves performance by ensuring that a decrement operation, which decrements a digit in a least significant cell in the array, will borrow from an adjacent more significant cell, without having to wait for the completion of a rippling sequence of borrows from more significant cells.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: September 27, 2011
    Assignee: Oracle America, Inc.
    Inventors: Josephus C. Ebergen, Adam Megacz
  • Publication number: 20110206176
    Abstract: Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 25, 2011
    Inventors: Brad Hutchings, Jason Redgrave, Dai Huang, Steven Teig
  • Publication number: 20110103540
    Abstract: A method comprises loading by logic a storage location with a count value. The count value comprises a plurality of upper order bits and a plurality of lower order bits. The method further comprises detecting, by said logic, an event and, based on detecting the event, sequentially changing the count value with the lower order bits changing according to base-1 counting and the upper order bits changing according to a counting scheme in which the upper order bits encode all possible binary values of the upper order bits.
    Type: Application
    Filed: October 29, 2009
    Publication date: May 5, 2011
    Inventor: Gary M. WASSERMANN
  • Patent number: 7877759
    Abstract: A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Alan G. Gara, Michael K. Gschwind, Valentina Salapura
  • Patent number: 7861126
    Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.
    Type: Grant
    Filed: June 29, 2008
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Carl E. Love, Donald R. DeSota, Jaeheon Jeong, Russell M. Clapp
  • Publication number: 20100290580
    Abstract: Timing circuitry may use control circuitry to control calibration circuitry to calibrate a counter so that an adder and a calibration period counter are not required. Concatenation circuitry may be used to concatenate a portion of the counter value and the calibration value to provide a calibrated value to the counter. The results from match circuitry may be used to provide status and control information to a calibration history bit and to an enable circuit. The counter may be an up counter or a down counter.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 18, 2010
    Inventor: Evgeni Margolis
  • Patent number: 7809901
    Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: October 5, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Brian Huber, Frank Ross, David R. Brown
  • Patent number: 7782995
    Abstract: A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Alan G. Gara, Valentina Salapura
  • Patent number: 7735031
    Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Valerie Hornbeck Chickanosky, Kevin William Gorman, Emory D. Keller, Michael Richard Ouellette
  • Publication number: 20100102203
    Abstract: A pulse data recorder system and method are provided. Upon the arrival or occurrence of an event or signal, the state of a digital switch is set. Upon receiving a pulse from a readout clock, the state of the switch is stored in a buffer memory, and the state of the switch is reset. As the readout clock is run, a time history of the state of the switch is obtained. The pulse data recorder can feature a plurality of unit cells, for use in imaging or other multiple pixel applications.
    Type: Application
    Filed: January 21, 2009
    Publication date: April 29, 2010
    Applicant: BALL AEROSPACE & TECHNOLOGIES CORP.
    Inventor: Christian J. Grund
  • Patent number: 7688931
    Abstract: A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Alan G. Gara, Valentina Salapura
  • Patent number: 7573969
    Abstract: A counting device includes a set of memory cells, which are configured to store respective bits of a count code. A controller is coupled to the memory cells so as to increment, in response to occurrences of a count input, the count code in the set of the memory cells from an initial value up to a preset bound in each of a plurality of successive iterations, and to shift the bits of the count code that are respectively stored in the memory cells in each of the iterations relative to a preceding iteration.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: August 11, 2009
    Assignee: Sandisk Il Ltd.
    Inventors: Eran Shen, Rotem Sela, Aviad Zer, Oren N. Honen, Ido Shilo
  • Patent number: 7551706
    Abstract: A counter device includes: a rewritable counter having a non-volatile memory which requires sector erasure to once turn all data in a sector into high data, prior to changing low data into high data in respective bits; and a control section updating a counter value of the rewritable count by writing in and reading out the data with respect to the rewritable counter using a complement of 1, and thereby controlling writing in and reading out the data of the rewritable counter.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: June 23, 2009
    Assignee: Kyocera Mita Corporation
    Inventor: Seigo Takagi
  • Patent number: 7532700
    Abstract: A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: May 12, 2009
    Assignee: International Business Machines Corporation
    Inventors: Alan G. Gara, Valentina Salapura
  • Publication number: 20090116610
    Abstract: A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set.
    Type: Application
    Filed: May 30, 2008
    Publication date: May 7, 2009
    Applicant: International Business Machines Corporation
    Inventors: Alan G. Gara, Valentina Salapura
  • Publication number: 20090116611
    Abstract: A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
    Type: Application
    Filed: May 14, 2008
    Publication date: May 7, 2009
    Applicant: International Business Machines Corporation
    Inventors: Alan G. Gara, Valentina Salapura
  • Patent number: 7526059
    Abstract: A counting device includes a set of memory cells, including multiple groups of the memory cells configured to store count words of a count code, which include a less significant word and a more significant word. A controller assigns first and second groups of the memory cells to store the less significant word and the more significant word. The controller increments the less significant word from an initial value up to a first limit in each plurality of successive first iterations and increments the more significant word from an initial value up to a second limit in each of a plurality of successive second iterations in response to reaching the first limit. Upon reaching the second limit, the controller makes a new assignment of the groups of the memory cells that are to store the less significant word and the more significant word.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: April 28, 2009
    Assignee: Sandisk IL Ltd.
    Inventors: Eran Shen, Boris Dolgunov
  • Publication number: 20090086880
    Abstract: A counting device includes a set of memory cells, which are configured to store respective bits of a count code. A controller is coupled to the memory cells so as to increment, in response to occurrences of a count input, the count code in the set of the memory cells from an initial value up to a preset bound in each of a plurality of successive iterations, and to shift the bits of the count code that are respectively stored in the memory cells in each of the iterations relative to a preceding iteration.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: SANDISK IL LTD
    Inventors: Eran Shen, Rotem Sela, Aviad Zer, Oren N. Honen, Ido Shilo