Abstract: A counter circuit, which may be on a semiconductor integrated circuit, that is applicable to both a linear sequence and an interleave sequence and is capable of setting a burst length at 1, 2, 4, 8, or 2.sup.n in both sequences. The burst length of the counter circuit may be changeable, and the counter circuit may output a signal indicating whether the count number has reached the burst length.

Abstract: A circuit for counting events occurring between two different clock domains includes a gray code counter having at least two stages. The gray code counter is incremented by the event to be counted. Dual rank synchronizer circuit and delay flip/flops are coupled to the counter. The circuit includes a comparison logic circuit fed by outputs from the dual rank synchronizers and the delay flip/flops to produce an output signal having a binary value corresponding to a number of events that occurred between transitions of the second clock.

Abstract: The present invention is directed to a circuit for detecting the end of a burst count in a semiconductor memory device. The circuit is responsive to a plurality of burst counter output bits and a plurality of burst length selection bits. The circuit is comprised of an array of individual semiconductor devices responsive to the burst counter output bits and the burst length selection bits for producing a transition in an output signal when the burst counter output bits are at a logical combination determined by the burst length selection bits. A method for detecting the end of a burst count in a semiconductor memory device is also disclosed.

Abstract: A programmable shift register in which the length (e.g., number of bits), number and location of taps, operating mode (i.e., counting up/down) and number of skip states are configured by programming selected memory cells. The programmable shift register includes a plurality of flip-flops, a programmable interconnect circuit, a next-state control circuit and a mode control circuit. The output terminal of each flip-flop drives a different bus line in the programmable interconnect circuit. Each bus line is programmably connected to a plurality of I/O lines via programmable interconnect points (PIPs). At least two of the second lines are connected to the input terminal of each flip-flop via portions (e.g., multiplexers) of the mode control circuit. Programming the PIPs to link selected flip-flop input and output terminals forms one or more shift registers of a selected length.

Abstract: A high modulus counter is provided for receiving a counter enable (CE) signal which switches between digital states. The counter is a single load conditional look ahead counter having a carry chain isolated from a timing critical path. The counter includes one toggle flip-flop for receiving the CE signal. The flip-flop has a first output and a second output. The first output and the second output are connected to an even counter and an odd counter, respectively. Both the output of the first counter and the output of the second counter are received by each of a plurality of multiplexers which are controlled by the first output of the toggle flip-flop. In this way, the high modulus counter outputs and increments the pointer signals of the odd counter and the even counter, alternatively. The even and odd internal counters are initially set at zero and one, respectively, and each increments by two. A second flip-flop may additionally receive the external CE signal for synchronization.

Abstract: The present invention discloses a memory device having a pipe counter. It provides the advantages in that it can reduce by about 50% the number of transistors needed in constructing a pipe counter while performing the same functions as a conventional pipe counter, thereby reducing the circuit area and decreasing the driving current of the counter, by applying the concept of a ring counter to a pipe counter used in a data output terminal of DRAM.

Abstract: The shift register includes a front stage latch portion for inputting input data when a clock signal is at a first level and latching the input data when the clock signal is at a second level, a rear stage latch portion for inputting data from the front stage latch portion when the clock signal is at the second level and latching the input data when the clock signal is at the first level, an input switch for connecting a data input terminal to the front stage latch portion when a mode switching signal is at a first level, and a feedback switch for connecting the rear stage latch portion to the front stage latch portion when the mode switching signal is at a second level. A latch mode clock signal is provided as the aforementioned clock signal when the mode switching signal is at the first level, and a counter mode clock signal or front stage shift register latch output signal is provided as the aforementioned clock signal when the mode switching signal is at the second level.

Abstract: A method is provided for preventing odometer fraud on a vehicle having a multiplex ring including a plurality of vehicle control modules in electrical communication with each other. The multiplex ring includes a cluster control module with an odometer display. The method includes: a) displaying an odometer mileage variable; b) periodically storing the displayed odometer mileage variable in a non-volatile memory location in the cluster control module; and c) periodically storing the displayed odometer mileage variable in a non-volatile memory location in at least one of the vehicle control modules other than the cluster control module, thereby increasing the level of difficulty of odometer tampering.

Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.

Abstract: A method of accumulating and maintaining the accumulated data comprises steps of maintaining an intermediate count in a first memory device (12), reading a plurality of count values from a second memory device (14), determining a greatest count value of a subset of the plurality of count values which satisfy at least one criterion, and determining an updated count based upon the intermediate count and the greatest count value. The at least one criterion includes a criterion that the greatest count value differs from a second greatest count value of the subset of the plurality of count values by at most a predetermined difference greater than one. A system and a device to perform the method are detailed.

Abstract: A real time clock plus user memory and extra memory integrated in a single circuit with access to the extra memory either by direct addressing or by providing the address as data to specified addresses in the user memory. Further, the user memory has two banks with the same addresses, and bank selection derives from a bit in another portion of the user memory.

Abstract: A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter that starts counting when transmission by either the port it is associated with is transferring a cell, or when another port is transferring a cell on a channel that conflicts with the channel attached to the port. The counter counts the appropriate number of digits corresponding to the length of the cell whereupon the port is provided with a signal indicating that the transmission has ended. In association with other control signals, the port may then begin transmitting a new cell. When multiple switches are attached to the same channel, the counter serves as a self-queuing mechanism that relieves a central controller from having to keep track of the transmission of bits by each port, and from having to select the next port for transmission.

Abstract: A high-speed predecoding address counter circuit comprising at least three tetrad counters connected in series, each for inputting an external 4-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific logic value at its four output terminals in response to a clock signal, a first clock switching unit responsive to a logical value of a most significant bit of an output signal from a lowest-order one of the at least three tetrad counters, for transferring the clock signal to a higher-order one of at least three tetrad counters, at least one logic unit for detecting whether both most significant bits of output signals from at least two lower-order ones of the at least three tetrad counters have the specific logic value, and at least one second clock switching unit connected between at least one logic unit and at least one of the at least three tetrad counters other than the at least two lower-order tetrad counters, for switching the clock signal to the at le

Abstract: A method for the resetting of a group of series-connected non-transparent synchronous memory cells. The method includes modifying the clock signals that control the transfer gates of these cells on the activation of a resetting signal to set all the transfer gates in the on state. The method is particularly suited to the resetting of long shift registers such as those used in cryptographic applications, especially in micro-circuit cards, and the reset circuitry can be implemented using conventional logic gates.

Abstract: The present invention is directed to a decoder circuit that can be operated at higher frequencies of a RLL clock. RLL data input from a disk drive is shifted through a first stage of the decoder circuit by the standard RLL clock. The RLL data is shifted from the first stage through a second stage of the decoder circuit by a modified RLL' clock that operates at a lower frequency than the RLL clock. In a preferred embodiment, RLL' clock operates at one-third the frequency of the RLL clock. The decoding step is accomplished within the period of one clock cycle of the slower RLL' clock, which affords the decoder circuit of the present invention a sufficient amount of time to decode the RLL data from the disk drive into NRZ data for the host. Since RLL' clock used in the decoding step is slower, the RLL clock used to generate RLL' clock and to clock data into the decoder circuit from the disk drive can be operated at a higher frequency than currently possible.

Abstract: A counting circuit including destructive memory elements detection circuits for detecting whether the memory elements are broken, and control circuits for controlling the supply of a break current to the memory elements in a plurality of stages. A current feed circuit supplies the break current for breaking the memory elements in the counting circuit every time a to-be-counted write pulse is input. The control circuit in each stage of the counting circuit supplies the break current from the current feed circuit to the memory element of the stage based on a detection result of the detection circuit only when the memory element of the stage is unbroken while the memory element of a stage preceding the memory element is broken. The control circuit of the first stage supplies the break current to the memory element of the first stage when the memory element of the first stage is unbroken.

Abstract: A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter that starts counting when transmission by either the port it is associated with is transferring a cell, or when another port is transferring a cell on a channel that conflicts with the channel attached to the port. The counter counts the appropriate number of digits corresponding to the length of the cell whereupon the port is provided with a signal indicating that the transmission has ended. In association with other control signals, the port may then begin transmitting a new cell. When multiple switches are attached to the same channel, the counter serves as a self-queuing mechanism that relieves a central controller from having to keep track of the transmission of bits by each port, and from having to select the next port for transmission.

Abstract: A real time clock plus user memory and extra memory integrated in a single circuit with access to the extra memory either by direct addressing or by providing the address as data to specified addresses in the user memory. Further, the user memory has two banks with the same addresses, and bank selection derives from a bit in another portion of the user memory.

Abstract: According to the present invention there is provided an encoder, which in one embodiment, includes a processing circuit which generates an output code according to an encoding algorithm, a counter circuit for incrementing a counter value such that only one bit of the counter value changes each time the counter value is incremented, a non-volatile memory for storing the counter value, and a transmitter which transmits the output code and the counter value. In another embodiment of the invention there is provided a method for use with an encoder having a processing circuit which generates an output code according to an encoding algorithm, a counter circuit for incrementing a counter value, a non-volatile memory for storing the counter value, and a transmitter which transmits the output code and the counter value. In one embodiment, the method includes the steps of incrementing the counter value such that only one bit is changed each time the counter is incremented.

Abstract: A frequency converter is provided of which a frequency-dividing ratio is arbitrarily altered and retained after a power is turned off. The frequency converter has a programmable counter which outputs a signal having a desired frequency, a non-volatile memory for storing data for setting the frequency-dividing ratio and a control unit for controlling a writing operation of data stored into the non-volatile memory. The programmable counter, the non-volatile memory and the control unit are accommodated in a single package. The frequency converter may comprise a resonator and an oscillating circuit within the package so that the frequency converter can be treated as a single frequency generator such as a quartz-crystal oscillator.

Abstract: The current invention provides a timer circuit for timing a plurality of time periods. The timer circuit has a timing pulse input for receiving timing pulses; a set of state outputs being at a set of logic states, each logic state taking one of two logic values, the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs, each providing a signal at the expiry of a predetermined time period; and a resetting signal for resetting the timing circuit and for defining an initial set of logic states. The set of logic states follows a first sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within each set are at a first logic value (1) except at least one logic state, which is at a second logic value (0), different state outputs carrying the excepted state(s) in each of the sets of logic values within the first sequence of sets of logic values.

Abstract: A periodic signal is produced by counting pulses of a clock during a given period of time. The number of pulses counted is divided by a whole number. A count is then made of a batch of pulses of this clock, the number of pulses in this batch corresponds to the quotient of this division. At each time a batch is completed, a value of a periodic signal is produced.

Abstract: In data logging applications, a method and apparatus are disclosed for storing an increasing number of consecutive real-time data points, such as those descriptive of AC (alternating current) power line parameters, in a fixed amount of memory by periodically applying a novel compression technique. The compression technique preserves time relationships in the data while maximizing the level of detail consistent with a limited amount of memory. When the memory is full each data point stored is paired with another data point and one value is calculated that will represent the pair of data points, reducing the necessary memory to half and allowing more data points to be stored.

Abstract: A history recording apparatus comprises an EEPROM for storing operation history data regarding a predetermined operation performed by a label printer, and an IC socket provided on a circuit board of the label printer and detachably connectable to the EEPROM. In particular, the history recording apparatus further comprises a CPU for updating the operation history data stored in the nonvolatile memory connected to the IC socket, upon detection of the predetermined operation having been performed a preset number of times which is determined on the basis of a writing tolerance limit of the EEPROM.

Abstract: A non-volatile electronic counter provides a substantially increased maximum count by utilizing a ring counting sequence to count the first n-1 events out of every n events, and a base-2 counting sequence to count each nth event. Each counting position of the ring counting sequence and the base-2 counting sequence is implemented with a memory stage that stores the logical state of the counting position when power is removed. Each memory stage can be implemented with redundant memory cells and voting logic, which provides the logic state represented by a majority of the redundant memory cells, to increase the reliability of the count.

Abstract: A programmable time-intervals generator comprising first and second digital counters, a memory, a digital divider and a digital adder. On the occurrence of a first event, the first counter starts counting, and on the occurrence of a second event, only the most significant bits of the number counted up to then are stored, thereby providing a division by truncation. From the stored number, at least two discrete fractions are obtained by the divider, whereafter said fractions are summed at the adder which operates on strings of bits. The second counter counts down the sum number and, on becoming cleared, generates a signal.

Abstract: An apparatus for recording driving data which comprises a data gathering device, which further comprises a sensory measuring device, a control unit, an A/D converter, a plurality of parallel ring storage devices and a semiconductor storage device. Analog measurement signals, which are continuously detected by the sensory measuring device, for recording a vehicle movement, are continuously sensed by the control unit with two different frequencies after being digitized into digital measurement signals in the A/D converter. The digital signals are stored in the plurality of parallel ring storage devices with clock frequencies.

Abstract: A counter has a memory which stores at least three continuous numerical values and a controller which rewrites a lowest numerical value to a numerical value obtained by adding 1 to a largest numerical value within said continuous numerical values stored in the memory and discriminates whether or not said numerical values stored in the memory are continuous to judge a count error. When said numerical values stored in the memory are not continuous, the noncontinuous numerical value is corrected by adding 1 to the largest value of other continuous numerical values stored in said memory.

Abstract: A bit clock regenerating circuit comprising an edge detector made up of two flip-flops for detecting edges of a binary signal and a gating circuit, a counter receiving an edge detected pulse from the edge detector as a load signal for setting an initial value, counting clock pulses with a given frequency, and generating a bit clock according to the result of the counting, and a ROM in which multiple conversion tables are formed to supply an initial value for the counter according to an output value of the counter, and a conversion table for determining regeneration conditions is selected according to a switching signal.

Abstract: A race-free arithmetic operation circuit is disclosed. The circuit comprises a register file array, an arithmetic logic unit (ALU), and apparatus for controlling the input and/or the output signal of the ALU. The apparatus for controlling can be two level-sensitive latches, located before and after the ALU, or one master-slave flip-flop, located either before or after the ALU.

Abstract: A vehicle classification system automatically identifies types of vehicles traveling along a vehicle lane of toll road. The system has a detector for detecting the passage of the vehicle at a plurality of positions along the vehicle lane. The system further has a pickup device for picking up profile information of the vehicle in accordance with the detected passage and an identification device for identifying the vehicle type based on the detected profile information.

Abstract: A counter for attribute stored in an Ethernet system is partitioned such that the storage section is separated from the incrementors section. In so doing, counters are implemented in a significantly less space than if the counters were implemented as individual counters. The counter utilizes random access memory as the storage section and a 32 bit incrementor. As the incrementor section along with a pair of latches to implement the counter.

Abstract: The disclosure relates to counters that require the counting to be done under conditions of high security. In such a counter, starting from a number represented by a certain number of bits, the stages of the counter are successively forced, one after the other, to represent the final number in an order such that at no instant do the contents of the counter represent a number smaller than the initial number. A particular structure is used to count very big numbers while, when the technology is of the EEPROM type. This prevents the stage that changes its state most frequently from being subjected to action more than is physically permitted by the technology used. The disclosed method makes it possible, in chip cards, to prevent the diminishing of memorized values representing substantial values which are, for example, monetary values.

Abstract: A method and circuitry are provided for modularized single transition counting. A count signal is provided on a count line (436). A single transition count is modified in response to the count signal. The single transition count has a plurality of bits (418, 416) provided by at least one first module (404) and at least one second module (406). The first (404) and second (406) modules are alternately coupled in series to an input module (402) so that one (404) of the first and second modules has an input (460a, 466a) coupled to an output (420, 468) of the input module (402) and so that each additional one (406) of the first and second modules has an input (482a, 488a) coupled to an output (472a, 478a) of an associated one (404) of the second and first modules, respectively.

Abstract: The invention includes a data memory having sequentially stored N-bit words that are each a binary description of a time at which an event is to occur. Also stored is a K-bit word, associated with each N-bit word, that is a binary description of what the scheduled event is to be. The invention utilizes a free-running clock and clock circuitry to gauge when an event should occur. The clock circuitry tallies an N-bit description of running time. M-bits of the N-bit description of running time are specified by a single fast synchronous counter. The remaining N-M bits are specified by two slow counters each of N-M bit capacity. Because incrementation of slow counters creates count settling times that may significantly affect accurate event sequencing, the slow counters are alternately incremented and a multiplexer is used to switch to the counter that will provide a "steady state" count at a scheduled event time.

Abstract: A high security counting system is shown for counting events represented by an event signal. The counting system includes a nonerasable programmable read only memory which is programmed by a programmer under the control of a controller. The controller is responsive to an event signal for controlling the programmer to program a bit from a first value to a second value wherein each bit programmed to a second value represents a unit of count and the number of bits programmed to the second value represents the count of said counter.

Abstract: A sampling device operating as a buffer between a first data signal and a relatively slow processing device accepts the input signal and stores samples of it on a SAW traveling past an input electrode. A blocking potential is applied to a set of electrodes to store a set of charge packets with the SAW device. Packets are consecutively released at a slower rate accommodated to the needs of the next processing unit in line, to read out the sampled signal at a modified rate for intentional distortion of the input signal, for slowing the output stored signal rate, or for time reversal of the signal.

Abstract: A counter has an electrically erasable and programmable read-only memory (EEPROM), a write circuit, and a read circuit. The EEPROM, which can be rewritten at least V times, is divided into count areas M.sub.O, . . . , M.sub.N each capable of storing count values from zero to V, and a number area for storing a number K from zero to N identifying the count area currently in use. The write circuit uses the count areas M.sub.O, . . . , M.sub.N in succession to store counts as high as N.times.V. The read circuit obtains the current count value by reading K from the number area, reading the contents C of the Kth count area M.sub.K, and calculating C+(V.times.K).

Abstract: A non-volatile counter memory is provided by using a gray code scale to store counter values in a plurality of counter memories (34) comprising a counter memory group (38). Each counter memory comprises a plurality of units which store a gray coded value. The weighting of the units is changed after a predetermined number of write operations such that the number of bit transitions is spread out among the units.

Abstract: For one of memory divisions that is selected at a time as a selected division N(m) in a memory for use in putting a sound processing device in operation of generating a three-dimensional image of an acoustic field, a difference signal is produced to represent a clock count minus a delay count n(m) specific to the selected division and to have more and less significant bits. For use as an address signal supplied to the memory, a part of the more significant bits is changed to a like part of a memory space address specific to the selected division. As usual, the less significant bits are used to indicate read aR(i(m)) and write W(i(m)) pointers which are spaced in the selected division by the delay count. The part may be specified to be wide and narrow when the selected division is narrow and wide. Alternatively, the part may have a predetermined bit width.

Abstract: An updown counter up-counts binary data stored in respective flip-flops in an up-count mode, and down-counts the binary data stored in the respective flip-flops in a down-count mode. When a command for an up-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on two after converting it into a complement on one. When a command for a down-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on one after converting it into a complement on two. The converted data is used to rewrite the data stored in the respective flip-flops.

Abstract: A multiple synchronized agile pulse generator is configured as high speed digital/analog test apparatus for providing complex patterns associated with modern avionics systems. The multiple synchronized agile pulse generator includes a network of counters and random access memory (RAM) banks which allow for predetermined hopping of pulse repetition intervals, pulse widths, pulse patterns, pulse amplitudes, and combinations of the above.

Abstract: An uninterrupted event-time recorder enables high-precision measurements of the time-of-occurrence of randomly- and rapidly-occurring, digitally specified events such as the leading and/or trailing edges of asynchronous pulses. The lowest order binary digits of the recorder are constructed of high-speed synchronous integrated circuit counter devices. For an N-bit timer having M low-order bits, the highest order (N-M) bit counting is executed by two parallel (N-M)-bit slow-speed counters, one of which is incremented by the terminal count of the M-bit high-speed counter and the other which is incremented by the most significant bit (MSb) of the M-bit counter. The (N-M)-bit counters are read out through a multiplexer controlled by the MSb.

Abstract: An interleaving method and apparatus suitable for burst error correction occurring in data transmission or reading of recording medium. In the interleaving method in which data to be transmitted is once written in a storing means and then read to be output in order different from a writing order, a plurality of counters for dividingly generating addresses of the storing means is used; and an operational relationship between the counters is changed between writing and reading of the storing means. ROMs for address translation can be omitted so that the number of gates is reduced very much. Thus, a reasonable interleaving apparatus suitable for LSI formation can be realized. In addition, since ROMs for address translation interposed between the counter and the storing means in the conventional apparatus are omitted, access time for the storing means can be shortened substantially.

Abstract: A preferred embodiment of the present invention comprises a pedometer having a housing, a weighted pendulum, a magnet and reed switch, a microprocessor, a LCD display, three push-bottons, a hinged door with a spring cam device that holds the door open and shut, and a replaceable belt hook. The entire unit is powered by an oversized lithium battery that has an expected life of seven years. A unique method of user calibration simplifies user input and provides maximum calibration accuracy regardless of operational or stride artifact variations.

Abstract: A counter includes an array of memory cells arranged in groups of memory cells, each group designating a counting decade, wherein each group of memory cells includes first and second word strings, each capable of storing a data word, and a fault flag, capable of indicating which word string contains the data word; sensing means coupled to the memory array for checking the status of the memory cells and for generating fault signals upon detection of a fault in a memory cell; logic means coupled to the memory cells and to the sensing means for selecting the first or second word string in response to a fault signal; wherein upon detection of a fault in a first word string, the data word is written into the second word string; and a central shifting unit coupled to the memory array for reading a data word stored in a word string into the shifting unit, incrementing the data word, and writing the incremented data word into its respective word string.

Abstract: An autoclave or other equipment has a counter provided by an EEPROM for counting the number of times the autoclave has been used. The EEPROM has a first set of ten registers which contain the unit value of the count together with a fault code associated with the last use of the autoclave. Two further registers contain the hundreds and tens, and the ten thousands and thousands value of the count. The tens value in one of the further registers is used to determine in which of the registers of the first set the units value is stored, so that each of the registers in the first set is only written into ten times for every hundred counts, thereby extending the life of the EEPROM. Another register in the EEPROM contains information about the nature of the autoclave.

Abstract: A waveform formation device according to the present invention comprises a memory storing rise time data and fall time data related to an output waveform, a first timing generator for producing a set signal at a timing related to the rise time data, and a second timing generator for producing a reset signal at a timing related to the fall time data. A flip flop circuit of the device produces an output signal which rises in response to the set signal and falls in response to the reset signal.

Abstract: A measurement mechanism which can be implemented in any complex system for measuring the service times required for carrying out specified operations is described for a system having a plurality of components working in pre-emptive mode so that an operation once started by a component can be suspended to perform other operations which are requested by the same or other components if these operations have higher priority levels. The measurement mechanism includes a current status register 16 in which the system causes a status value to be stored representative of the current operation being performed by the system. It also includes a reference status register 18 in which a reference value representative of the operation to be measured is stored. These values are compared through a compare logic circuit under control of a filtering value stored in another register. When a match is detected by the compare circuit, the content of a counter is incremented.

Abstract: A card counter (10) prints card inventory information locally and communicates with a remote computer (43) for permanent storage and retrieval of inventory information. A microprocessor controller detects a counting error in response to the actual count failing to match a preset count, failing to match a precount information machine read from a machine readable precount label (130) attached to the cards (18), in the event of a phrase error from a pair of parallel scanning card sensor circuits (58, 59) or if the final counts of the two card sensor circuits (58, 59) do not match. In the event of detection of a counting error, an error indication is provided and entry of the count into an accumulator memory is inhibited. The present number is entered into memory by selectively entering an actual count into the preset memory. A pair of separate accumulators are provided for concurrently accumulating totals of two different groups of cards (18).