Abstract: A time delay circuit for providing a delayed replica of a digital input signal including first and second counters for providing first and second count outputs offset relative to each other by a predetermined value indicative of a predetermined delay, and further including a first-in first-out (FIFO) memory for controllably storing selected values of the digital input signal together with corresponding first count output values. First comparison circuitry compares each digital input with the immediately prior digital input, and controls the FIFO memory to store (a) each digital input which is different from the immediately prior digital input, and (b) the first counter output value associated therewith.

Abstract: A timing system using shared address generator(s) to address memories that form the basis of each pin's timing reference generator can reduce the amount of hardware required to implement a "Timing Generator Per Pin" architecture in a VLSI tester by at least 50%.

Abstract: An apparatus and method for testing the integrity of wiring cables provides a transmitter and a receiver that electrically connect to opposite ends of group of wires to be tested. The transmitter produces a voltage test signal applied to a test set of wires and a different voltage reference signal is applied to a reference set of wires. At the receiver, indicator circuits interconnect the wires to a common bus. The reference signal is applied to the common bus and, when the test signal is present, the indicators operate to produce a display. The test signal can be cycled through a plurality of test sets making up the entire test group.

Abstract: A card counter (10) prints card inventory information locally and communicates with a remote computer (43) for permanent storage and retrieval of inventory information. A microprocessor controller detects a counting error in response to the actual count failing to match a preset count, failing to match a precount information machine read from a machine readable precount label (130) attached to the cards (18), in the event of a phase error from a pair of parallel scanning card sensor circuits (58, 59) or if the final counts of the two card sensor circuits (58, 59) do not match. In the event of detection of a counting error, an error indication is provided and entry of the count into an accumulator memory is inhibited. The preset number is entered into memory by selectively entering an actual count into the preset memory. A pair of separate accumulators are provided for concurrently accumulating totals of two different groups of cards (18).

Abstract: A hubodometer (10) for attachment to a vehicle's wheel structure for sensing a rotation of the wheel structure and for converting the sensed rotation to a distance travelled. The hubodometer comprises an outer housing (12) having a permanent magnet (28) affixed thereto for generating a magnetic field and a coupler (14) for coupling the housing to the wheel structure such that the outer housing rotates therewith. The hubodometer further comprises an anti-rotation mechanism (16) rotatably coupled within the outer housing, the mechanism having a plurality of components (18,20,22,24,30) coupled thereto, the components being stabilized against rotation thereby. The components include an electronic controller (20) and a plurality of magnetic field sensors (30). The plurality of sensors are disposed relative to the housing such that as the magnet rotates thereabout all of the plurality of magnetic field sensors do not simultaneously sense the magnetic field.

Abstract: A method for storing run data of a vehicle in a data memory of an electronic tachograph and displaying the run data with a predetermined resolution. The method includes the steps of sensing the movement of the vehicle, providing digital distance and velocity data from signals of the sensing step proportional to the travel distance of the vehicle and the instantaneous velocity, respectively, and reading the digital data into successive cells of the data memory of the tachograph in predetermined regular periods corresponding to a first sampling rate defining the resolution. The digital data are read into successive cells of an accident memory which has a substantially smaller storage capacity than the data memory at a rate substantially higher than the first sampling rate corresponding to regular intervals of distance traveled. Thereafter, the maximum and minimum values of the velocity and the value of the distance during each of the predetermined regular periods are determined.

Abstract: Equipment using consumables that require replacement after a predetermined number of uses includes counter arrangements for keeping track of the number of uses of each consumable. Even though some of the consumables may replace the same item, the usage count is maintained for each individual consumable. For the consumables, automatic identification of replaced items is provided whereby the counter arrangement is enabled to accumulate usage counts on the correct consumables.

Abstract: A nonvolatile memory has a linear array of memory cells to serially store counts by setting the cells one by one in correspondence with input pulses and when the array is full by resetting the cells one by one for successive pulses. When all the cells are reset a conventional binary counter is incremented and the serial count is repeated for further inputs. This procedure minimizes the erase/write sequences required to count a series of pulses. A shift register having a stage corresponding to each memory cell is used to read out the data from the linear array. Data is loaded from the array into the shift register and shifted out in a serial pulse train to a binary counter.

Abstract: There are provided a method and an apparatus for absolute position detection, in which position detection is performed with high accuracy by interpolation between feedback pulses generated as an object of position detection moves, and the power-on command displacement can be calculated with high accuracy, the method and the apparatus entailing only small electric power consumption. A stored value in an absolute counter (2), which is indicative of an approximate absolute position of an object of position detection, is updated each time a feedback pulse is generated from a feedback pulse generating circuit (1), and is retentively stored in the counter even after the power is turned off. As the object of position detection moves, moreover, the count value of interpolation pulses, generated during the time interval which elapses from the instant that the power is turned on again until the first one of the feedback pulses is generated, is temporarily stored in a correction counter (5).

Abstract: A method for detecting a fault, e.g. a short circuit, break or leakage in an electric cable or conductor, whereby two conductor pairs (1,2 and 4,5), one of which comprises the faulty conductor (1), are connected in such a way as to form a double loop (1,5 and 2,4), a voltage pulse being applied to the intact loop (2,4) to locate the fault (X). Depending on the nature of the defect, the pulse voltage is adjusted to a level sufficient to produce a malfunction, e.g. sparking, in the defective loop (1,5), whereupon the ratio of the currents produced at the ends of this loop is measured and the proportion (U.sub.1 /U.sub.2) is translated into a distance of the fault from the detector.

Abstract: A timing generator for generating a plurality of pulse sequences within a test cycle. Each pulse sequence has a plurality of pulses having a position identified by the data contents of a multiplicity of random access memories. Like numbered lower order bits of each memory are decoded to provide a plurality of pulse sequences corresponding in number to the number of lower order bits. The memories are arranged in a hierarchy. The random access memories are each provided with a separate address counter. The highest order bit of each memory is used to reset the respective memory address counter as well as enable an adjacent higher order memory address counter, and are decoded to define the end of the test cycle.

Abstract: A successive approximation register for an analog/digital converter operating according to the weighing method and having a bit width n includes a comparator and n memory elements each having one data input and one data output for shifting onward a logical "1" potential for each successive weighing step as well as for writing-in and storing in memory the particular result of weighing ascertained by the comparator. Multiplexers are associated with the n memory elements and have data input sides partially connected to the comparator. Logic elements are connected between the data outputs of the memory elements and the multiplexers for respectively controlling the data input sides of the multiplexers.

Abstract: In construction of a digital phase locked loop for detection of the angular displacement of a mobile object depending on input signals from an encoder, is provided a bit number control circuit so that working bit numbers of A/D converters and a counter in the loop are automatically reduced as the frequency of the input signals rise and, in accordance with such reduction in working bit number, a function generating ROM of a smaller bit number is selected from a group of function generating ROMs of different bit numbers for supply of address data to multipliers connected to the A/D converters, thereby the signal processing speed of the loop is significantly raised to face up to current speed-up in the mobile object displacement.

Abstract: A control circuit such as a microcomputer sets only the starting address of the memory in which initial information for generating a maximum length recurring sequence is stored and the number of chips of the maximum length recurring sequence and the initial information for generating a maximum length recurring sequence is set from the memory in the maximum length recurring sequence generator by a hardware. The hardware for accessing the memory is constructed by a counter working with a high speed clock. The number of chips of the maximum length recurring sequence set by the external control circuit is counted by a counter working with a high speed clock.

Abstract: Apparatus for categorizing and accumulating a plurality of different event types wherein the characteristics of each event are detected by a detector and presented to the apparatus as an electrical signal of variable analog or digital value which may indicate the type, speed, energy level or the like of an event. The apparatus includes a table look-up storage device having a plurality of individually addressable memory locations which receives the electrical or digital value and in response thereto outputs a bin address or clock select number which identifies a particular bin. Clock distribution logic circuitry receives the bin address from the look-up table storage device and in accordance with the bin address selects a particular bin and increments the event count being accumulated therein. Counter select logic circuitry is also provided for use by a host computer or the like to select a particular bin and output the event count being accumulated in the selected bin.

Abstract: In an automotive engine control microcomputer the frequency of interrupt programs initiated by a pulse from an engine speed tachogenerator is prevented from being excessive as a result of loose connections or other malfunctions or distrubances by blocking the access of tachogenerator pulses to the interrupt port of the microcomputer for a predetermined interval following a successful interrupt from that source. If another signal that would produce an interrupt from that source is received during that interval, a circumstance indicative of probable malfunction, the blocking of interrupts from that source is continued for another interval of the same length.

Abstract: Disclosed is a mobile incident logger for monitoring an on-board, automotive, computer and signal levels developed by analog and digital sensors, the logger employing a coverage monitor, which records which memory locations are accessed by the computer; a cycle tag counting unit, which counts bus cycles of the computer; a discriminator, which detects the occurrence of incidents the logger is to record; a trace memory unit, which stores bus states of the computer; a trace memory unit, which stores memory variables of the computer; a discriminator, which detects the occurrence of some of the incidents the logger is to record; and a trace memory unit, which stores the sensor signals.

Abstract: A read-only sequence control system comprises a control unit having counters for determining the cycle time of the system and timing for the performance of various operations an EPROM and a plurality of relays responsive to data outputs of the EPROM for controlling a machine. The system has a first sensor for detecting the entrance of a work part into the machine and a second sensor for detecting discharge of the entered work part. When the second sensor does not detect the work at an end of working cycle, the control unit operates to stop the machine.

Abstract: A circuit arrangement for adding, storing and reproducing electric counting pulses, is suggested, which preferably serves as an electronic kilometer counter of a motor vehicle with a distance transmitter (10). The circuit arrangement comprises an overwritable nonvolatile storage (16) which is divided into a series of storage registers (19) in which the counting pulses are stored by a one-unit shift code. When erroneous information occurs in any storage cell, the error of the indicated storage contents amounts to a maximum of .+-.1. This is achieved in that the control circuit (13), beginning with the first register (14), writes each new counting pulse into the next register (13, 12 . . . ) and, after reaching the last register (0), increases the contents of the first register and then the following respective registers by one unit with the next counting pulses. Such a circuit arrangement is to be used as a kilometer counter, operating time counter, quantity or piece counter, and the like.

Abstract: A vehicle odometer system for counting pulses representing translation and storing in nonvolatile form binary data representing the decimal values of the odometer data. The architecture of the circuit is structured to use the data in the more significant digit positions of the odometer count as pointers for the nonvolatile storage addresses used to store data for the less significant digit positions. This arrangement ensures that the endurance capabilities of the nonvolatile memory array are taken into account while apportioning degradation in relation to the significance of the odometer data to be stored. Furthermore, electronic manipulation of the odometer data is prevented by inclusion of a write only high odometer value flag which cannot be removed and is redundantly detected.

Abstract: A multi-marker, multi-destination timing signal generator including a count-setting memory for storing a plurality of pulse-count values in a numerical order and a pulse counter for counting the number of pulses from a master clock. An output selection memory stores, for each pulse count value, enabling signals for a plurality of output elements so that a marker signal generated when the pulse counter equals a pulse-counter value in memory may be selectively routed to one or more output elements. The addresses of the count-setting memory and the output selection memory are maintained by an address counter. When the value of the pulse counter equals a pulse-count value stored in the count-setting memory, the address counter counts to the next address value for locating successive values in the count-settiong memory and the output selection memory.

Abstract: A variable timing sequencer for producing sets of data which correspond to different current states of the sequencer, wherein the interval of each such set of data corresponds to said current state and user input, and said current state is determined by a previous state and input data. This separation of the time domain sequencing from the functional sequencing allows operation of functional components at lower frequencies than the timing components and the increase of effective memory density. The ability to affect both current state and interval by means of an input permits the sequencer to be used in a variety of conditions and applications with a minimum amount of reprogramming.

Abstract: In a counting circuit having non-volatile electrically erasable memory elements and a plurality of similar counters each representing one place of the count, respective memory elements of suitable capacity are associated with the counters. Low value counters can be connected cyclically to each other via their counting inputs and transfer outputs. Their association with the other places of a count is changed as a function of the count of the highest-value place. In this way, the result is obtained, without additional expense for memory, that the individual memory elements are erased equally frequently during the life of the counting circuit.

Abstract: Apparatus and method are disclosed for identifying and measuring random contact interruption events in a circuit interconnection device. A comparator circuit, adapted to be operated at high frequencies, identifies when an interrupt event has occurred. The comparator circuit, as a result of the interruption event, causes a high frequency counter circuit to count clock pulses. The count in the counter circuit is continuously applied to an RAM memory circuit, write-enabled at an addressed memory location. After the interruption event is terminated, the RAM memory circuit is no longer write enabled at the addressed location and the addressed location is changed (incremented) in preparation for the next event. The counter circuit is also reset to zero in preparation for the next interruption event. The number of counts from a clock unit having a known frequency provides the duration of the interruption event. With the use of a clock unit operated at 100 MHz, interrupt events from 10 nanoseconds to 9.

Abstract: Control of a microcomputer performing a wide variety of functions in a motor vehicle in which the sequences of input and output signals intersect in time, instead of being performed by an elaborate input/output unit, is performed in the microcomputer itself with the help of a timing signal generator operating at a sub-multiple of the microcomputer clock frequency and producing a sequence of timing signals, each of which serve as an interrupt signal to the microprocessor of the microcomputer to initiate an interrupt program for scanning inputs and preparing outputs. After this short interrupt program, the main program is resumed. In the interrupt program each of a number of registers, respectively serving separate inputs or outputs, are decremented or incremented, having been set at particular values at the beginning of each interrupt program. Some registers are set at two different values in alternation in succeeding interrupt intervals.

Abstract: Method and apparatus for monitoring the time rate of successive events the rate of occurrence of which can vary over a wide range by: detecting the successive events during a succession of consecutive time intervals of equal duration; producing successive counts each representing the number of events occurring during each interval in which at least one event occurs; producing successive counts each representing the number of intervals between the end of a respective interval in which at least one event occurred and the end of the immediately preceding interval in which at least one event occurred; and storing representations of the successive counts produced.

Abstract: A device for generating timing pulses for a rotary printing machine includes generators for generating synchronizing pulses and a pulse sequence corresponding to increments of angle of rotation of the machine. A pulse processing circuit includes address counters connected to the pulse generating means and being preset by an address presetting device. The output of the one address counter is connected to a PROM storing predetermined sequences of timing pulses. In order to provide for shifting of the stored timing pulse sequences in a negative direction, an inverting member is connected in the data bus between the rotary speed counter and the address presetting device of the one address counter. The inverting member can include either negators or storing means programmed with complementary values.

Abstract: A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.

Abstract: A pulse generator (2) provides output pulses which are phase-synchronized to pulses from an external trigger source (3) through the use of gated delay lines (13) used as clocks. Output mode versatility is achieved by storing desired pulse output waveforms in a random access memory device (26). Expanded output resolution is achieved via an arrangement of three independent counters (10, 20, 24). A fourth independent counter (40) is used for burst counting. A pair of converters (36, 38) are used to provide an output amplitude monitor/test capability.

Abstract: In the disclosed device, a counter digitally counts the used or unused length of a tape, a display using a liquid crystal or the like displays the count, and a switch optionally shifts the count up or down.

Abstract: A circuit for storing a multi-digit decimal numerical value of the distance traversed by a vehicle having a signal transmitter which gives off electric counting pulses, and particularly an electronic tachometer. The improvement consists of the numerical value being able to be stored by means for coding the numerical value in a one-step code for a non-volatile storage formed of floating-gate storage cells.

Abstract: The counter circuit is adapted to counting high frequency pulses and to being read while counting said pulses. It comprises a plurality of pulse counting stages of increasing numerical significance, and read means for reading the states of said stages. Said plurality of pulse counting stages comprises lower significance stages (10.sub.1 to 10.sub.4) connected as a synchronous counter (10) and higher significance stages (12.sub.1 to 12.sub.n) connected as a ripple counter (12). The synchronous counter is so connected that it counts the high frequency pulses (H) directly, and that any change of state required in any of its stages on counting a pulse occurs substantially simultaneously with the arrival of said pulse. The ripple counter is so connected that it counts count cycles of the synchronous counter, and that it takes a long time relative to the interval separating two successive high frequency pulses for a change of state to propagate, where necessary, from the least significant stage (12.sub.

Abstract: An electron dosimeter system which measures the length of time that an individual, or object, is exposed to discrete strength levels of a stimulating medium. The dosimeter device is comprised of a sensing device with associated electronics, a converter and a processing circuit. The sensing device/electronics produces an electrical output, representing the strength level of the stimulating medium, which is converted to electrical pulses. The output of the converter is comprised of electrical impulses whose frequency or repetition rate represents the strength of the stimulating medium. The output of the converter is then processed in a circuit having a plurality of storage devices, each of which represent a discrete strength level of the stimulating medium. The processor produces a plurality of timed interval pulses which are addressed to the particular storage device representing that strength level of the stimulating medium.

Abstract: A speed measurement system including a magnetic pickup positioned in proximate relation to a driven element of a gas turbine engine having a plurality of discontinuities therein. The pickup providing a pulse per every discontinuity and thus a multiplicity of pulses for every revolution of the driven element. Conditioning circuitry connected to the pickup for generating a strobe pulse signal for every discontinuity. Interval measuring circuitry receiving interval signals asynchronous to the strobe pulses of a predetermined period which are to form a measurement period which is exactly related to a count of the strobe pulses over a measurement period. Additionally included is circuitry used to lengthen the measurement period up to a maximum of N intervals for increasing the low frequency response of the system.

Abstract: There is disclosed a new and useful taximeter which allows simple changes in tariff display conditions in various operating modes without any change or modification in circuit construction. The taximeter using a memory device removable from the taximeter body and containing lamp enabling and disabling information is capable of optionally setting tariff display conditions in respective ones of operating modes without reconstructing the circuit arrangement of the taximeter body.

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver section and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. The frequency synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. A programmable divider coupled to a reference oscillator source is compared with the output of the synchronous counter in a digital and analog phase detector.

Abstract: A copying machine managing apparatus identifies information recorded on a plurality of using section magnetic cards and on an administrative department magnetic card. The plurality of using section magnetic cards are respectively assigned to using sections and bearing thereon respective using section codes. When one of the using section magnetic card is inserted in a slit of the copying machine managing apparatus, the using section code is identified and a copying machine associated therewith is made operable. The number copies produced by the particular using section is accumulated by a digital computer at each production of a copy and stored in an RAM. The accumulated number is at the same time indicated on an indicator window of the managing apparatus. When the administrative department magnetic card is inserted in the slit, the accumulated number of copies for each using section is successively read out from the RAM and indicated on the indicator window.

Abstract: A device for the use of and easily portable by an individual, consisting of a main memory, a microprocessor, a keyboard for the control of the microprocessor, etc., and at least one accounting memory and a display. Operation of the keyboard in a pre-determined fashion will cause the microprocessor to transfer one or more units of information from the main memory to at least one accounting memory. The point in time at which this transfer is made directly or indirectly (for example via internal delay circuits) may be determined by the individual. The number of information units to be transferred is determined by operating the keyboard in a certain, preferably combinatory fashion. Each information unit or group of units which is transferred from the main memory to the accounting memory by operating the keyboard in some other, certain, preferably combinatory fashion will either be given a certain address code or will be allocated to a specific accounting memory.

Abstract: A clock pulse control device for address allocation of a read-only memory in a small size sequence controller in which data stored in the read-only memory are read out sequentially to operate an output relay during a time interval in accordance with the stored data, and the relay controls a load. Clock pulses generated by a frequency-dividing clock pulse generator (30) are applied to presetable down counters (33) and (34) in which the clock pulses are divided down to pulses each having a time period corresponding to the preset value. The divided pulses are applied to a binary counter (29). The outputs of the binary counter (29) are delivered to the read-only memory provided outside from address lines (Q1)-(Q7) via a connector (10) to allocated addresses of the read-only memory sequentially. Predetermined data are stored in the read-only memory in advance and the data of the allocated addresses are delivered to operate the output relay.

Abstract: A digital rate monitor including a microprocessor operating under program control to receive and process event pulses to calculate the rate of the event pulses, and display the calculated rate. The rate is calculated by accumulating a batch of pulses and measuring the time it takes to accumulate such number of pulses. The batch size for a given calculation is a function of the event pulse rate, and a different batch size is automatically selected if the event pulse rate increases or decreases within a certain range. The rate is calculated once per second by averaging sixteen pulses for high speed inputs, four pulses for intermediate rates, and using a single pulse for low speed inputs.

Abstract: This anti-fraud system includes a process and devices for avoiding fraud on the price indicated by an electronic taximeter. The taximeter apparatus, which includes a luminous display unit and a computing unit, is supplied with d.c. voltage V by the vehicle battery. One particular fraud, made more difficult by this system, involves voluntary cut-off of the voltage supply to the meter. To execute this fraudulent maneuver the cabdriver firstly starts the meter, and records a price on the fare meter, with no passenger in the taxi. Secondly, before a customer is picked up, the operator cuts off the current supply to the meter, which extinguishes the fare display. Thus, as the customer enters the cab, it is not apparent that the meter has already been run-up to a non-zero value. To preclude this maneuver, the anti-fraud system has a first comparator which compares the voltage V with a reference voltage Vr and emits a constant voltage Vc if V<Vr and a zero voltage if V>Vr.