Pulse Multiplication Or Division Patents (Class 377/47)
  • Patent number: 10447294
    Abstract: In accordance with an embodiment, a circuit includes a first oscillator having an oscillation frequency dependent on an input signal at a first input, where the first oscillator is configured to oscillate when an enable input is in a first state and freeze its phase or reduce its frequency when the enable input is in a second state. The circuit also includes a first time-to-digital converter having an input coupled to an output of the first oscillator, and a pulse generator having an input coupled to a first clock input of the circuit and an output coupled to the enable input of the first oscillator, where the pulse generator is configured to produce a pulse having pulse width less than a period of a clock signal at the first clock input.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 15, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Cesare Buffa, Fernando Cardes Garcia, Luis Hernandez-Corporales, Andrés Quintero Alonso, Andreas Wiesbauer
  • Patent number: 10353587
    Abstract: A method of operating a data storage device includes fetching a first plurality of commands from at least one submission queue generated in a host memory, determining whether a ratio of a second plurality of commands from among the fetched first plurality of commands exceeds a reference ratio, and adjusting a number of a plurality of pointers being fetched at substantially a same time based on determining whether the ratio exceeds the reference ratio. The second plurality of commands has a same property, the plurality of pointers indicates a physical address of the host memory corresponding to the first plurality of commands, and the data storage device includes a storage controller configured to perform an interfacing operation with a host including the host memory.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taemin Jeong, Soonjae Won
  • Patent number: 10230381
    Abstract: A frequency divider circuit comprises a first divider chain including at least one first divider cell and a second divider chain coupled to the first divider chain to form an extendable divider chain. The second divider chain includes at least one second divider cell with a respective reset control. An effective length of the extendable divider chain may be altered, dynamically, via the respective reset control. Altering the effective length, dynamically, enables a division ratio of the frequency divider circuit to be changed, dynamically. The frequency divider circuit may be advantageously employed by applications that rely upon a dynamic division ratio, such as a fractional-N (frac-N) phase-locked loop (PLL).
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: March 12, 2019
    Assignee: Cavium, LLC
    Inventors: JingDong Deng, Omer O. Yildirim
  • Patent number: 9772344
    Abstract: An apparatus and a computer-implemented method for generating pulses synchronized to a rising edge of a tachometer signal from rotating machinery are disclosed. For example, in one embodiment, a pulse state machine may be configured to generate a plurality of pulses, and a period state machine may be configured to determine a period for each of the plurality of pulses.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 26, 2017
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: Lawrence Greer
  • Patent number: 9641182
    Abstract: A digital phase-and-frequency controller. In one embodiment, the controller includes: (1) a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first value and (2) a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second value, and (3) circuitry operable to produce the control signal using the errors accumulated in the first segment accumulator while a use-selection signal has a first value and the errors accumulated in the second segment accumulator while the use-selection signal has a second value.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: May 2, 2017
    Assignee: Nvidia Corporation
    Inventor: Kenneth Evans
  • Patent number: 9509406
    Abstract: An optical transmitter includes: a digital signal process unit that generates a drive signal for generating multi-carrier signals through a plurality of independent digital signal processes, the multi-carrier signals having a cyclic prefix and to be transmitted by a parallel transmission; a synchronization unit that synchronizes clocks of the plurality of digital signal processes; and an adjust unit that reduces a delay difference of the cyclic prefix between the multi-carrier signals after the parallel transmission.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Toshiki Tanaka, Tomoo Takahara, Masato Nishihara
  • Patent number: 9490826
    Abstract: Methods and apparatus for synchronizing dividers in different LO paths using pulse swallowing. One example apparatus generally includes a first path having a first frequency divider configured to generate a first divided signal from a first periodic signal; a second path having a second frequency divider configured to generate a second divided signal from a second periodic signal; a phase detector configured to compare phases of a first sensing signal based on the first divided signal and a second sensing signal based on the second divided signal and to generate a first trigger signal if the first and second sensing signals are out-of-phase; and a first pulse suppressor configured to suppress a pulse of the first periodic signal for at least one cycle in response to the first trigger signal to adjust a phase of the first divided signal.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: November 8, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Cheng-Han Wang, Keplin Victor Johansen, Jeongsik Yang, Justin Phelps Black
  • Patent number: 9490777
    Abstract: A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Inayat Ali, Puneet Dodeja, Sachin Jain
  • Patent number: 9270280
    Abstract: A fractional-N frequency divider includes a half-integer frequency divider and a duty cycle adjustment circuit. The half-integer frequency divider includes a multi-modulus divider containing a cascaded chain of div2/3 cells, which is responsive to a multi-bit modulus control signal, and a phase control circuit configured support half-integer frequency division by the multi-modulus divider, by providing an input terminal of the multi-modulus divider with a periodically phase-flipped input signal having a first frequency. The duty-cycle adjustment circuit is configured to generate a divider output signal with a 50% duty cycle in response to a periodic signal generated by the half-integer frequency divider.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 23, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Mihai A. Margarit, Mohamed AH. Mostafa
  • Patent number: 9257991
    Abstract: A programmable high-speed frequency divider architecture is provided that is programmable to divide an input clock signal frequency by a selectable division N. The frequency divider architecture has a shift register circuit having N/2 shift register stages, connected in series when N is an even integer and trunc[N/2]+1 shift register stages when N is an odd integer. The frequency divider architecture includes a feedback logic circuit that performs a logical NAND of the output clock signal with the logical ORed result of a pre-output signal provided from a shift register stage prior to the output stage and another signal that indicates whether the selectable divisor N is odd or even.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: February 9, 2016
    Assignee: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventor: Ferdinando Pace
  • Patent number: 9219487
    Abstract: An RF transceiver circuit is disclosed herein. In accordance with one example of the disclosure the RF transceiver circuit includes a phase-locked-loop (PLL) with a fractional-N multi-modulus divider. The PLL operates in accordance with a PLL clock frequency and generates a frequency modulated RF output signal. The RF transceiver circuit further includes a modulator unit, which is configured to generate a sequence of division values dependent on a set of modulation parameters. The modulator operates in accordance with a system clock frequency, which is lower than the PLL clock frequency. A sample rate conversion unit is coupled between the modulator unit and a fractional-N multi-modulus divider. The sample rate conversion unit is configured to interpolate the sequence of division ratios to provide an interpolated sequence of division ratios at a rate corresponding to the PLL clock frequency.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Rainer Stuhlberger, Klemens Kordik
  • Patent number: 9071176
    Abstract: There is provided an apparatus and a method for controlling a motor. The apparatus for controlling a motor includes a signal detection unit detecting a first signal, a sampling unit acquiring the number of pulses of the first signal included in a predetermined sampling period, and an operation unit dividing the sampling period into a predetermined number of, a plurality of sub periods, and computing a speed of a motor by allocating predetermined weights to the number of pulses of the first signal included in the plurality of respective sub periods, wherein the operation unit computes the speed of the motor by controlling at least one of the weights and the number of sub periods when the number of pulses of the first signal included in the plurality of respective sub periods is different.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: June 30, 2015
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Bon Young Gu
  • Patent number: 9054680
    Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: June 9, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Keun Kim, Sun Cheol Kwon, Si Young Kim, Jae Gon Lee, Jung Hun Heo
  • Patent number: 9048843
    Abstract: A frequency divider circuit includes an adder circuit, multiplexer circuits, and a phase interpolator circuit. The adder circuit generates a summed value. The multiplexer circuits receive first periodic signals and generate second periodic signals by selecting among the first periodic signals based on the summed value. The phase interpolator circuit generates a third periodic signal using a weighted average of the second periodic signals that is determined based on the summed value.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: June 2, 2015
    Assignee: Altera Corporation
    Inventor: Warren Trent Nordyke
  • Patent number: 9018988
    Abstract: One of the most important RF building blocks today is the frequency synthesizer, or more particularly the programmable frequency divider (divider). Such dividers preferably would support unlimited range with continuous division without incorrect divisions or loss of PLL lock. The inventors present multi-modulus dividers (MMDs) providing extended division range against the prior art and without incorrect divisions as the division ratio is switched back and forth across the boundary between two different ranges. Accordingly, the inventors present MMD frequency dividers without the drawbacks within the prior art.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: April 28, 2015
    Assignee: MEMS Vision LLC
    Inventors: Muhammad Swilam Abdel-Haleem, Rania Hassan Mekky
  • Patent number: 9013213
    Abstract: A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.
    Type: Grant
    Filed: October 1, 2011
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Kailash Chandrashekar, Stefano Pellerano
  • Patent number: 9008261
    Abstract: An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: April 14, 2015
    Assignee: Liming Xiu
    Inventor: Liming Xiu
  • Patent number: 8994417
    Abstract: A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: March 31, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Keng Leong Fong, John Wong, Jenwei Ko
  • Publication number: 20150043702
    Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.
    Type: Application
    Filed: September 23, 2014
    Publication date: February 12, 2015
    Inventors: Dae-Han KWON, Yong-Ju KIM, Jae-Il KIM, Taek-Sang SONG
  • Publication number: 20150030117
    Abstract: A shift frequency divider circuit includes: an inverter; N?1 registers; and N?2 logic gates; wherein each reset terminal of the register is connected to a system reset signal terminal; an output terminal of the inverter is respectively connected to an input terminal of the No. 1 register and input terminals of all the logic gates; all the logic gates are respectively connected between output terminals and input terminals of the No. 1 register to the No. N?1 register, and the output terminal of the No. 1 register is connected to another input terminal of the No. 1 logic gate, an output terminal of the No. 1 logic gate is connected to the input terminal of the No. 2 register; an output terminal of the No. N?2 logic gate is connected to the input terminal of the No. N?1 register.
    Type: Application
    Filed: October 15, 2014
    Publication date: January 29, 2015
    Inventor: Guo Zhang
  • Patent number: 8891725
    Abstract: A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N?1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: November 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Emmanouil Terrovitis
  • Patent number: 8890594
    Abstract: A system for synchronizing a functional reset between first and second clock domains that operate on first and second clock signals, respectively. The system includes first, second and third synchronizer flip-flops that operate on the second clock signal. The first synchronizer flip-flop receives a functional reset signal generated by the first clock domain at its reset terminal and generates a low output signal. The low output signal causes the second synchronizer flip-flop and subsequently the third synchronizer flip-flop to generate low output signals at positive edges of the second clock signal. The low output signal generated by the third synchronizer flip-flop is used to reset the second clock domain.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: November 18, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Surendra Kumar Tadi, Nitin Kumar Jaiswal
  • Patent number: 8884663
    Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 11, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven J. Kommrusch, Zihno Jusufovic
  • Patent number: 8867695
    Abstract: A prescalar counter may be configured to repeatedly increment once for each cycle of a clock signal at a first frequency and reset upon reaching a threshold counter value. The prescalar counter may also include toggling logic configured to generate a clock pulse of a global time base signal upon each reset of the prescalar counter. A frequency divider may be configured to divide the global time base signal into a plurality of separate clock signals with each of the separate clock signals having a different frequency. The frequency divider may also be configured to provide, to each of a plurality of timers, one of the separate clock signals.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: October 21, 2014
    Assignee: Apple Inc.
    Inventor: Gilbert Herbeck
  • Publication number: 20140306740
    Abstract: Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.
    Type: Application
    Filed: May 24, 2012
    Publication date: October 16, 2014
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventor: Matthew C. Guyton
  • Patent number: 8860511
    Abstract: A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Kenichi Okada, Ahmed Magdi Hassan Musa
  • Patent number: 8797078
    Abstract: The invention pertains to a latch circuit comprising a sensing arrangement with one or more sensing transistors adapted to sense an input signal and to provide a first signal based on the sensed input signal, and a sensing arrangement switch device connected or connectable to a first current source, the sensing arrangement switch device being adapted to switch on or off a current to the one or more sensing transistors based on a first clock signal.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: August 5, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Saverio Trotta
  • Publication number: 20140211906
    Abstract: A prescalar counter may be configured to repeatedly increment once for each cycle of a clock signal at a first frequency and reset upon reaching a threshold counter value. The prescalar counter may also include toggling logic configured to generate a clock pulse of a global time base signal upon each reset of the prescalar counter. A frequency divider may be configured to divide the global time base signal into a plurality of separate clock signals with each of the separate clock signals having a different frequency. The frequency divider may also be configured to provide, to each of a plurality of timers, one of the separate clock signals.
    Type: Application
    Filed: January 25, 2013
    Publication date: July 31, 2014
    Applicant: APPLE INC.
    Inventor: Gilbert Herbeck
  • Patent number: 8791729
    Abstract: A multi-phase frequency divider comprises first and second latches configured to receive a first input clock having a first frequency and a first phase, wherein the second latch receives the inverted first input clock. The first and second latches generate a plurality of output clocks each having a frequency that equals the first frequency divided by a predetermined divider ratio. The plurality of output clocks each have different phases staggered from the first phase. The frequency divider also comprises at least a first delay latch electrically connected between the first and second latches. The first delay latch is configured to generate, based on an output clock generated by the first latch and a second input clock at the first frequency and a second phase, two delayed output clocks. These two delayed output clocks have a frequency that equals the first frequency divided by the predetermined ratio with different staggered phases.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 29, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Joachim Heinz Dieter Woelk, Erwin Robert Schlag
  • Patent number: 8754719
    Abstract: A divider for use in an integrated circuit chip, such as a clock generator chip, includes a ramp generator circuit configured to generate a ramp signal and a synchronous detector circuit configured to receive the ramp signal and an input clock signal and to responsively control the ramp signal generator circuit to generate an output clock signal at an output of the synchronous detector circuit. In some embodiments, the synchronous detector circuit may include a voltage threshold detector circuit configured to receive the ramp signal and to generate a detection signal responsive thereto and a synchronous latch circuit having a clock input configured to receive the input clock signal and a data input configured to receive the detection signal. The synchronous latch circuit may be configured to control the ramp generator circuit.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: June 17, 2014
    Assignee: Integrated Device Technology Inc.
    Inventor: Justin O'Day
  • Patent number: 8742804
    Abstract: A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Fujita, Yukio Maehashi
  • Patent number: 8744037
    Abstract: A divider for providing an output signal having an output frequency by dividing a reference frequency of a reference signal by a divider value is disclosed. The divider includes at least a first divider element configured to provide a first divider output signal having a first divider output signal frequency which is half of the reference frequency and a last divider element configured to provide a last divider output signal having a last divider output signal frequency which half of the preceding divider output signal frequency. Furthermore, the divider comprises an output signal provider for providing the output signal.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: June 3, 2014
    Assignee: Intel Mobil Communications GmbH
    Inventor: Oliver Hauck
  • Patent number: 8736317
    Abstract: A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwan-Seok Yeo, Ji-Hyun Kim
  • Patent number: 8723579
    Abstract: The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 13, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Yasushi Imai
  • Patent number: 8704559
    Abstract: A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 22, 2014
    Assignee: Mediatek Singapore Pte. Ltd.
    Inventors: Keng Leong Fong, John Wong, Jenwei Ko
  • Patent number: 8693616
    Abstract: An IC that performs integer and fractional divisions is disclosed. The IC comprises a plurality of shift registers that forms a shift register ring. Consecutive shift registers are coupled to each other through a multiplexer. The IC also includes a multiplexer controller that determines the shift registers to be activated within the shift register ring. The multiplexer controller determines the activation based upon a divisional factor. The IC also includes a pattern controller that generates the control signal to program the shift register.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: April 8, 2014
    Assignee: Altera Corporation
    Inventors: Chuan Thim Khoŕ, Teng Chow Ooi
  • Patent number: 8675810
    Abstract: Disclosed is a method and apparatus for a modular high performance low power divider with 50/50 duty cycle output. The modularity offers custom dividers to be quickly developed while maintaining minimum power usage. A multi-modulus divider (MMD) receives an input signal and outputs an MMD output signal. The MMD includes a chain of modulus divider stages in such a way as to generate any divide value from 1 to 2(n+1)?1 (n is the number of cascaded elements) while maintaining a 50/50 duty cycle output. Power can be dramatically reduced as the frequency of each subsequent element is halved. The modular nature allows rapid development of any dividers simply by adding more elements to the chain.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: March 18, 2014
    Assignee: Intel Corporation
    Inventor: Alan J. Martin
  • Patent number: 8664933
    Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: March 4, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Masayoshi Todorokihara
  • Patent number: 8653862
    Abstract: A frequency divider includes a phase selection circuit, control circuit and a retiming circuit. The phase selection circuit is arranged to receive a plurality of input signals with different phases, and generate an output signal by selectively outputting one of the input signals according to a plurality of retimed signals. The control circuit is arranged to receive the output signal to generate a plurality of control signals. The retiming circuit is arranged to retime the control signals to generate the retimed signals according to the input signals.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 18, 2014
    Assignee: Mediatek Inc.
    Inventor: Ang-Sheng Lin
  • Patent number: 8644447
    Abstract: A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: February 4, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Chandra Bhushan Prakash, Balwinder Singh Soni
  • Publication number: 20140003570
    Abstract: A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N?1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.
    Type: Application
    Filed: April 29, 2013
    Publication date: January 2, 2014
    Applicant: QUALCOMM Incorporated
    Inventor: Emmanouil Terrovitis
  • Patent number: 8598932
    Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: December 3, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Ramakrishnan Venkatasubramanian, Anthony Lell, Raguram Damodaran
  • Patent number: 8599997
    Abstract: A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: December 3, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Yen-Tso Chen, Jian-Yu Ding
  • Patent number: 8575914
    Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: November 5, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Masayoshi Todorokihara
  • Patent number: 8565368
    Abstract: A multi-modulus divider includes a chain of n dual modulus divider cells in cascade and connected in a ripple configuration where the last (n-k) of the divider cells are state-parked dual modulus divider cells. The state-parked dual modulus divider cells are forced to a given logical state when the divider cell is bypassed. The state-parked dual modulus divider cells ensure that the multi-modulus divider can change between different number of cells without clock glitches or clock errors. The multi-modulus divider is therefore capable of achieving a wide division range with seamless transition between division ratios.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: October 22, 2013
    Assignee: Micrel, Inc.
    Inventors: Juinn-Yan Chen, San-Chieh Chou
  • Patent number: 8559587
    Abstract: Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multi-modulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: October 15, 2013
    Assignee: Integrated Device Technology, inc
    Inventors: Brian Buell, Benedykt Mika, Chen-Wei Huang
  • Patent number: 8552770
    Abstract: A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and additional circuit elements to correctly divide an input frequency by a divisor on successive output cycles while the divisor transitions across an octave boundary. The frequency divider creates a divide-by-1 mode for unused divide-by-1/2/3 cells in the series of cells. The divide-by-1 mode passes the input clock in the unused latches of each unused divide-by-1/2/3 cell as opposed to having each unused divide-by-1/2/3 cell implement divide-by-3 mode.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: October 8, 2013
    Assignee: Coherent Logix, Incorporated
    Inventor: Mark S. Cavin
  • Publication number: 20130251090
    Abstract: A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2?/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2?K/m phase offset from the previous clock output signal.
    Type: Application
    Filed: May 21, 2013
    Publication date: September 26, 2013
    Applicant: Texas Instruments Incorporated
    Inventor: Rajesh Velayuthan
  • Patent number: 8542040
    Abstract: An integrated circuit includes a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal and a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal. The integrated circuit further includes a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: September 24, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventor: Justin O'Day
  • Publication number: 20130216017
    Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 22, 2013
    Inventors: Dae-Han KWON, Yong-Ju Kim, JAE-IL Kim, Taek-Sang Song