Abstract: Methods for performing mixed-mode Multiply-Accumulate (MAC) functions in an integrated circuit (IC) are disclosed. By performing part of the MAC operation spatially and in parallel, and part of it temporally and serially, the number of MAC operations can be programmed in the serial/temporal MAC segment as a multiple of the parallel/spatial MAC segment. Such a trait provides a degree of flexibility in programming the mixed-mode MAC function. A Programmable-Hybrid-Accumulation (PHA) method, performs the accumulation function of the MAC IC, by transforming the accumulation signal to a hybrid accumulation signal. The hybrid accumulation signal is comprised of a Most-Significant-Portion (MSP) and a Least-Significant-Portion (LSP), wherein the portions of the hybrid accumulation signal can be programmed in accordance with cost-performance objectives of an end application.

Abstract: A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.

Abstract: A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.

Abstract: A method for measuring a period of time between a first event and a second event via a hardware counter 2 and of a software counter 3. A digital counter 1 using such a method is also described.

Abstract: Embodiments of the present invention include complementary metal-oxide-semiconductor (CMOS) readout architectures for photon-counting arrays with a photon-counting detector, a digital counter, and an overflow bit in each of the sensing elements in the array. Typically, the photon-counting detector is a Geiger-mode avalanche photodiode (APD) that emits brief pulses every time it detects a photon. The pulse increments the digital counters, which, in turn, sets the overflow bit once it reaches a given count. A rolling readout system operably coupled to each sensing element polls the overflow bit, and, if the overflow bit is high, initiates a data transfer from the overflow bit to a frame store. Compared to other photo-counting imagers, photon-counting imagers with counters and overflow bits operate with decreased transfer bandwidth, high dynamic range, and fine spatial resolution.

Abstract: Embodiments of the present invention include complementary metal-oxide-semiconductor (CMOS) readout architectures for photon-counting arrays with a photon-counting detector, a digital counter, and an overflow bit in each of the sensing elements in the array. Typically, the photon-counting detector is a Geiger-mode avalanche photodiode (APD) that emits brief pulses every time it detects a photon. The pulse increments the digital counters, which, in turn, sets the overflow bit once it reaches a given count. A rolling readout system operably coupled to each sensing element polls the overflow bit, and, if the overflow bit is high, initiates a data transfer from the overflow bit to a frame store. Compared to other photo-counting imagers, photon-counting imagers with counters and overflow bits operate with decreased transfer bandwidth, high dynamic range, and fine spatial resolution.

Abstract: A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.

Abstract: A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed.

Abstract: A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.

Abstract: A counter system and method and computer program product for managing counter systems. Counter systems management includes receiving a count event associated with a counter, updating a first stage counter value based on the count event, determining whether to eject the counter value based on a random function of the counter state, and ejecting the counter value. A counter system comprises a first stage update unit configured to accept a count event and to eject a counter. A second stage update unit may be configured to accept an ejected counter value, and includes a second counting module configured to accumulate the ejected counter value.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: Optimizing statistics counter use is disclosed. A total number of counter bits to be used to track two or more statistics is determined. The total number of counter bits is allocated among the two or more statistics to provide for each statistic a counter comprising the number of bits allocated for that statistic, the allocation being such that each counter overflows at a rate desired for that counter. The overflow rates may be balanced, such that each counter overflows at approximately the same rate.

Abstract: A circuit for controlling the random character of a bit flow, including an input shift register receiving the bit flow and having its outputs exploited in parallel, at least one element for comparing at least a partial content of the input register with predetermined patterns, a plurality of counters in a number at most equal to the number of predetermined patterns, and an element for detecting the exceeding of at least one threshold by one of the counters, the result of this detection conditioning the state of a word or bit indicative of the random or non-random character of the bit flow.

Abstract: A digital counter with a dial position having a hardware part which determines the n lowest-value bits of the dial position and a software part which determines the remaining higher-value bits of the dial position includes first and a second software parts as the software part with the dial position being a combination of the first software part and the hardware part when the hardware part is in a first counting range, and being a combination of the second software part and the hardware part when the hardware part is in a second counting range.

Abstract: Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described.

Abstract: A multi-bit counter of the present invention is capable of high-speed operation because the time needed for increasing count values and combining count bits for a carry can be minimized by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by a clock signal, i.e., by presetting the state of each of the bit combinations and outputting a next required value.

Abstract: A system and method are presented for providing a multi-stage counter. In one embodiment, a signal propagates from the most significant bit of the counter to the least significant bit of the counter that indicates that all “more significant” stages of the counter have reached a limit value (e.g., all 1's). Use of this propagating signal means that only the first (or first couple) stages of the counter are time critical, while the remainder are less so. The described counter may have a modular design and may result in lower power consumption.

Abstract: A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of said first counter stage and an output of said look-ahead circuit as an output of said counter. In the specific embodiment, the first counter stage is adapted to receive a first clock signal having a frequency of N cycles per second and output a second clock signal having a frequency of M cycles per second. The first counter stage includes an accumulator having a rollover point at which an instantaneous count thereof exceeds the value of N−M. The look-ahead circuit determines for a present clock cycle the rollover point for a preceding clock cycle. The look-ahead circuit is a second counter stage adapted to ascertain whether the rising edge or the trailing edge of the second clock signal is closer to the rollover point and output an indication with respect thereto.

Abstract: The present invention is an efficient system and method for flexible masking of output bits from a counter. The maskable counter system and method of the present invention modify the chain carry fed into a counter so that any bit (or bits) of the counter may be masked. A masked bit of a maskable counter system and method is utilized to facilitate user programmable control of multiple configurations in a memory. A maskable counter system comprises a mask register (e.g., a D flip flop), a counter (e.g., a D flip flop), and a masking coordination circuit. The masking coordination circuit permits a carry in signal, a carry out signal, and a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents the counter output bit signal from changing if the mask bit is asserted.

Abstract: A watchdog timer includes an instruction decoder, a delay circuit and a counter. The instruction decoder decodes a watchdog timer initialization instruction regularly executed to generate an instruction pulse for initializing the count of the counter. The delay circuit delays the rising edge of the instruction pulse, and supplies the delayed instruction pulse to the counter as a signal for initializing the count. The delay circuit prevents the pulse signal from being supplied to the counter when the operation frequency of the microcomputer is high or when the supply voltage to the microcomputer is low, so that the count of the counter overflows, and the overflow signal causes the microcomputer to be reset. This makes it possible to reset the microcomputer before it runs away, thereby solving a problem of a conventional watchdog timer in that the microcomputer can produce, if it runs away, an unexpected signal from its port before it is reset, and hence can impair the security of the system.

Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.

Abstract: An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first input, a test carry signal as a second input, and a control input, the switchable device being capable of providing one of its inputs as an output, the control input capable of controlling selection of the output which is a carry signal. The subcounter also includes an n/k-bit counter, the n/k-bit counter receiving the carry signal and providing n/k output bits, and logic for combining the n/k-bits output from the n/k bit counter with the carry-out signal from an adjacent subcounter to provide an output that is a carry-out signal from the subcounter. The logic introducing a single gate delay between the carry-out signal from the adjacent subcounter and the carry-out signal from the subcounter.

Abstract: A ripple counter becomes programmable by use of intervening circuitry selectively inhibiting state transitions according to an initial programming step. The illustrated embodiment of a programmable ripple counter includes a forward chain of count registers operating generally in the fashion of a ripple counter, but selectively inhibited by an intervening control signal originating from a reverse chain of control registers. By selectively controlling the number of state transitions inhibited and by selectively controlling the number of registers participating in the counting operation, a low power general purpose programmable ripple counter results.

Abstract: A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pre-divider circuit (208). Divider circuit (210) also generates serial data that is sent to an absolute value circuit (216) and then to a bit-serial filter (218). Bit-serial filter (218) generates an average signal from the serial data. A comparator circuit (224) compares the average signal to a threshold signal and generates the greater of the average signal or the threshold signal for use as a denominator in a next division cycle. The divider circuit includes an overflow control circuit (618) which detects overflow from the carryout bit of the partial remainder operation at the beginning of a division cycle and the sign bit of the numerator. If overflow is detected, the output is clipped according to whether the numerator is positive or negative.

Abstract: A very high speed counter system of operating at frequencies of up to around 800 MHz provides timing measurements with accuracies on the order of (1/f) seconds where f is the frequency of operation. The least significant bit of the counter operates at the given frequency of a first clock signal while the other higher order bits operate at a second clock signal where the second clock signal is one-half the frequency of the first clock signal and is inverted. Carry lookahead circuits connected between stages of the second counter operate in conjunction with the clocking scheme to produce a high speed and accurate counter.

Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.).

Abstract: A rate generator for use in a video server or other computer system requiring the generation of multiple timing signals from a single fixed frequency clock signal is disclosed. The rate generator stores a count value, a subtrahend value and a preload value for each timing signal that must be generated. The subtrahend value is subtracted from the count value. If this causes an underflow, an underflow signal, which comprises the generated timing signal, is asserted. The preload value is then added to the result of the subtraction, forming the new count value. If an underflow did not result from the subtraction, the result of the subtraction is the new count value. The frequency of the generated timing signal is determined by the ratio of the subtrahend and preload values. This permits the generation of many different timing signals from a single fixed frequency. The architecture required to perform these operations is relatively simple and inexpensive.

Abstract: A counter circuit having a load function which is able to speedily yet stably perform counting operations no matter what kind of value has been loaded. The counter circuit having a load function performs counting operations in synchronization with an input clock signal and is able to count from an arbitrary value upon receiving a count initiation value in synchronization with a load signal. The principal composing elements are: at least three counter circuits 1-1.about.

Abstract: Method and apparatus for performing read accesses from a counter (40) while avoiding the large rollover error that may occur when the counter (40) is read using more than one read access cycle. In one embodiment, the present invention monitors the most significant bit of the lower portion (44) of counter (40) for a transition indicating that a rollover has taken place. If a rollover has not occurred, read accesses take place in the normal manner. However, if a rollover has occurred during the latency period between a read access from the upper portion (42) of counter (40) and a corresponding read access from the lower portion (44) of counter (40), the read access from the lower portion (44) is inhibited and a default value is placed on the bus (36) instead.

Abstract: A reference signal generator that operates in response to a digital control signal has an increased resolving power without the requirement for increasing the basic clock rate or increasing the bit capacity of a down counter by thinning a pulse from the basic clock signal each the down counter overflows so as to adjust the down-counting clock rate of the down counter. The down counter counts the higher-bit data of the digital control signal. The basic clock signal is multiplied by a decoded signal to obtain the adjustment of the down counting clock signal. The decoded signal is obtained by counting the overflow pulses from the down counter and decoding the counter output with the lower-bit data of the digital control signal.

Abstract: A synchronous counter circuit comprises first and second counting circuits and a latch circuit. Each of the first and second counting circuits includes a clock terminal for receiving a clock signal, an enable terminal for receiving an enable signal, a counter coupled to the clock terminal for counting pulses of the clock signal, a carry signal generating circuit coupled to the counter for generating a carry signal in response to a finish of the counting of the counter, and a ripple carry signal generating circuit coupled to the clock terminal and the carry signal generating circuit for generating a ripple carry signal in response to the clock signal and the carry signal.

Abstract: A timer circuit is disclosed which includes a counter counting a clock signal, a register temporarily storing data, and a comparator comparing a count value of the counter with the data stored in the register and producing a signal when the count value of the counter reaches the value represented by the data stored in the register. Further provided in the timer circuit are detection circuit detecting the value of the data stored in the register and producing a detection signal when the register is written with data indicative of a value that is equal to an initial value of the counter and a circuit responding to the detection circuit to cause the register to change the value of the data stored therein to another value that is different from the initial value of the counter.

Abstract: An n-bit input count value is split into high-order n-1 bits and a low-order one bit so that the overflow signal 3a of the n-1 bit counter 2 for counting the high-order n-1 bits and the output signal 4a which is obtained by delaying the overflow signal 3a by half the cycle of the input clock by means of the delay circuit 4 are switched by the switch circuit 5 according to the low-order bit stored in the 1-bit register 6 to achieve a signal having a minimum decomposition width which is half the cycle of the input clock 7a.

Abstract: A digital pulse processing device is capable of selecting desired precision. The digital pulse processing device includes a counter group for counting pulses output from a pulse output device, the counter group having a plurality of counters A and B that can be separated from and coupled with each other, a mode control circuit for instructing separation and coupling of the counters A and B, and a control circuit for separating and coupling the counters A and B in accordance with the instruction of the mode control circuit. An overflow condition of the free-run counter B is detected using an overflow flag. Detection of an overflow is conducted by setting the flag when an overflow condition has occurred twice or more. The flag is reset by rewriting the state of the flag by a software. An overflow condition which has occurred for the first time is detected in the conventional manner and is treated as carry or borrow.

Abstract: A clock signal generator using fractional frequency division is provided comprising a division circuit that produces a clock signal starting from a timing rhythm signal. The frequencies of the two signals are in a division ratio which is the sum of a whole part and a fractional part. A pulse subtractor is provided for receiving the rhythm signal and transmitting it to the division circuit while deleting at least one pulse from this signal upon a command. An accumulator commands a pulse subtractor on each occasion when the product of the number of pulses of the clock signal counted, starting from a time of origin and of the fractional part, changes by unity.

Abstract: A circuit that may be implemented in a computer system that will measure the maximum and minimum time intervals for system elements to respond to a request for data or information. The circuit includes control logic that controls operation of the circuit, an up-counter and a down-counter that are used together for measuring the maximum or minimum response time interval, and a display for displaying the maximum or minimum response time interval that is measured during a test period.

Abstract: A high speed modular counter (100) utilizing a novel counting method in which the first bit changes with the frequency of the driving clock, and changes in the higher order bits are initiated one clock pulse after a "0" to "1" transition of the next lower order bit. This allows all carries to be known one clock period in advance of a bit change. The present counter is modular and utilizes two types of standard counter cells. A first counter cell determines the zero bit. The second counter cell determines any other higher order bit. Additional second counter cells are added to the counter to accommodate any count length without affecting speed.

Abstract: A pulse generator circuit includes an adder, a count register which holds the result of addition provided by the adder in order for the addition-result for recursive addition in the adder, a constant register holding a constant required for making said adder continue to perform count-up/count-down operation until a carry/borrow occurs, a parameter register for applying to said adder a correction value for changing, during a normal count-up/count-down operation, the time when carry/borrow occurs, a selector for selecting one of said constant and parameter registers for applying the value held in the selected register to said adder, and a shift register responsive to a carry/borrow occuring in the addition-result from said adder for shifting the content thereof.

Abstract: The present invention relates to a counter circuit for counting the rotated position of the motor and controlling absolute position of the same to control an absolute position of a robot system, which comprises, a RS-422 receiver for receiving encode signals from a motor driver, a 16-bit counter device for receiving rotated-number data of the motor supplied from the receiver and counting the data to output the counted value to a CPU via a bus line, a plurality of 4-bit counters for counting the signals when overflow or underflow is produced at the 16-bit counter portion, a first 8-bit latch circuit for receiving the counted values from the 4-bit counters and outputting the counted values to the CPU, and, a second 8-bit latch circuit for controlling the output state of the receiver on the basis of a control signal supplied through the bus line when a zero pulse control signal is inputted for searching an origin of the robot system thereby preventing erroneous counting operations due to a program and reducing t

Abstract: A reload timer circuit comprises an n-bit up/down counter circuit for receiving input data of n bits and providing up/down count data of n bits; an n-bit timer circuit for receiving the n-bit up/down count data and providing timer data of n bits; and a timer period setting means for generating a timer period signal in response to an overflow signal of the n-bit timer data and providing the n-bit up/down counter circuit with the timer period signal. This reload timer circuit automatically sets a reload value by hardware without relying on software, thereby reducing the load on a central processing unit.

Abstract: High speed synchronous counters are constrained to operate within certain speeds due to delays inherent in the counter configurations. By utilizing look-ahead carries, that is, producing carry signals in anticipation of when they might be required, much of the delay can be eliminated. Speed performance can be further improved by fashioning the look-ahead carry system from programmable gate arrays, where non-standard logic structures can be created.

Abstract: A frequency divider circuit, especially for use in frequency synthesizers, in which the frequency divider is provided with whole-number division factors, permits intergrator, differentiator and/or phase accumulations to be used to generate the successive values of the division factor which average, over time to allow fractional frequency division.

Abstract: An incrementer circuit includes a plurality of input terminals for receiving an address data, having a plurality of bits, to be incremented, a carry signal generating unit for generating a carry signal for each bit of the address data and a plurality of output terminals where an incremented address data appears. The carry signal generating unit includes a detector for detecting whether or not all of a predetermined number of less significant bits of the address data are at high level and outputs a detection signal if so. In response to this detection signal, a carry signal is generated and supplied to a bit which is more significant than the most significant bit of the predetermined number of less significant bits by one bit.

Abstract: A threshold detection logic circuit of simple and economical design is disclosed that indicates when the difference in the number of first operations to be counted and the number of second operations to be counted is either greater than or equal to a threshold value, or less than or equal to a threshold value. The threshold detection logic circuit employs the use of an overflow bit of a counter, which has a counting range of 2.sup.N+1 for a threshold range of 2.sup.N, in order to generate a threshold interrupt signal. In addition, the disclosed threshold detection logic circuit permits the threshold value to be programmed to any desired value.

Abstract: A device for the measurement of an event or occurrence, including a summing counter which is actuated from a divider circuit. The device includes a divider circuit constituted of a series circuit of counting steps, and wherein a transfer circuit for the counting pulses of the counting steps is arranged intermediate the summing counter and the divider circuit.

Abstract: Error rates above a given threshold are detected by initiating a counter to count a group of n bits on each occurrence of an error bit. The counters are inspected on each occurrence of an error to see whether the counter initiated x error bits earlier is still counting. If the counter is still counting the error rate is above a threshold of x error bits in a group of n bits in a serial stream.

Abstract: A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks and produces two outputs. A parallel terminal count output is produced each time the parallel section count reaches a programmed value. A frame output is generated every time the parallel section reaches its maximum count and starts counting again. The serial counter section decrements its programmed value by one each time it receives a frame signal from the parallel section. This subtraction is accomplished by a half-adder and associated borrow flip-flop. The borrow flip-flop is set by each arrival of the frame signal. Between frame signals, the decremented programmed value is circulated in a shift register as the serial subtraction process is performed.

Abstract: The present invention relates to a circuit for detecting an overflow when data is shifted by a shifter. The circuit of the present invention makes possible the detection of an overflow during 1 clock period. In addition, it compares the magnitude of the bit string signal, obtained by passing data through a priority order decomposing circuit with the magnitude of the signal obtained by passing the shift number through a decoder.

Abstract: A method and apparatus for testing operation of an n-bit counter with carry inputs in an electronic system. The n-bit counter is divided into a high section and a low section. An external carry is forced to the lowest significant bit of the high section. All states of both sections of the counter are clocked, each state of each of the sections being clocked simultaneously with a corresponding state of the other of the sections. The natural carry is selected so that, at the next clock cycle, when the low section is set at the highest count, the highest significant bit of the low section is carried to the lowest significant bit of the high section.