Abstract: A high-speed counter using radix-N Signed-Digit redundancy adders, an initial value generator and an interim value generator for each digit. The initial value is selected based upon a desired count. The transfer digit and interim value for each digit are generated to eliminate a carry propagation from a lower digit position. The high-speed counter reaches a desired count with a certain delay time regardless of the starting count value.

Abstract: An integrated circuit memory with additional circuitry added so that the integrated circuit acts as a counting memory is disclosed. A memory core is included with associated circuitry allowing it to be accessed in the same manner as ordinary random access memory (RAM). A counter is included and is coupled so that it can receive the contents of any location in the memory core. Each address in the memory acts as an individual counter. When a particular memory address is presented indicating that the count at that memory location should be incremented, the contents of that memory location are transferred to the counter, the counter is incremented, and the contents of the counter are then transferred back to the memory location. This process is repeated each time a new address is presented indicating a new event to be recorded. At the end of a series of events, the core memory will contain, at each corresponding memory location, the number of occurrences of the event assigned to that address.

Abstract: A Gray code counter employs modules of binary bits to form expressions or numbers. The count is sequenced from one expression to the next by changing only one binary bit in one location of an expression. The Gray code counter can be an incrementing counter or an increment/decrement counter. The counter can operate with expressions of several bits, and employs a minimal number of D type flip-flops and logic gates.

Abstract: A signal processor converts quadrature phase signals, from an encoder, representative of a measured parameter, into data which is directly readable by a computer and representative of the magnitude and direction of the current value of the parameter. The signal processor decodes binary signals representative of successive samples of the quadrature phase signals into UP signals, DOWN signals, ERROR signals and NO CHANGE signals. The UP and DOWN signals are converted into corresponding pulse streams which drive an up-down counter. Range control circuitry facilitates extension of the measuring range of the processor beyond that of the counter. Error control circuitry provides an ERROR INTERRUPT signal to the computer when an illegal condition occurs and also preserves the last valid data occurring before the illegal condition.

Abstract: There is disclosed herein an up/down counter with a programmable terminal count. The up/down counter has a two level input structure such that new terminal counts may be written into the up/down counter asynchronously without disturbing operations of the up/down counter. Although the invention is described in the bidirectional sense, certain of the features are also applicable to unidirectional counters.

Abstract: An incremental count display system having a display (14) for displaying odometer information and trip odometer information. The display includes a display overflow indicia (21) that will not be permanently activated unless the odometer itself has been factory preset to an initial starting point of other than zero. Otherwise, the overflow indicia (21) must be reset with each display cycle. The trip odometer provides for an accurate count of trip mileage, even during a trip that includes an odometer memory rollover cycle. In addition, the trip odometer display makes use of a masking technique to avoid automatically writing to non-volatile memory (12). Also, an error indicia can be displayed in response to early failure detection.

Abstract: A frequency synthesizer which has a constant resolution over an octave frequency range is disclosed. The frequency synthesizer has a presettable high speed counter, a low speed counter, an adjusting counter, and a count selector. The low speed counter provides a first output signal whose frequency is rapidly alternated between two closely-spaced frequencies so that the average frequency of the output signal is the desired frequency. The adjusting counter determines the period of time that each of the closely-spaced frequencies is present at the output. The count selector determines the frequency of each of the two closely-spaced frequencies. The frequency synthesizer also has a phase splitter and provides a second output signal which is also of the desired frequency but which is phase-shifted by ninety degrees from the first output signal.

Abstract: An engine control apparatus includes a microprocessor, a ROM for holding a program required for the operation of the microprocessor, and a RAM for holding data supplied from the microprocessor. Pulse signals representative of results of the arithmetic operations executed by the arithmetic unit on the basis of input signals available from various sensors as well as data stored in the memory in accordance with the program are supplied to actuators for controlling engine operations through an input/output circuit. The control apparatus further includes a counter for counting crank angle pulses produced in synchronism with rotation of the engine shaft, an interrupt request generating circuit for requiring an interrupt to the microprocessor when overflow occurs in the counter. In response to every interrupt request, the microprocessor causes the count value held in the RAM to be incremented by unity.

Abstract: A counter counts clock signals following a reference signal to provide an address for accessing a memory wherein marks are stored at respective addresses corresponding to desired timing signals with respect to the reference signal. The memory has plural channels, all of which are accessed by the same count value, to provide different timing signals on different channel outputs corresponding to the marks stored in respective portions of the memory. Different sets of timing signals can be stored in different memory blocks, and the memory block which is accessed by the count value can be selected. The memory can be divided into plural memories of smaller capacity, and low speed memories can be used. A timing signal with respect to a first reference signal can be provided after the occurrence of the subsequent reference signal.

Abstract: At the inception of a time interval whose duration is to be measured, pulses whose rate may be varied are applied to a first counter. A second counter controls the rate of the pulses applied to the first counter. An overflow sensing circuit is connected to the output of the first counter for, in response to each overflow signal at the output of the first counter, incrementing the second counter which then causes pulses having a new rate to be applied to the first counter and for, concurrently, presetting the counter to a new count. The new rate is equal to 1/N the old rate and the new count is equal to 1/N the count in the first control prior to the overflow. The elapsed time information in the circuit is therefore always valid.

Abstract: In order to improve the operable frequency of a programmable counter circuit which serves as an N-step counter by loading an initial value N, load terminals of flip-flops of respective stages forming the counter circuit are sequentially cascade-connected via buffers and a load signal is applied to each of the load terminals from a load signal generator circuit. The load signal generator circuit includes a detector circuit which detects a specified value which is provided a short time before the initial value loading of the counter circuit and generates a detected output signal. The detected output signal is shifted by a shift register included in the load signal generator circuit which operates on the same clock signal as that which drives the counter circuit, thereby generating the load signal at the moment of the initial value loading of the counter circuit.