Using Shift Register Patents (Class 377/54)
  • Patent number: 11073556
    Abstract: A circuit comprises a plurality of scan chains configured to perform scan shifting in two opposite directions and a register configured to store a first signal. The first signal determines whether the plurality of scan chains operate in a first mode or a second mode. The plurality of scan chains operating in the first mode is configured to perform, based on a second signal, either scan shifting in a first direction in the two opposite directions or scan capturing during a test; the plurality of scan chains operating in the second mode is configured to perform, based on the second signal, scan shifting in the first direction or a second direction in the two opposite directions.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: July 27, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Wu-Tung Cheng, Yu Huang
  • Patent number: 11011132
    Abstract: The present application provides a shift register unit, a shift register circuit, a driving method, and a display apparatus, and relates to the field of display technology. The method includes: in a reset phase in which a second node is at a first level, transmitting, by a control circuit, a second level signal to a first node and an output signal terminal under the control of a voltage at the second node; and in a normal operation phase, normally operating, by the shift register unit.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 18, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Zhen Wang, Jian Sun, Fei Huang, Xiaozhou Zhan, Yun Qiao, Han Zhang, Wenwen Qin, Lele Cong, Zhengkui Wang, Rui Liu, Pengjun Chen, Lidong Wang, Shuang Zhao
  • Patent number: 10902809
    Abstract: A scan driver circuit includes a pull-up unit and a bootstrap unit arranged on a base. The pull-up unit includes a pull-up thin-film transistor for supplying a scan drive signal. The bootstrap unit includes a bootstrap capacitor electrically connected with the pull-up thin-film transistor. The pull-up thin-film transistor includes a gate electrode, a first insulation layer, and a source electrode and a drain electrode stacked in sequence from the base. The bootstrap capacitor includes first and conductive electrodes. The first conductive electrode and the source electrode are arranged on the same layer and are electrically connected together. A second insulation layer is arranged between the second conductive electrode and the second electrode. The second conductive electrode is electrically connected, through a first via that extends through the second insulation layer and the first insulation layer, to the gate electrode. An array substrate and a display device are also provided.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: January 26, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Longqiang Shi, Shu Jhih Chen
  • Patent number: 10825413
    Abstract: A shift register circuit, a gate driving circuit and a method for driving the same, and a display apparatus are disclosed.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: November 3, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Can Yuan, Yongqian Li, Zhidong Yuan
  • Patent number: 10762828
    Abstract: The present disclose provides a display panel and a display device. The display panel includes a display area, a non-display area surrounding the display area, at least one notch, a cathode layer, a peripheral bus, and shift registers. A first non-display area and a second non-display area are oppositely disposed, and a third non-display area and a fourth non-display area are oppositely disposed. A cathode layer includes a cathode connection portion. A peripheral power bus is connected to the cathode connection portion in a cathode contact region. A first cathode contact region and first shift registers are located in a notched non-display area and are overlapped with each other. A second cathode contact region is located in the fourth non-display area. A width of the first cathode contact region in a first direction is less than a width of the second cathode contact region in a second direction.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: September 1, 2020
    Assignee: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yangzhao Ma, Yujiao Liang
  • Patent number: 10424242
    Abstract: A shift register unit and a drive method thereof, a gate drive circuit, and a display device are disclosed. The shift register unit includes a shift resister circuit which delays a phase of an input signal from an input terminal to output a first output signal from a first output terminal and an inverting circuit which generates an inverting signal having an inverted voltage with respect to the first output signal and output it from a second output terminal. The shift resister circuit includes a first input circuit configured to control a voltage of a first node, a second input circuit configured to control a voltage of a second node, a latch circuit configured to latch the voltage of the first node and that of the second node as being inverted, and a first output circuit configured to selectively output the second clock signal or a first voltage.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: September 24, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Bo Wang
  • Patent number: 10424266
    Abstract: Provided are a gate driving circuit and a display device using the same. The gate driving circuit includes a shift register including a plurality of stages. A stage of the stages includes a first transistor configured to charge a first node with a first voltage level of a high voltage terminal of the stage. The first voltage level is higher than a second voltage level of a low voltage terminal of the stage. The stage further includes a control circuit connected to the first transistor. The control circuit is connected to the high voltage terminal and to an output terminal of a previous stage of the shift register. The control circuit is configured to control the first transistor to increase a voltage of the first node to be higher than a third voltage level, which is less than the first voltage level by a threshold voltage of the first transistor.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: September 24, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Sung Wook Chang, Se Wan Lee
  • Patent number: 10235955
    Abstract: A stage circuit includes an output part configured to supply a carry signal to a first output terminal and a scan signal to a second output terminal, in response to a voltage of a first node, a voltage of a second node, and a first clock signal being supplied to a first input terminal, a controller configured to control the voltage of the second node in response to the first clock signal being supplied to the first input terminal, a pull-up part configured to control the voltage of the first node in response to a carry signal of a previous stage being supplied to a second input terminal, and a pull-down part configured to control the voltage of the first node in response to the voltage of the second node and the carry signal of a next stage being supplied to a third input terminal.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: March 19, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Hee Kim, Ji Hye Lee, Chong Chul Chai
  • Patent number: 9847062
    Abstract: The present invention provides a scanning driver and an organic light-emitting display using the same. The scanning driver comprises a plurality of cascaded structures receiving signals from a first timing clock line (CK1) and a second timing clock line (CK2) with opposite phases, the cascaded structures successively generating output signals (i.e., scanning signals), wherein each of the cascaded structures comprises: a first transistor, connected to a starting signal line or to a scanning output line of a previous cascaded structure; a second transistor, connected to the second timing clock line and to the scanning output line; a third transistor connected to a high-level power supply VGH; a fourth transistor, connected to a low-level power supply VGL and to an output terminal of the third transistor; a fifth transistor, connected to a high-level power supply VGH and to a scanning output line; and a first capacitor, connected between an output terminal of the first transistor and the scanning output line.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 19, 2017
    Assignees: KUNSHAN NEW FLAT PANEL DISPLAY TECHNOLOGY CENTER CO., LTD., KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventors: Siming Hu, Hui Zhu, Xiuqi Huang, Xiaoyu Gao
  • Patent number: 9734464
    Abstract: A computer implemented method, apparatus, and computer usable program product for creating a labor standard for a task. The process automatically detects event data derived from a continuous video stream, wherein the event data comprises metadata describing a sequence of motions for performing the task, and parses the event data to identify appropriate event data describing a discrete set of motions from the sequence of motions. The process then analyzes, using an analysis server, the discrete set of motions to form a labor standard, wherein the labor standard specifies an optimal manner of performing the discrete set of motions. Thereafter, the process generates a set of recommendations for performing the task efficiently according to the labor standard.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Robert Lee Angell, James R. Kraemer
  • Patent number: 9589520
    Abstract: The present invention provides a self-compensating gate driving circuit, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a first DC low voltage VSS1.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: March 7, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Chao Dai
  • Patent number: 9576620
    Abstract: A semiconductor apparatus including a register input selection block configured to serially receive input data and output the input data in parallel as first and second data sets, or receive register selection output signals and output the register selection output signals as the first and second data sets, in response to a shift control signal and a capture control signal; a first data register configured to receive and store the first data set and output stored data as first register output signals; a second data register configured to receive and store the first and second data sets and output stored data as second register output signals; a register output selection block configured to output ones of the first and second register output signals as the register selection output signals; and a data output selection block configured to serially output one of the first and second data sets as output data.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 21, 2017
    Assignee: SK HYNIX INC.
    Inventor: Ho Sung Cho
  • Patent number: 9558843
    Abstract: A shift register unit, a gate driving circuit, and a display device are disclosed. The shift register unit comprising: a pull-up module for pulling up level signal at present-stage signal output based on a signal at a pull-up control node and a first clock input; a control module connected to a first voltage terminal and a second voltage terminal for controlling the level at the pull-up control node based on a signal inputted to a first signal input and a second clock input; and a reset module for resetting the level signal outputted from the present-stage signal output based on a signal inputted to a second signal input. Signal lines and TFTs integrated in the shift register unit may be reduced, thereby saving space occupied by the circuit and reducing product cost.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: January 31, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Rui Ma, Ming Hu, Guolei Wang
  • Patent number: 9524686
    Abstract: The present disclosure provides a shift register unit, a gate electrode drive circuit and a display apparatus, which relates to a technical field of display. The shift register unit includes an input reset module, a pull up module, a control module and a pull down module. By inputting a high level into the second signal input end of the input reset module in the touch scan to maintain the level at the pull up control node, the electrical leak effects at the pull up control node may be avoided efficiently. In this way, the defects of insufficient charging rate of the row pixels may be avoided and the dark lines or bad bright lines may be suppressed.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 20, 2016
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yuanbo Zhang, Jiayang Zhao, Seung Woo Han, Xing Yao, Haifeng Jin
  • Patent number: 9489878
    Abstract: A shift register has an input stage circuit, a first switch, a control circuit and a pull down circuit. A first end of the first switch receives a first clock signal. A second end and a control end of the first switch are respectively coupled to an output end of the shift register and a first output end of the input stage circuit. The control circuit controls electrical connection between a first power terminal and a node according to a second clock signal and controls electrical connection between the node and a second power terminal according to a voltage level of a second output end of the input stage circuit. The pull down circuit controls electrical connection between the second output end and the second power terminal and electrical connection between the output end and the second power terminal according to a voltage level of the node.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: November 8, 2016
    Assignee: AU OPTRONICS CORP.
    Inventors: Cheng-Chiu Pai, Ming-Hung Chuang, Shu-Wen Tzeng, Wei-Chien Liao
  • Patent number: 9478310
    Abstract: Provided is a shift register unit, a gate driving circuit and method, and a display apparatus. The shift register unit comprises an input module, a pulling-up module, a first control module, a second control module, a first reset module and a pulling-down module. It can be avoided that a relative large drift occurs in a threshold voltage of a pulling-down TFT (T8) by controlling a voltage at the pulling-down control node (PD) of the shift register unit, thus effectively increasing reliability of the shift register unit in operation.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: October 25, 2016
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Seung Woo Han, Yuanbo Zhang
  • Patent number: 9299452
    Abstract: A shift register is provided. In the shift register, each of successively cascaded shift register units includes first and second switches and first and second capacitors. For the first switch, a control terminal is coupled to a first node, an input terminal receives a first clock signal, and an output terminal is coupled to an output node. The first capacitor is coupled between the first node and the output node. The second capacitor is coupled between the output node and a ground terminal. For the second switch, an input terminal receives a second clock signal, and an output terminal is coupled to the first node. A carry signal is generated at the first node. For the N-th shift register unit, a control terminal of the second switch receives the carry signal generated at the first node of the previous shift register unit.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: March 29, 2016
    Assignees: Innocom Technology (SHENZHEN) Co., Ltd., Innolux Corporation
    Inventor: Keitaro Yamashita
  • Patent number: 9190007
    Abstract: A circuit block of a driving circuit of a display device includes a first transistor that has a gate being connected to a first node having an active potential during an output period, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period, and controls electrical conduction between the first node and an inactive potential line, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line applied with a first period signal having an active potential at the time of termination of the output period.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: November 17, 2015
    Assignee: Japan Display Inc.
    Inventors: Motoharu Miyamoto, Takahiro Ochiai
  • Patent number: 9176522
    Abstract: A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: November 3, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Kumar Dey, Himanshu Mangal, Kulbhushan Misri, Amit Roy, Vijay Tayal, Chetan Verma
  • Patent number: 9054696
    Abstract: The present invention relates to a gate driving circuit, and a array substrate and a display using the same.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: June 9, 2015
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Ping-Sheng Kuo
  • Patent number: 9041453
    Abstract: Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Kouhei Toyotaka
  • Publication number: 20150085968
    Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.
    Type: Application
    Filed: November 25, 2014
    Publication date: March 26, 2015
    Inventor: Tadashi Yamamoto
  • Patent number: 8964059
    Abstract: A scanning circuit, comprising first signal lines, second signal lines, third signal lines, a drive unit configured to drive the first signal lines, first buffers configured to drive the second signal lines in accordance with signals of the first signal lines, second buffers configured to drive the third signal lines in accordance with the signals of the first signal lines, and a shift register having a first part to be driven by signals of the second signal lines and a second part to be driven by signals of the third signal lines, wherein the first to third signal lines include two signal lines arranged in parallel to each other and configured to transmit the in-phase signals.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: February 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideo Kobayashi, Masanori Ogura
  • Patent number: 8952944
    Abstract: A stage circuit and a scan driver using the same that is capable of concurrently (e.g., simultaneously) or progressively supplying a scan signal to a plurality of scan lines. The stage circuit includes a progressive driver and a concurrent driver.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: In-Ho Choi, Bo-Yong Chung
  • Publication number: 20140241487
    Abstract: To provide a semiconductor device having a high aperture ratio and including a capacitor with a high charge capacitance. To provide a semiconductor device with a narrow bezel. A transistor over a substrate; a first conductive film over a surface over which a gate electrode of the transistor is provided; a second conductive film over a surface over which a pair of electrodes of the transistor is provided; and a first light-transmitting conductive film electrically connected to the first conductive film and the second conductive film are included. The second conductive film overlaps the first conductive film with a gate insulating film of the transistor laid between the second conductive film and the first conductive film.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Hiroyuki MIYAKE, Kouhei TOYOTAKA
  • Publication number: 20140205056
    Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Tadashi Yamamoto
  • Publication number: 20140204011
    Abstract: A gate drive circuit, comprising: a plurality of shift register units each having a signal output end, wherein the signal output end of one of the plurality of shift register units except the last one is connected to the signal input end of the next one; L arithmetic units each having a plurality of input ends, wherein L is an integer equal to or larger than 2, and one of the plurality of input ends of each of the L arithmetic units is connected to the signal output end of a respective shift register unit; and a clock generation unit having a plurality of clock output ends for outputting different clock signals, wherein at least one of the plurality of clock output ends is connected to at least one of the other input ends of a respective arithmetic unit except the one input end connected to the signal output end of the shift register unit, so that the L arithmetic units output L different drive signals.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 24, 2014
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Like Hu, Xiaojing Qi
  • Publication number: 20140078335
    Abstract: A scanning circuit, comprising first signal lines, second signal lines, third signal lines, a drive unit configured to drive the first signal lines, first buffers configured to drive the second signal lines in accordance with signals of the first signal lines, second buffers configured to drive the third signal lines in accordance with the signals of the first signal lines, and a shift register having a first part to be driven by signals of the second signal lines and a second part to be driven by signals of the third signal lines, wherein the first to third signal lines include two signal lines arranged in parallel to each other and configured to transmit the in-phase signals.
    Type: Application
    Filed: August 1, 2013
    Publication date: March 20, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hideo Kobayashi, Masanori Ogura
  • Patent number: 8675812
    Abstract: A configuration of logic elements enables existing Serial-In-Parallel-Out (SIPO) shift registers to perform their own bit count, report the receipt of a valid transmission consisting of an expected number of bits and report the receipt of an invalid transmission consisting of greater than the expected number of bits. Logic elements additional to the foregoing enable SIPO shift registers to receive valid transmissions of varying expected numbers of bits. Special purpose integrated circuits (ICs) are disclosed which also contain the aforementioned configurations of logic elements. Newly designed SIPO shift registers which contain within them the foregoing configurations of logic elements are further disclosed. Potential messages of multiple acceptable message lengths are accommodated. Some embodiments are equipped with tri-state data outputs.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 18, 2014
    Inventor: Richard C. Warner
  • Publication number: 20140061442
    Abstract: According to one embodiment, a method includes generating a first clock signal and a second clock signal with non-overlapping clock phases. The method may further include latching, by a plurality of master latches of a shift register, a plurality of values at a plurality of inputs of the master latches in response to a particular type of logical transition of the first clock signal. The method also includes latching, by a plurality of slave latches of the shift register, a plurality of output values of the plurality of master latches at a plurality of inputs of the slave latches in response to a particular type of logical transition of the second clock signal.
    Type: Application
    Filed: February 21, 2012
    Publication date: March 6, 2014
    Applicant: Raytheon Company
    Inventor: Martin S. Denham
  • Publication number: 20140050294
    Abstract: The present disclosure relates to the field of a liquid crystal display, and discloses a gate line driving method, a shifting register, and a gate line driving apparatus, for improving the stability of the shifting register in operation. The gate line driving method comprises the steps of: decreasing the threshold voltage shifting of a thin film transistor in a shifting register corresponding to a gate line; applying a voltage to a gate of the thin film transistor in the shifting register to turn on the thin film transistor, so that the gate line corresponding to the shifting register is provided with a line scan signal to drive the row of the gate lines to be switched on or off. The shifting register includes a first TFT, a second TFT, a third TFT, a capacitor, a resetting module, and a feedback receiving module. The disclosure can be used for driving the gate lines.
    Type: Application
    Filed: October 26, 2012
    Publication date: February 20, 2014
    Applicant: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kun Cao, Ming Hu
  • Patent number: 8653871
    Abstract: A counter circuit includes two pairs of registers configured to swap contents based on a timer overflow or underflow condition. The counter circuit also includes a waveform generator that generates a composite pulse width modulated signal with a period and duty cycle specified by values stored in the registers. A demultiplexing circuit generates first and second signals from the composite signal.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 18, 2014
    Assignee: Atmel Corporation
    Inventor: Karl Jean-Paul Courtel
  • Publication number: 20140023173
    Abstract: An object is to suppress the stress applied to a transistor as well as suppressing generation of defective operation. In a pulse output circuit having a function of outputting a pulse signal and including a transistor that controls whether to set the pulse signal to high level, in a period during which the pulse signal output from the pulse output circuit is at low level, the potential of a gate of a transistor is not set to a constant value but intermittently set to a value higher than the potential VSS. Accordingly, the stress to the transistor can be suppressed.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 23, 2014
    Inventor: Hiroyuki MIYAKE
  • Patent number: 8520796
    Abstract: A signal transfer circuit may include first to nth switches that are respectively connected to bits of an n-bit digital signal output from a digital signal generating circuit and controlled by a transfer control circuit, a first memory circuit including first to nth memories that respectively hold bits of the n-bit digital signal input through the first to nth switches and are serially connected to each other, a second memory circuit including (n+1)th to mth memories that hold a digital signal and are serially connected to each other, an output signal of the nth memory of the first memory circuit being input to the (n+1)th memory of a first stage, and (n+1)th to mth switches that are connected to output signals of the (n+1)th to mth memories of the second memory circuit and controlled by a read control circuit.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: August 27, 2013
    Assignees: Olympus Corporation, Denso Corporation
    Inventor: Yusaku Koyama
  • Publication number: 20130121455
    Abstract: A signal transfer circuit may include first to nth switches that are respectively connected to bits of an n-bit digital signal output from a digital signal generating circuit and controlled by a transfer control circuit, a first memory circuit including first to nth memories that respectively hold bits of the n-bit digital signal input through the first to nth switches and are serially connected to each other, a second memory circuit including (n+1)th to mth memories that hold a digital signal and are serially connected to each other, an output signal of the nth memory of the first memory circuit being input to the (n+1)th memory of a first stage, and (n+1)th to mth switches that are connected to output signals of the (n+1)th to mth memories of the second memory circuit and controlled by a read control circuit.
    Type: Application
    Filed: December 27, 2012
    Publication date: May 16, 2013
    Applicants: DENSO CORPORATION, OLYMPUS CORPORATION
    Inventors: OLYMPUS CORPORATION, DENSO CORPORATION
  • Publication number: 20130107096
    Abstract: A scanning circuit includes a shift register configured by connecting a plurality of unit circuits, and a control unit which controls the shift register. In a certain mode, the control unit supplies, to a control terminal of a unit circuit of at least one of a plurality of groups each constituted by the unit circuit, a logic level which operates the unit circuit of the at least one group as a buffer, and supplies the clock signal to the control terminals of unit circuits of other groups, thereby operating each of the unit circuits of the other groups to transfer a pulse signal, and outputting pulse signals from the unit circuit of the at least one group and the unit circuit arranged at the input side of it in one time period.
    Type: Application
    Filed: October 9, 2012
    Publication date: May 2, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: CANON KABUSHIKI KAISHA
  • Publication number: 20130039455
    Abstract: A shift register stage includes a first transistor having a capacitor electrode (CAPm) that faces, in a film thickness direction, at least one of source and drain electrodes (Tr4s and Tr4d) of the first transistor in a side opposite to a gate electrode (Tr4g) of the first transistor. One of (i) the capacitor electrode (CAPm) and (ii) the one of the source and drain electrodes (Tr4s and Tr4d) which faces the capacitor electrode (CAPm), is electrically connected to a control electrode of an output transistor of the shift register stage.
    Type: Application
    Filed: January 21, 2011
    Publication date: February 14, 2013
    Inventors: Satoshi Horiuchi, Masahiro Yoshida, Takaharu Yamada, Isao Ogasawara, Shinya Tanaka, Tetsuo Kikuchi
  • Publication number: 20130003911
    Abstract: Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.
    Type: Application
    Filed: September 8, 2011
    Publication date: January 3, 2013
    Inventors: Kenneth I. Schultz, Brian Tyrrell, Michael W. Kelly, Curtis Colonero, Lawrence M. Candell, Daniel Mooney
  • Patent number: 8300621
    Abstract: The present invention relates to a method for timing acquisition and carrier frequency offset estimation of an OFDM communication system and an apparatus using the same. For this purpose the present invention provides a method for calculating at least one auto-correlation and calculating an observation value by performing a sliding sum on the at least one auto-correlation, and calculating a peak point of an absolute value of the observation as frame timing. In addition, the present invention provides a method for generating a third OFDM symbol that is generated by delaying a second OFDM symbol, calculating an observation value through the second and third OFDM symbols, and calculating a phase difference from a result of multiplication of the observation value and a conjugate complex value of the observation value such that a carrier frequency offset can be estimated.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: October 30, 2012
    Assignees: Samsung Electronics Co., Ltd, Electronics and Telecommunications Research Institute, KT Corporation, SK Telecom Co., Ltd, Hanaro Telecom, Inc.
    Inventors: Hyoung-Soo Lim, Dong-Seung Kwon
  • Patent number: 8144828
    Abstract: A counter module may include a first set of registers configured to store respective sets of first control data, a second set of registers configured to store respective sets of second control data, a first counter and a second counter. The first counter may be coupled to the first set of registers and may receive counter input signals and an internal control signal, and generate a first count output and a first terminal count output according to one of the respective sets of the first control data, the internal control signal, and the counter input signals. The second counter may be coupled to the first counter and to the second set of registers, and may receive the counter input signals, generate the internal control signal, and generate a second count output and a second terminal count output according to one of the respective sets of the second control data and the counter input signals.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: March 27, 2012
    Assignee: National Instruments Corporation
    Inventors: Rafael Castro Scorsi, Brian Keith Odom
  • Publication number: 20110199353
    Abstract: A shift register circuit and method includes: a plurality of shift registers configured to generate latch clock signals by sequentially shifting input signals according to first and second clock signals, the first and second clock signals including: periods longer than a shift register clock signal, and phases different from each other, wherein odd shift registers among the plurality of shift registers are configured to be driven by the first clock signal, and wherein even shift registers are configured to be driven by the second clock signal.
    Type: Application
    Filed: November 15, 2010
    Publication date: August 18, 2011
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Kyuyoung CHUNG
  • Patent number: 7889831
    Abstract: A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of ‘k’ bits. The controller only requires information regarding the value of the number ‘k’ and the pre-programmed stop code in order to control any number of bits in a shift chain.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: February 15, 2011
    Assignee: ProMOS Technologies Pte. Ltd.
    Inventor: Christopher M. Mnich
  • Publication number: 20110026664
    Abstract: A counter module may include a first set of registers configured to store respective sets of first control data, a second set of registers configured to store respective sets of second control data, a first counter and a second counter. The first counter may be coupled to the first set of registers and may receive counter input signals and an internal control signal, and generate a first count output and a first terminal count output according to one of the respective sets of the first control data, the internal control signal, and the counter input signals. The second counter may be coupled to the first counter and to the second set of registers, and may receive the counter input signals, generate the internal control signal, and generate a second count output and a second terminal count output according to one of the respective sets of the second control data and the counter input signals.
    Type: Application
    Filed: August 3, 2009
    Publication date: February 3, 2011
    Inventors: Rafael Castro Scorsi, Brian Keith Odom
  • Patent number: 7774674
    Abstract: The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: August 10, 2010
    Assignee: Stmicroelectronics N.V.
    Inventors: Norbert Wehn, Frank Kienle, Torben Brack
  • Patent number: 7747020
    Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventor: Wajdi K. Feghali
  • Publication number: 20100134234
    Abstract: A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 3, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Yi-Suei Liao, Chien-Liang Chen, Chen-Lun Chiu, Hao-Chieh Lee, Kuan-Yu Chen
  • Patent number: 7656382
    Abstract: A shift register having a plurality of stages in which each of the stages includes: an input circuit part arranged to receive an input signal; an exclusive OR circuit arranged to generate a toggle signal by an exclusive OR operation on a non-inversion output and an inversion output of the input circuit part; and an output circuit part arranged to supply one of a clock signal and a feedback signal from an output terminal to the output terminal and an input terminal of the next stage in response to the toggle signal.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: February 2, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Kyung Eon Lee, Juhn Suk Yoo
  • Publication number: 20090285352
    Abstract: A readout chip for single photon counting has a plurality of N individually working channels each assigned to a respective detector diode. Each channel has a counter designed as a binary counter having a length of M bits and a number of programmable bits. Further, the readout chip has a serial shift register or parallel data input register for entering values for the counter and the programmable bits, and a number of data output shift registers each having a number of K data outputs. Means are provided for selectively multiplexing each of the K data outputs onto a selectable bit of the data output shift register.
    Type: Application
    Filed: November 20, 2006
    Publication date: November 19, 2009
    Applicant: Paul Scherrer Institut
    Inventor: Bernd Schmitt
  • Patent number: 7583247
    Abstract: A gate driver for a display device includes a plurality of shift registers to sequentially generate output signals during a frame period in response to multi-phase clocks; and a dummy clock provided to the plurality of shift registers during a vertical blank time to reduce a stress voltage in the shift registers, wherein an output of each of the shift registers is reset to a low state power supply voltage by an output signal of the next shift register.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: September 1, 2009
    Assignee: LG Display Co., Ltd.
    Inventors: Kwang Soon Park, Soo Young Yoon, Min Doo Chun
  • Patent number: RE48737
    Abstract: The present invention provides a scanning driver and an organic light-emitting display using the same. The scanning driver comprises a plurality of cascaded structures receiving signals from a first timing clock line (CK1) and a second timing clock line (CK2) with opposite phases, the cascaded structures successively generating output signals (i.e., scanning signals), wherein each of the cascaded structures comprises: a first transistor, connected to a starting signal line or to a scanning output line of a previous cascaded structure; a second transistor, connected to the second timing clock line and to the scanning output line; a third transistor connected to a high-level power supply VGH; a fourth transistor, connected to a low-level power supply VGL and to an output terminal of the third transistor; a fifth transistor, connected to a high-level power supply VGH and to a scanning output line; and a first capacitor, connected between an output terminal of the first transistor and the scanning output line.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: September 14, 2021
    Assignees: KUNSHAN NEW FLAT PANEL DISPLAY TECHNOLOGY CENTER CO., LTD., KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventors: Siming Hu, Hui Zhu, Xiuqi Huang, Xiaoyu Gao