Abstract: As the incrementer of the invention comprises a shift register for its lower order bits, while its higher bit portions are constructed in the same way as a conventional incrementer, the incrementer can give output signals directly to a memory and the like without the necessity of decoding the same, and the incrementer is free from carry propagation delay possibilities, which assures an improved rate of operation of the incrementer as a whole.

Abstract: An interface control circuit includes a shift register which is parallel loaded with a 17 bit binary code and with control information comprising two bits of opposite level loaded in the head cells of the register, the first bit having a control function, the second having a separation function from the 17 bit binary code. The parallel loading is performed by a load command which also sets a control flip flop and wherein a timing circuit, triggered by command, controls in continuous mode the interlocked interface dialogue as long as the control flip flop is set, and causes the register to shift its contents so as to serially unload the binary code to the interface and to serially load the register with the logic level of the control bit, until, at the completion of transferring the control bit level present at a predetermined number of register outputs is inverted, reintroduced in the first register cell and causes the control flip flop to reset and the dialogue to halt.

Abstract: A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks and produces two outputs. A parallel terminal count output is produced each time the parallel section count reaches a programmed value. A frame output is generated every time the parallel section reaches its maximum count and starts counting again. The serial counter section decrements its programmed value by one each time it receives a frame signal from the parallel section. This subtraction is accomplished by a half-adder and associated borrow flip-flop. The borrow flip-flop is set by each arrival of the frame signal. Between frame signals, the decremented programmed value is circulated in a shift register as the serial subtraction process is performed.

Abstract: The invention relates to a charge-coupled device of the accordion type provided with a shift register for supplying accordion clock voltages on the one hand and with clock lines for supplying conventiional clock voltages on the other hand. The electrodes are alternatively coupled to the shift register and to the clock lines. The dissipation can be considerably reduced in this device. Moreover, the transport direction can be reversed in a simple manner, which is of importance, for example, in image sensors for smear suppression.

Abstract: Apparatus is disclosed for forming scan data path subchains from the elemental memory units of a digital system, and interconnecting the scan data path subchains to form an extended serial shift register for scan testing. The method and apparatus for forming the interconnections ensures that data is passed from one subchain to another without data being lost due to clocking irregularities.

Abstract: A logic integrated circuit of the scan path system comprises a combination circuit and a shift register associated to the combination circuit and including a plurality of cascaded flipflops. The shift register has a scan input, a clock input, a scan control input, and a scan output. A scan input terminal is connected to the scan input of the shift register, and a clock terminal is connected to the clock input of the shift register. A scan output terminal is connected to the scan output of the shift register. Further, there is provided a counter having an input connected to the clock terminal and an output connected to the scan control input of the shift register. This counter has a frequency division ratio equivalent to the stage number of the flipflops in the shift register, so that the shift register is switched between a shift register mode and a normal mode by the frequency division signal from the counter.

Abstract: An efficient area imager CCD readout scheme in which two electrodes in each column are used to store charge packets and a three electrode technique is used to implement the readout function. A static clock generator drives the CCD electrodes to provide the three electrode technique.

Abstract: A successive approximation register for an analog/digital converter operating according to the weighing method and having a bit width n includes a comparator and n memory elements each having one data input and one data output for shifting onward a logical "1" potential for each successive weighing step as well as for writing-in and storing in memory the particular result of weighing ascertained by the comparator. Multiplexers are associated with the n memory elements and have data input sides partially connected to the comparator. Logic elements are connected between the data outputs of the memory elements and the multiplexers for respectively controlling the data input sides of the multiplexers.

Abstract: A gated shift register includes a first set of 16 storage devices and a second set of 16 storage devices with interconnection circuitry for configuring the first set of 16 storage devices as a 16 bit shift register. The second set of storage devices is coupled between the outputs of the first set of storage devices and 16 output terminals of the gated shift register and transfers the outputs from the first storage devices to the output terminals when a transfer input terminal is at a first logic state, and isolates the first storage devices from the output terminals and retains the data at the output terminals when the transfer input signal switches to a second logic state. The gated shift register also includes power monitor and control circuitry for supplying standby battery voltage to the circuit when the primary power source becomes unavailable.

Abstract: An electronic counter such as for use in the odometer of a motor vehicle is provided comprising an array (10) of m rows and n columns of single flip-flop data latches and a central shifting unit (14). The central shifting unit (14) comprises a row of n data latches arranged to read data from and write data to each of the m rows of data latches of the array (10). In operation, the central shifting unit (14) reads data from a row of data latches of the array, performs a shift operation on the data and an invert operation on one of n data latches of the central shifting unit (14) and returns the data so operated on to the row of data latches in the array (10). By these steps, a counting operation in Johnson code is performed on the data. This invention uses less chip area than known counters.

Abstract: A semiconductor logic integrated circuit device comprising a signal selection means and a storing means, which is capable of adjusting the logic levels of an output signal therefrom. With such a circuit device, the signal selection means and the storing means are controlled in normal operation mode so that a parallel input signal is allowed to be output as a parallel output signal from output terminals of the circuit device after subjecting the parallel input signal to logical signal processing. On the other hand, the signal selection means and the storing means are controlled in a testing opertion mode so that the parallel input signal are output in serial mode from a serial signal output terminal of the circuit device, and a serial input signal to the signal selection means is allowed to be stored in the storing means to adjust the logic levels of the output signal from the circuit device at desired levels voluntarily.

Abstract: A first digital sound data of N-bits delivered from the input terminal is controlled by a mute control signal indicating either on-mute state signifying the state where mute operation is conducted or off-mute state signifying the state where no mute operation is conducted. This circuit includes a level control circuit, a register, a bit shift circuit, and a data selector. The level control circuit outputs a second digital sound data corresponding to the soundless state at the time of on-mute. It outputs data of which level gradually rises from the level of the soundless state to the level indicated by the first digital sound data at the beginning of off-mute and outputs the first digital duration at times subsequent thereto. Thus, for a duration at the beginning of off-mute, sound volume gradually rises. The register and the bit shift circuit gradually attenuate the first digital sound data to the level of the soundless state. Thus, for a duration at the beginning of on-mute, sound volume gradually lowers.

Abstract: Apparatus is disclosed for reversing the bit order of a portion of a digital word. The apparatus contains a shifter, connected to the input through a bit reversing means, and selector means which forms an output word by selecting appropriate bits either directly from the input word or from the output of the shifter.

Abstract: A counter circuit for counting pulses inputted thereto asynchronously during a fixed period includes a counter 12' for counting the input pulses, a register 13 for storing pulses outputted by the counter 12' at fixed periods, and a control circuit 11' for generating a signal that controls the operating state of the counter 12' and register 13. When a signal that decides the operating period of the counter 12' is not being generated, namely between pulses indicative of the operating period, the counter 12' performs an ordinary counting operation. If an input pulse for counting is applied to the counter 12' during a period of time in which the abovementioned pulse is being generated, the control circuit 11' causes the counting operation to continue without clearing the counted value in the counter 12', after which the counted value in counter 12' is outputted to the register 13 to be latched therein, thereby preventing miscounting in the register 13.

Abstract: In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A "0" propagates through the shift register at the DAC conversion rate.

Abstract: YA dual clock shift register for use in a computer display system for converting a higher resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus. The dual clock shift register includes a first shift register which is used to apportion a second shift register between control by two different clock rates.

Abstract: A programmable logic device includes an AND plane and an OR plane associated with the AND plane. At least one of the AND and OR planes includes an array of programmable memory elements which can be selectively programmed to define a desired logic function. In one form, a function cell designed for providing one of a predetermined functions, such as a counter or shift register function, selectively is provided. In another form, a driver circuit connected to a pair of input lines has a first state in which one of the paired input lines serves as an inverting input line and the other as a non-inverting input line and a second state in which both of the paired input lines are set at low level. In a further form, two pairs of input lines of the AND plane are connected to an input or input/output terminal of the device.

Abstract: A parallel-to-serial converter is described, comprising a shift register into which a data word can be loaded in parallel and then shifted out serially. As the data is shifted out, a string of zeros is shifted in. When a predetermined number of zeros is detected, a flip-flop is set at the next clock beat. This switches the shift register into its parallel load mode so that, at the next again clock beat the shift register is parallel loaded with the next data word. The detection of the predetermined number of zeros and the setting up of the shift register occur in different clock periods, allowing the clock period to be reduced, thus increasing the speed of operation.

Abstract: Basic block shift registers are cascaded to form a fully programmable linear feedback shift register. Each of the basic block shift registers comprises a plurality of flip-flops, each of which includes control logic circuits. A polynomial equation is first fed into the linear feedback shift register for setting the respective flip-flops into predetermined logic states, which are used to encode messages to be shifted by the programmable linear feedback shift register. The number of flip-flops in the programmable linear feedback shift register can be varied, in accordance to the polynomial equation. Likewise, the polynomial equation also determines the number of times the programmable linear feedback shift register is to circulate the encoded messages.

Abstract: An addressing device for a memory, such as a dynamic memory ROM or RAM, addressable by address words at a predetermined clock-period rate. Each address word is made up of first and second address words composed of least significant and most significant bits of the address word respectively. The first and second address words are multiplexed. The device comprises an adding circuit for incrementing the first address words in terms of a predetermined digital signal carrying words that are synchronous with the first address words and for incrementing the second address word in each address word by unity whenever the first word of the address word has bits all equal to "1", and a shift circuit looped across the adding circuit in order to deliver the first and second multiplexed address words to the memory.

Abstract: Apparatus, which first de-interleaves a signal, that comprises a plurality of interleaved pulse trains, into its constituent pulse trains and then identifies the emitter which transmitted each pulse train, is described herein. Specifically, this apparatus comprises a folded shift register which performs the de-interleaving. The folded shift register comprises a plurality of serially connected identical "active" cells, each of which detects a pulse occurring at a particular group pulse repetition interval (PRI) and, in an embodiment described herein, ascertains the inter-pulse PRI for each detected pulse for use in identifying an emitter. One or more processors analyze the group and inter-pulse PRI data, provided by the folded shift register, in order to identify each emitter.

Abstract: In a machine having automatic article transport individual identical articles are conveyed along a conveyor path (21) past various processing stations. A clock (12) is associated with the conveyor path. Furthermore, a characteristic detection apparatus (13) is provided which delivers information corresponding to the characteristics of the articles (16) which are moving past to a characteristic shift register (11), which is pulsed by the clock (1). An article sorting apparatus (14) is arranged spaced from the characteristic detection apparatus and is controlled by the associated storage (11') of the characteristic shift register. A further presence shift register (15) is arranged parallel to the characteristic shift register (11) and the information contained in the presence shift register (15) is compared with the output of a presence detection apparatus (17) and can be used to stop the machine in the event that a deviation is detected (FIG. 1).

Abstract: In a data processor system, a method for transferring data to and from a random access memory (RAM) with a serial data interface and having accessible word location includes the steps of generating a timing pulse consisting of contiguous time slots each defined by the Nth count of a counter, generating an initial address signal in the first occurring contiguous time slot of the timing pulse with the initial address signal including a read/write command signal, incrementing the initial address signal at each Nth count of the counter to form data address signal, accessing memory locations in the RAM with the initial address signal followed by said data address signals, supplying data words to or reading data words from the RAM at the word locations accessed by the data address signals in response to each Nth count of the counter and when the data address signal contains a write command or a read command signal, respectively.

Abstract: A successive approximation analog-to-digital converter, of the type which successively compares an analog level represented by binary weighted bits with an analog signal and in response thereto generates a signal indicating whether each successive binary bit should be set or reset, includes a shaft register for counting cycles during the sampling phase and generating signals for controlling the setting and resetting of each bit. Each binary bit cell includes a latch capable of assuming first and second stable states. A first string of field-effect-transistors coupled to the latch and controlled by the shift register receives a first signal indicating that the latch should be reset. A second string of field-effect-transistors coupled to the latch and controlled by the shift register receives a signal indicating that the latch should remain in a set condition.

Abstract: A multi-purpose register formed of various cells of a customized integrated circuit gate array chip having input gate cells, multiplexor cells, flip-flop cells and output gate cells. The flip-flop cells may be segmented into registers of different widths or may be employed as individual flip-flop cells depending upon the mode in which the register array is to be employed.

Abstract: The use of a comparator and counter associated, on-chip, with each photo-element of an array. Sensing each photo-element without discharging it and allowing each photo-element to accumulate a charge which is large relative to noise variations. These features result in a photo-detector with large signal-to-noise ratios.

Abstract: In a CCD, especially in an image sensor device, the information density can be doubled by sequentially switching the electrodes between a clock signal and a reference signal. Clock signals and reference signals are obtained as output signals of a shift register controlled by a monophase or multiphase clock. The register is provided, for example, using C-MOS technology. Information at the input terminal of the first stage of the shift register in combination with clock pulse signals at the register clock, determine the output signals of the next stage of the shift register. Hence, these input signals determine the voltage variations at the electrodes connected to the outputs of the register stages.

Abstract: A noise elimination circuit for eliminating noise signals from data given by a binary form includes a modulo in up/down counter having a first input for receiving binary data, a second input for receiving clock pulses and output for producing a counted signal. The counter is effected to count up in response to the clock pulses when the binary data is a HIGH, and to count down in response to said clock pulses when the binary data is a LOW. A decoder is provided which has inputs for receiving the counted signal, a first output for producing an indication signal when the counted signal corresponds to a first predetermined number i, and a second output for producing an indication signal when the counted signal corresponds to a second predetermined number j, in which i is equal to or greater than zero, j is greater than i and n is equal to or greater than j.

Abstract: A pulse counting device wherein a number of pulses is stored in a first register out of a plurality of registers, and subsequently a new pulse number counted is stored in the first register and pulse numbers stored in the registers are successively shifted with a pulse number erased from a final register. The pulse numbers stored in the respective registers are corrected dependent on the latest pulse number stored in the first register, and a value dependent on the corrected values stored in all of the registers is displayed. If the latest pulse number is abruptly varied in excess of a certain preset value upon comparison with the pulse numbers in the registers, then the pulse numbers in the registers are corrected with a value dependent on the latest pulse number.

Abstract: A register circuit for serial transmission or reception of digital data in a microprocessor controlled system is provided. A first plurality of rank ordered latches is provided to receive in parallel data to be transmitted. A second plurality of rank ordered latches is provided wherein each of the second plurality of latches except the highest ranked latch interconnects the first plurality of latches. The first and second plurality of latches function together to serially clock output data to be transmitted. The two pluralities of latches form a single register circuit which also serially receives data and latches the received data in response to a control circuit implemented as a "walking one" register. After the serially received data is latched, the data is provided for use by the microprocessor controlled system in parallel output form.

Abstract: A random number generator (RNG) uses an edge-triggered D-type flip-flop with a high frequency square wave having an approximately 50 percent duty cycle connected to a data input terminal and a low frequency square wave connected to a clock input terminal, a five-state counter, five two-input AND gates, five exclusive-OR gates, and five shift registers. An essentially truly random number is generated at the RNG output terminals. Probability biases due to both variations in the 50 percent duty cycle of the data waveform and small amounts of cycle-to-cycle jitter of the clock waveform are effectively removed.

Abstract: A variable frequency divider which includes a feedback shift register having a feedback gate of NOR type, a delay shift register for delaying output data from the feedback shift register by one clock, a control shift register having a control gate of AND type, a feedback circuit for feeding output data from the delay shift register and from the control shift register back to the feedback gate, and an expander which receives output data from the feedback shift register and produces a control signal according to said frequency dividing input and a frequency division ratio instruction signal. The control gate receives output data from the delay shift register and the control signal.

Abstract: A digital circuit requiring minimum power for accurately and reliably measuring the average pulse rate of a periodic signal. The circuit includes a plurality of flip-flop stages adapted to be configured by control gates either as a binary counter or a shift register in response to the pulses of the periodic input signal. Through a series of configuration gates, each pulse momentarily configures the circuit as a shift register and effects a shift operation, e.g. a divide-by-two operation. After each pulse, the circuit resumes a counter configuration and counts the clock pulses of a crystal controlled clock oscillator. After a few input pulses, the contents of the counter immediately after each shift operation indicates the average periodic rate of the periodic signal in much the same manner as a conventional R-C network. However, the digital circuit is not suseptable to drift caused by temperature changes and also moderates the effects of momentary irregularities in the periodic rate of the signal.

Abstract: When the frequency dividing ratio of a programmable divider in a phase locked loop is controlled by an up/down counter, the designing of a system can be simplified by reducing the number of control lines connected to a microprocessor as much as possible. An up/down counter control circuit of the present invention comprises a timing control means to which a latch signal, a data and a clock signal are supplied, a data memory means and an up/down counter and is characterized in that under the control of the timing control means, in the data latch mode, a first level (0 or 1) of the latch signal is detected and in synchronism with the clock signal that data is latched in the data memory means, while in the up/down mode, a second level (1 or 0) of the latch signal is detected and the content of the up/down counter is changed in response to the level of the data synchronized with the clock signal.

Abstract: A logic circuit is formed on a gate array chip together with a custom-circuit. Bonding pads mounted on the gate array chip are used as the terminals which send forth or receive data and control signals. The logic circuit is provided with a shift register for holding data to test the flip-flops of the custom-circuit and output data from the flip-flops. The shift register comprises the stages each of which holds 1-bit data selected by a read control signal. The output terminals of the stages are respectively connected to the input terminals of the flip-flops of the custom-circuit through the AND gates which are rendered conducting in response to a set control signal. The output terminals of the flip-flops are connected to the input terminals of the respective stages of the shift register.

Abstract: Serial to parallel conversion circuitry achieves phase synchronization and signal bit sampling of received asynchronous serial data through use of a gate enable delay line oscillator having a selected response time, and selectably enabled in the presence of the received serial data to provide a sampling clock signal for shifting the serial data into register for parallel formatting at a frequency equal to the line frequency.

Abstract: Apparatus is disclosed wherein the average period of a synthesized signal is a non-integral multiple of the period of a given signal. The apparatus is arranged so that a counter alternates its count between N and N+1, wherein N is a predetermined integer, in a predetermined pattern so that the average count approximates a rational non-integral value between N and N+1.

Abstract: The timer generates a selected number of control pulses per hour, at unpredictable (pseudo-random) intervals, for use with a time lapse video tape recorder used for time studies. The hour is divided into equal intervals to provide the number of samples required per hour, and one trigger pulse is generated randomly timed within each interval. A noise generator drives a counter whose outputs are loaded every Nth clock pulse into an N-stage shift register. The contents of the shift register are shifted out serially at the clock frequency.

Abstract: The clock signal to a fine delay shift register is divided by the number of fine delay bits for application to a coarse delay shift register such that two serially connected shift registers can provide a range of delays equivalent to a shift register having a number of bits equal to the product of the bits of the two shift registers.

Abstract: Cascaded programmable logic arrays are used to program any type of flip-flop. The latch itself can be embedded in the array when using cascaded PLA's. The arrays can be cascaded to provide logic functions using less total area than a single array embodying the same function.

Abstract: A logic system which includes a plurality of identical logic circuit building blocks, each referred to as an M Circuit, is disclosed. The M Circuits are connected in a linear array of interconnected M Circuits including first through last M Circuits, the linear array providing a latch operation. The system comprises a plurality of M Circuits each of which responds to transitions of a two-level binary input signal to provide a memory and a logic function which has a complete truth table for every possible combination of input signal transitions or changes in logic level at a pair of input terminals A and B. Each of the M Circuits comprises a gate having two inputs connected to the A and B input terminals, resepectively, and a set-reset flip flop having its set input connected to the output of the gate, the reset input connected to the B input terminal and the set and reset outputs connected, respectively, to the output terminals Q and Q of the M Circuit.

Abstract: This disclosure relates to a programmable logic array having an AND array disposed for receiving n input signals, an OR array providing k output signals on k output lines and m term lines coupling the AND and OR arrays together. New and improved AND and OR arrays are disclosed wherein the AND array includes n X m cells and each cell has first and second transistor means coupled in series between one of the term lines and a reference potential. Each cell includes a storage element that has an output terminal coupled to the control element of the first transistor means and one of the n input terminals is coupled to the control element of the second transistor means. The OR array includes m X k cells wherein each cell has third and fourth transistor means coupled in series between one of said output lines and a reference potential.

Abstract: The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. The odd bits, or nonsymmetrical bits across the various data formats are processed by a separate shifter. In this manner, no pre or post processing of the data word is required in the overall shifting operation.

Abstract: A pulse detection circuit, is used for detecting pulses contained in output signals derived from an encoder. An encoder, such as rotary encoder, converts a physical quantity like spatial position, displacement or length into an electric signal. This detection circuit achieves high definition in terms of the rotational angle of the encoder shaft. It does so by positively utilizing four different combinations of modes, obtained for one period of the encoder output signals, which had hitherto been treated in one count. It thereby avoids erroneous counting of the pulses contained in the encoder output signals, even if chatterings are incidentally included in the encoder output signals and if the phase relation between the two signals is temporarily inverted. The circuit thus performs pulse detection with a very high accuracy.

Abstract: The control system for periodically synchronizing in a sequential order the operation of a plurality of control elements of a printing machine comprises a control shift register having an input coupled to a fine timing device for generating synchronizing pulses corresponding to predetermined angular positions of the machine and another input connected to a sheet feeding control device. The outputs of a predetermined number of first stages in the control shift register are connected to a gating nonoperative time compensator, the control inputs of which are connected to the rotary speed detector and the output of which is connected to an assigned operation control element in the machine. A transfer shift register is connected in series with the control shift register or with the output of the dead time compensator.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Abstract: A data control circuit (18) for an input/output arrangement is arranged for controlling the transfer of a data word through a shift register (20 or 120) to or from a peripheral device (22 or 122). The circuit (18) provides for selection between internal clock generation at one of several rates or application of an external clock and for selection of the length and format of the data words to be transferred. Selection is accomplished by an interval counter (38), format data stored in a control register (37), two gating circuits (30 and 40) and a selection circuit (35).

Abstract: 1. Apparatus for producing multiple combinations of parallel output binary signals for controlling an anti-jam or other form of telegraphy system comprising four parallel feedback shift registers, a pair of serial to parallel converters, each having an input terminal, means for combining the output signals of said shift registers for producing two separate serial signals, means for coupling one of said serial signals to the input terminal of one of said converters, means for coupling the other of said serial signals to said input terminal of the other of said converters and means for changing the output signal of one of said converters when said separate signals are identical for a predetermined number of binary digits, said feedback shift registers having pluralities of separate stages and a feedback mixer having input terminals connected to the last and certain other three of said stages, and an output terminal connected to the first of said stages.

Abstract: A rotary-type switch simulator includes a shift register and a counter, both clocked by a momentary contact switch. The shift register outputs drive visual indicators indicating the selected switch position, while the counter provides a binary output corresponding to the indicated switch position. Logic circuitry, responsive to selected data bits at the outputs of the shift register and counter, reset the shift register and counter respectively to their initial states after the highest switch position has been accessed.

Abstract: In utilizing frequency dividers at high frequencies the maximum operating frequency is determined by the delay time through the frequency divider. To minimize this delay time, a digital frequency divider is provided having a binary counter constructed of flip-flops and a shift register coupled to the output of said counter, wherein the output state of the shift register is forcibly reduced to a low level in response to a control signal for varying the number of frequency division of said counter. A circuit is also provided for feeding the input terminal of the flip-flop at the first stage of said counter with an OR output made up of the outputs of said shift register and said counter. Thus, the digital frequency divider can operate at a speed which is limited only by the toggle frequency of said flip-flop circuits.