Abstract: A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.

Abstract: The invention concerns a charge-to-voltage converter including a read diode and a read transistor of no-load gain G.sub.o. The converter includes complementary circuits assuring a conversion gain greater than G.sub.o during read periods and a conversion gain substantially equal zero at other times.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: The charge coupled device charge detection node includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type in the substrate; virtual gate regions of the first conductivity type formed in the second semiconductor layer, the virtual gate regions forming virtual phase potential areas; an insulating layer on the second semiconductor layer; a floating gate formed on the insulating layer, the floating gate is located above a portion of the second semiconductor layer that is between virtual gate regions, the floating gate forming a floating gate potential well in response to a voltage; a first transfer gate formed on the insulating layer and separated from the floating gate by a virtual gate region, the first transfer gate forming a transfer potential area in response to a voltage; and an electrode coupled to one of the virtual gate regions on the opposite side of the floating gate from the first transfer gate, the electrode increases the potential o

Abstract: A charge-coupled device type image sensor having a floating diffusion-type amplifier including a drive transistor comprising a substrate, a drain region, a source region, a depletion channel region formed between the drain and source regions in contact with the drain region, and a gate electrode formed on the substrate between the source region and the drain region, such that the gate electrode overlays a portion of the source region and overlays a portion of the depletion channel region, wherein the drain region is spaced apart from said gate electrode.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Abstract: A charge detection device for converting a signal charge consisting of carriers of a first polarity externally provided into a voltage signals, the charge detection device comprising a MOS transistor, the MOS transistor including: a first semiconductor layer having a transistor channel for carriers of a second polarity; an insulating layer provided on the first semiconductor layer; and a gate electrode provided on the insulating layer, wherein transistor characteristics of the MOS transistor are changed by the signal charge accumulated in a surface region the first semiconductor layer immediately below in interface between the first semiconductor layer and the insulating layer, thereby detecting a quantity of the signal charge.

Abstract: In a charge transfer device incorporating a charge-coupled device, a junction type field-effect transistor, and a reset transistor, the junction type field-effect transistor includes a source region in contact with a junction gate region and a drain region in contact with the junction gate region. The charge-coupled device has an output gate electrode on a first insulation film formed on a surface of a transfer channel region which is formed in contact with the junction gate region. The reset transistor has a reset gate electrode adjacent to the junction gate region with a second insulation film interposed between the junction gate region and the reset gate electrode. A first distance between the source region and each of the output gate electrode and the reset gate electrode is longer than a second distance between the source region and the drain region.

Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition. In this circuit, the state of the output gets switched over in the first phase if the voltage at the terminals of the capacitor at the start of this stage (this voltage being equal to a fraction of the input voltage) crosses a determined threshold. This threshold is determined as a function of technical parameters for the construction of the circuit. These technical parameters are chiefly the threshold voltage of the transistor and the characteristics of the transistors that form the locking circuit.

Abstract: An image sensor element having at least one charge storage well 70 and 80, charge transfer structures for transferring charge from one charge storage well 70 to another charge storage well 80, and a charge sensor for sensing charge levels in a charge storage well 70 without removing the charge from the well.Other devices, systems and methods are also disclosed.

Abstract: The present invention is directed to a charge transfer apparatus. A reset gate (RG) is formed of an N-channel MOSFET of depletion type in which a carrier concentration of a channel region is set in a range from 10.sup.15 to 5.times.10.sup.16 cm.sup.-3. Also, a circuit for generating a reset pulse that is supplied to the reset gate (RG) is constructed as follows. A drain voltage source (12) and a drain of a transistor (Tr) are connected via a junction (a), and two resistors (R1) and (R2) are connected in series between the anode of the drain voltage source (12) and the ground. A junction (b) between the resistors (R1) and (R2) and the reset gate (RG) are connected together via an input line (13) and a high resistance (Rh) is inserted into the input line (13). Further, a coupling capacitor (Cc) is connected between a clock pulse input terminal (.phi.in) and the input line (13).

Abstract: An output circuit device for detecting and converting signal charge transferred thereto from a charge transfer section of a CCD into a signal voltage his constructed such that a gate oxide film of a driving side MOS transistor of a first stage source follower which receives signal charge is formed as a thinner film than gate oxide films of the other MOS transistors in the same circuit to reduce the 1/f noise.

Abstract: A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.

Abstract: A device and method for controlling the gain of a charge based signal is described. The described device and method may be used for both offset correction and for gain control. First and second charge holding gates are provided for receiving a charge packet representing a signal. A control gate partitions off at least a portion of the charge on the secondary charge holding gate. The charge not so partitioned off is then transferred onto the output line as the adjusted charge packet representing the adjusted signal, where the gain is now the ratio of areas of first charge holding gate to the sum of areas of both first and second charge holding gates. The offset of a signal can also be corrected by segregating the portion of charge representing the offset of an input signal onto the second charge holding gate.

Abstract: A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR operation, the best matching in case a perfect one does not exist. The chip disclosed herein has a fully parallel architecture in which an input word is compared to all stored words at one time. A preferred embodiment of the invention uses a four phase CCD, wherein each stored word occupies one row of the CCD and each such bit of each such word occupies two cells. Where perfect matches exist, only one comparison clock cycle is needed to compare the input word with all stored words and where there is no perfect match, the best match will be detected on a subsequent comparison pulse. Charge packets represent binary words generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines.

Abstract: A CCD delay line comprises of first, second and third transfer regions which are formed in a semiconductor substrate. Output portions of the second and third transfer regions are connected to a differential amplifier. The output terminal of the differential amplifier is connected to input sources of the first and second transfer regions. The third transfer region is able to carry at most 30% of maximum amount of charge which the first and second transfer regions can carry. A signal is supplied from a signal source through a clamp circuit to an input gate electrode of the first transfer region. Bias changing means independently change one of an input bias voltage supplied to the input gate electrode of the first transfer region and a reference bias voltage supplied to an input gate electrode of the second transfer region.

Abstract: A solid-state imaging device includes a semiconductor substrate in which an element part including a plurality of light responsive elements for generating charge carriers in response to incident light and a transfer part for transferring the charge carriers generated in each light responsive element are incorporated; a lens layer is disposed on the element part so that incident light is collected in the light responsive elements; and a light beam dispersion layer is disposed between the lens layer and the element part and includes two light transmissive layers having different refractive indices for dispersing light collected by the lens layer so that collected light entering respective light responsive elements is closer to a parallel beam than the incident light. By suppressing broadening of incident light in the semiconductor substrate at the light responsive elements, fewer charge carriers enter the CCD channel region and smear is reduced.

Abstract: A thinned backside illuminated charge-coupled imaging device has improved quantum efficiency by providing a sharp ion implant distribution profile (20) disposed at the rear surface (22) of the device. The sharp ion implant distribution profile (20) is formed using ion implantation at a beam energy potential of between 100-150 keV, which forms an electric field beneath the surface of the device. The ion distribution profile (20) is brought to the surface (22) of the device by removing silicon (18) from the rear surface (22), using a polishing technique wherein the device is lapped with colloidal silica abrasive to controllably remove silicon down to the level of the ion implantation profile (20).

Abstract: A charge detecting device in which a buried type charge sensing channel and a surface type floating surface channel crossing with the charge sensing channel in three-dimensional, the floating surface channel having a surface potential varying depending on a charge amount of the charge sensing channel, the device being characterized by a surface channel region disposed on the charge sensing channel, surface channel the region having a conductivity opposite to that of the charge sensing channel. A surface-invertible buried channel isolation region is disposed between the charge sensing channel and each of a source and a drain both formed on either side of the floating surface channel. Carriers of the floating surface channel and the charge sensing channel correspond to electrons of the same polarity. With this structure, there is no problem of dark current. Also, a short noise caused by dark noise is reduced, thereby enabling a high sensitivity to be obtained.

Abstract: A charge coupled device according to the present invention, having an output terminal, for detecting an electric charge and for outputting a detection signal corresponding to the electric charge from the output terminal, comprises a semiconductor substrate having a main surface, further having a first, second and third regions in the main surface, both the first and second regions defining the third region therebetween, a charge supply formed in the vicinity of the first region, for supplying the electric charge to the first region, a first impurity formed in the first region, for transferring the electric charge to the third region, a floating gate electrode overlying the third region, coupled to the output terminal, for detecting the electric charge and outputting the detection signal corresponding to the electric charge from the output terminal in a first condition, for transferring the electric charge to the second region in a second condition, a transfer electrode overlying the second region, applied a c

Abstract: Generally, and in one form of the invention, a method for multiplying charge in a CCD cell is disclosed comprising the step of causing impact ionization of charge carriers in the CCD cell.Other devices, systems and methods are also disclosed.

Abstract: A charge transfer device has a transfer section for transferring a signal charge along a transfer channel, and a pickup section connected to the transfer section for converting the signal charge received from the transfer section to a voltage signal, both sections being formed on a substrate. The transfer channel is bent generally at a right angle between the transfer section and the pickup section.

Abstract: A charge transfer device includes a first input stage converting a first input signal into first signal charge, a first shift register transferring the first signal charge with a first delay amount, a second input stage converting a second input signal into second signal charge and having a first switch for selectively inputting the second signal charge to a second shift register, a third input stage converting a third input signal into third signal charge and having a second switch for selectively inputting the third signal charge to a third shift register, and an adding section for selectively adding one of the second and third signal charge to the first signal charge. The second shift register transfers the second signal charge with a second delay amount and the third shift register transfers the third signal charge with a third delay amount.

Abstract: A charge transfer device in which a charge transfer section, an output gate, a floating diffused region, a reset gate electrode, a reset drain region, a barrier gate electrode and an absorption drain region are provided in semiconductor substrate. The reset drain region for resetting or draining charges in the floating diffused region is connected via a capacitor to a constant potential terminal. The absorption drain region is provided with a voltage booster for raising the amplitude of the transfer pulse to a level higher than the power source voltage. The output voltage of the voltage booster is supplied to the absorption drain region. The channel potential beneath the barrier gate electrode is set lower than that beneath the reset gate electrode.

Abstract: The invention provides a signal processing device including sampling means (31, 41, 32) for sampling an input signal in the form of charge carrier packages and a shift register (4) having an input region (41) to which a signal sample is offered during operation, and provided with transport means (2) for transporting the signal sample to an output region (42) of the shift register. The device according to the invention is capable of adapting itself to the frequency with which the input signal is sampled in such a way that the storage of the increase in signal samples which accompanies an increase in the sampling frequency does not require additional space. For this purpose, according to the invention, the shift register comprises a transport channel (4) in which an electron-hole liquid can exist. The sampling means (31, 41, 32) are capable of sampling the input signal in the form of electron-hole droplets (71 . . .

Abstract: In an output circuit for a charge transfer device, a floating diffusion region is connected to a source side gate electrode of a double-gate read-out field effect transistor having its drain side gate electrode connected to the drain of the read-out transistor itself. Thus, the capacitance between the gate of the read-out transistor connected to the floating diffusion region and the drain of the read-out transistor can be made small, so that the total capacitance of the floating diffusion region is correspondingly reduced, with the result that a high detection sensitivity can be realized.

Abstract: In a solid state image sensor, such as a CCD image sensor having lateral antiblooming protection, the level of which is controlled by an overflow gate voltage forming a barrier, the storage of electrons in the photodiode junction region of the sensor is eliminated by removing the barrier and allowing the charge to flow from the sensor's photodiode junctions into the overflow region. The charge flow is then detected as a function of the instantaneous light impinging on the photodiodes. The physical connections of the overflow gates are selected to form zones. Since the charge flow now represent the instantaneous light intensity, higher frequency components are detected than that limited by the sensor sampling rate. An amplifier is connected to sense the charge flow from each zone. With the range of light intensity being large the amplifier is provided with a logarithmic feed back element. This element provides compression of a signal representing the sensed charge flow.

Abstract: A solid imaging device that minimizes the degradation in charge transfer efficiency attributable to narrow channel effect by enlarging the apparent width of the horizontal output gate outlet. Miniaturization of the floating diffusion (FD) region is not hampered despite the apparent widening of the horizontal output gate outlet. The inventive imaging device utilizes a floating diffusion amplifier as the charge detector that detects a charge signal transferred from a horizontal CCD. In this device structure, ions are implanted into the substrate surface side of the region adjacent to the FD region in the horizontal output gate in such a manner that the channel potential of the adjacent region will become appropriately deeper than that of the forward-half region next to the adjacent region.

Abstract: A charge coupled device transfers a charge packet to a floating diffusion region for producing voltage variation therein, and the voltage variation is relayed to an output terminal by means of a driving unit implemented by a plurality of source follower circuits coupled in cascade, wherein each of the second to final source follower circuits is implemented by a series combination of an enhancement type driving transistor and an enhancement type load transistor, and the enhancement type load transistor changes the channel conductance thereof complementary to the enhancement type driving transistor under the control of a control unit so as to improve the dynamic range of the output signal thereof without sacrifice of the sensitivity of the floating diffusion region.

Abstract: A solid state image sensing device comprising first and second horizontal shift registers of two-phase drive system, a smear drain region disposed in an opposing relation to a first storage section of the second horizontal shift register to which the first phase drive pulse of the second horizontal shift register is applied and a channel stop region disposed in an opposing relation to a second storage section of the second horizontal shift register to which the second phase drive pulse is applied, wherein a smear component is drained to the smear drain region, and a hole component is drained to the channel stop region for thereby reducing a dark current of the second horizontal shift register to about that of the first horizontal shift register. Therefore, a dark current in the horizontal shift register of the solid state image sensing device can be reduced.

Abstract: Herein disclosed is an amplification circuit for realizing a substantially high sensitivity with a simple structure. The amplification circuit comprises: a first capacitor C1 for receiving a signal charge; a source-follower circuit for receiving a voltage of the first capacitor C1; an inversion amplification circuit including a source-earth type amplification MOSFET Q5 having its gate fed with the output signal of the source-follower circuit through a second capacitor C2; a feedback third capacitor C3 connected between the gate and drain of the amplification MOSFET Q5; and a switch element Q6 for feeding the gate of the amplification MOSFET Q5 with a predetermined bias voltage while the signal charge of the first capacitor C1 is being reset. The amplification MOSFET Q5 has its drain equipped as load means with a depletion type MOSFET Q4 having its gate and source connected, and the depletion type MOSFET Q4 has its source given the same potential as the substrate potential thereof.

Abstract: A floating diffusion type signal charge detection circuit for use in a charge transfer device includes a charge transfer region formed in a semiconductor layer, a plurality of transfer electrodes formed on the charge transfer region through an insulating layer, a floating diffusion formed in the semiconductor layer adjacent to a final stage of the charge transfer region, a reset drain formed in the semiconductor layer separate from the floating diffusion and connected to a reset drain voltage, and a reset gate formed through an insulating layer on a portion of the semiconductor layer between the floating diffusion and the reset drain. The floating diffusion, the reset drain and the reset gate forms a reset transistor. An amplifier is connected at its input to the floating diffusion so as to detect a voltage change appearing in the floating diffusion.

Abstract: The present invention is directed to an output circuit for a charge transfer device which can reduce a coupling voltage of a floating diffusion type charge detecting section and in which a DC fluctuation of an output from a source-follower stage can be suppressed. A dummy floating diffusion region (FD2) is provided and an output thereof is converted by and derived from a bias generator circuit (7) of a source-follower configuration as a positive phase output. This positive phase output is supplied to a load MOS transistor (Q.sub.2) of a source-follower circuit (5) as a bias voltage and also fed back to the load MOS transistor (Q.sub.6) of the bias generator circuit (7) as a gate voltage.

Abstract: An exploiting or readout circuit for a linear or matrix type photodetector array is of the multiplex type, such as a charge-coupled device (CCD). The exploiting circuit has a number of input stages corresponding to the number of photodetectors or similar photosites, and the gains of the input stages are established as a function of the fields of view of their associated photodetectors. In one embodiment the input stages each comprise a storage device formed of a first and a second storage electrode separated by a dividing electrode, the storage electrodes having respective surface areas selected in a relation that varies as a function of solid angle field of view of the respective photodetector. In another embodiment the input stage can include an OpAmp with a negative feedback capacitor whose value is selected as a function of the viewing solid angle of the respective photodetector.

Abstract: There is disclosed a solid-state image sensor comprising: photo-detecting devices arranged in a matrix structure for receiving external light signals; vertical charge transfer device interposed between the columns of said photo-detecting device for vertically transferring the charges produced from said photo-detecting device according to external control signal; first horizontal charge transfer device for horizontally transferring the charges coming out of said vertical charge transfer device according to external control signal; output control device for controlling the charges flowing from said first horizontal charge transfer device to said output device; second horizontal charge transfer device for transferring the output charges of said first horizontal charge transfer device controlled by said output control device to said vertical charge transfer device according to external control signal; and a feedback line for connecting the output of said first horizontal charge transfer device to the input of sai

Abstract: A CCD amplifier circuit including an active load type source-grounded inverting amplifier circuit which includes a driving MOS transistor, an active load MOS transistor connected to the driving MOS transistor, and a control circuit. The control circuit controls the voltage at the gate electrode of the active load MOS transistor with a control signal of low output impedance which is substantially inversely proportional to the drain-source voltage of the active load MOS transistor and level-shifted by a predetermined voltage. Further, a CCD delay line includes a floating diffusion region of predetermined impurities formed at an end of a charge-coupled device with a gate section having a predetermined fixed gate voltage, and a switched capacitor integrator for detecting the injection charge of the floating diffusion region to detect signal charges transferred to the floating diffusion region from the charge-coupled device.

Abstract: Special purpose CCD designed for ultra low-noise imaging and spectroscopy applications that require subelectron read noise floors, wherein a non-destructive output circuit operating near its 1/f noise regime is clocked in a special manner to read a single pixel multiple times. Off-chip electronics average the multiple values, reducing the random noise by the square-root of the number of samples taken. Noise floors below 0.5 electrons rms are possible in this manner. In a preferred embodiment of the invention, a three-phase CCD horizontal register is used to bring a pixel charge packet to an input gate adjacent a floating gate amplifier. The charge is then repeatedly clocked back and forth between the input gate and the floating gate. Each time the charge is injected into the potential well of the floating gate, it is sensed non-destructively.

Abstract: A charge detection circuit includes a p-type semiconductor substrate, a reference voltage source for generating a reference voltage having a predetermined voltage difference with respect to the potential of the semiconductor substrate, a first n.sup.+ -type semiconductor region formed in the semiconductor substrate, for storing a carrier packet, a second n.sup.

Abstract: An image sensing device that outputs a signal logarithmically proportional to the intensity of the incident light. The image sensing device makes use of a sub-threshold current flowing between the drain and source of a MOS transistor when the gate voltage is below the threshold voltage (above which the MOS transistor is nominally conductive and below which nominally non-conductive). Since the logarithmic conversion is done in the photosensing section of a solid-state image sensing device, the output from the device is already compressed and is easily handled by a small capacity CCD. Some output systems for the image sensing device of the present invention are also described.

Abstract: In this invention, a plurality of clock buffers are provided to supply clock signals to a charge transfer apparatus. These clock buffers are driven by the same basic clock which is introduced through a plurality of clock logics. Accordingly, even if the charge transfer apparatus is comprised of a multi-stage charge coupled device having a large number of stages, those clock buffers still have enough ability to drive the charge transfer apparatus with high frequency. So, the driving circuit according to this invention can drive a multi-stage charge transfer apparatus with keeping the excellent frequency characteristics, even if the charge transfer apparatus is driven with high frequency.

Abstract: A wide dynamic range photodetector comprising a photosensitive region for generating signal electrons in response to being illuminated, a collection region for storing the signal electrons generated within the photosensitive region, a shift register for receiving and outputing the signal electrons from the collection region, and a transfer gate intermediate the photosensitive region and the collection region for alternately facilitating transfer of the signal electrons from the photosensitive region for storage in the collection region, and isolating the photosensitive region from the collection region while the signal electrons are being output via the shift register.

Abstract: A charge transfer and/or amplifying device includes a surface channel region of opposite conductivity type formed on the surface of a charge transfer buried channel region, a junction gate type field effect transistor formed of source and drain regions separated from each other by the buried channel region and the surface channel region and an insulated gate electrode formed on the surface channel region, wherein the gate electrode and the source region of the junction gate type field effect transistor are electrically coupled to thereby enhance a conversion efficiency.

Abstract: A transversal filter comprises an acoustic charge transport device comprising an input contact for introducing a signal into a buried channel through which the signal is transported by a high frequency acoustic wave and a plurality of non-destructive sense electrodes overlying the channel for successively sampling the signal. A memory device is provided for storing a plurality of tap weight signals, with each tap weight signal for being associated with one of the electrodes. A multiplier system is operably connected with each of the electrodes and with the storage device for generating the product of the signal sampled at each electrode and the associated tap weight signal. A summer is operably associated with the multiplier for summing the products and thereby generating an output signal.

Abstract: A charge transfer device is equipped with a junction type field effect transistor coupled with the final stage of a transfer shift register for modulating current flowing therethrough depending upon the amount of electric charge from the transfer shift register, and the junction type field effect transistor comprises an n-type looped gate region formed in a p-type well, a p-type source region surrounded by the looped gate region, a p-type drain region opposite to the source region with respect to the looped gate region, and a p-type channel region defined in the p-type well beneath the looped gate region, wherein the p-type channel region is shallower or smaller in dopant concentration than remaining portion of the p-type well so that the current is effectively modulated with the electric charge.

Abstract: A charge transfer device comprises a charge transfer section having a charge transfer region formed in a semiconductor substrate and transfer electrodes formed on the semiconductor substrate, and a reset transistor having a floating diffusion region formed in the semiconductor substrate for receiving an electric charge transferred from the charge transfer section, a reset drain applied with a reset voltage, and a reset gate formed above a channel between the floating diffusion region and the reset drain, the reset gate being applied with a reset pulse. A a peak hold circuit is connected to the reset gate of the reset transistor for hold a peak level of the reset voltage. A potential detection circuit includes a dummy transistor having a drain connected to a voltage V.sub.DD, a source grounded through a resistor which is considerably larger than an on-resistance of the dummy transistor itself, and a gate electrode connected to an output of the peak hold circuit.

Abstract: An amplification MOSFET in a source ground form receives at its gate an output signal of a source-follower circuit through a second capacitor. The source-follower circuit, on the otherhand, receives a voltage of a first capacitor which receives a signal charge. A predetermined bias voltage is supplied to the gate of the amplification MOSFET through a switch device while the signal charge of the first capacitor is reset. According to this structure, the second capacitor can transmit only the signal component and the voltage signal itself can be amplified by the source ground type amplification MOSFET. The amplification MOSFET can be biased to its optimum operation point by the switch device during the reset period of the first capacitor; hence, sensitivity can be substantially improved with a simple circuit structure.

Abstract: An interline transfer or frame interline transfer CCD solid image sensor is adapted to read out signal charges from light receiving sections of a matrix array by means of vertical charge transfer sections and horizontal charge transfer sections. A plurality of horizontal charge transfer sections are formed for lowering the horizontal transfer frequency. The voltage transition in the transfer gate across the horizontal charge transfer sections is caused to occur stepwise or temporally slowly to improve the transfer efficiency across the horizontal charge transfer sections. A smear drain region for sweeping out unnecessary charges is formed along the horizontal charge transfer sections. The transfer electrode of the horizontal charge transfer sections connected to the busline wiring is patterned to clear contact holes provided in the smear drain region to provide for positive overflow without increasing the chip area.

Abstract: A charge detecting device comprises a floating diode for accumulating a signal charge, a source-follower amplifier for detecting a variation in a surface potential of the floating diode, a reset transistor, a transistor having a same size to the reset transistor for detecting a channel potential of the reset transistor and a reset pulse supplying means including an inverting amplifier, in which the channel potential of the reset transistor detected by the transistor is amplified and is added with a binary digit pulse inputted through an AC coupled capacitor to be made into a reset pulse which is applied to a gate electrode of the reset transistor. This allows automatic setting of each level of the suitable reset pulse in response to a variation in the channel potential of the reset transistor without any external circuits for setting reset pulse levels.

Abstract: A charge coupled device is provided with a first signal input path for supplying an information signal for transfer through a delay line, which contain an inverting amplifier, and a second signal input path which has no inverting amplifier. The first and second signal input paths are arranged in parallel to each other. The charge coupled device also has a switching means associated with the first and second signal input paths so as to selectively establishing connection between one of the first and second signal input paths and the delay line so that non-inverted and inverted information signals can be selectively supplied to the delay line.

Abstract: A solid state imaging element includes a plurality of photodetectors arranged in a two-dimensional array on a semiconductor substrate, first and second charge transfer circuits for transferring signal charges in a vertical direction and a horizontal direction, respectively, a plurality of transfer gates for controlling charge transfer from the photodetectors to the first charge transfer circuit, a scanner for controlling switching of the transfer gates, a plurality of bus lines connecting the transfer gates with the scanner, and a bus line breakage checking circuit. The bus line breakage checking circuit includes a plurality of transistors connected in series with respective bus lines, a test pad connected with the bus lines through the transistors, and a voltage applying pad for applying a voltage to control switching of the transistors. Therefore, the breakage of a bus line can be detected in a wafer test without actually operating the element, whereby time and money are saved.