Abstract: In a charge transfer device, a low impurity density region is provided in its portion forming a floating capacitor. It becomes possible thereby to reduce the capacitance of the floating capacitor and thus to ensure a larger output voltage relative to a signal charge.

Abstract: There is provided a solid-state image sensor which can optimize the I-V characteristics of MOS transistors on drive side and load side, and which can improve the sensitivity by maximizing the small-signal AC gain of a source follower amplifier. According to one embodiment of the invention, a CCD solid-state image sensor has a floating diffusion type charge detecting amplifier composed of at least one drive side MOS transistor and at least one load side MOS transistor. In a substrate of one conductivity type, there are formed two wells of the opposite conductivity type independently. The drive side MOS transistor is formed in the first well which is deeper from the top surface of the semiconductor substrate. The load side MOS transistor is formed in the shallower second well. It is possible to further improve the AC gain by depleting or neutralizing the first well for the drive MOS transistor, and at the same time neutralizing the second well for the load MOS transistor.

Abstract: A FISO analog signal acquisition system includes a plurality of CCD arrays (20a-20d), with each array containing a plurality of CCD serial registers (22). Each serial register (22) has a first cell (23) and a large number of additional cells (24) coupled in series with the first cell (24), with acquired samples being transferred along the string of additional cells (24) according to a clock signal having two or more phases, with each CCD array (20a-20d) operating in response to a set of clock signals having a different phase (P1,P2,/P1,/P2). A tapped delay line (10), or other similar hold signal generating means, produces a plurality of closely spaced-in-time sequential hold signals in response to a master hold signal. In response to each one of the hold signals, a CMOS transistor (Q.sub.x) briefly connects an associated first cell (23) to the signal to be sampled so that a series of closely spaced-in-time samples of the signal are acquired.

Abstract: In a CCD element, the influence of a parasitic capacitance existing between a floating diffusion region and a reset gate section of an output section is suppressed to increase sensitivity. In a CCD element in which a floating diffusion region (7) is connected to the final stage of a charge transfer register (1) having a CCD structure through a horizontal output gate section (5) and a reset gate section (11) is disposed between the floating diffusion region (7) and a reset drain region (10), an output gate pulse (.phi..sub.HOG) having an anti-phase of a reset pulse (.phi..sub.RG) applied to the reset gate section (11) is applied to the horizontal output gate section (5). Further, an output waveform in a signal period in a CCD linear sensor can be made flat and a signal level difference between odd-numbered and even-numbered pixels can be improved.

Abstract: A magnetic field sensor, having a charge-coupled device formed in a semiconductor region is disclosed. The magnetic field sensor has first and second contact zones, made of a heavily doped semiconductor material of a first conductivity type, located on an outer surface of the semiconductor region which is made of a semiconductor material of a second conductivity type. The magnetic field sensor also has an insulating layer, located on the outer surface of the semiconductor region, which has passages for sensor connections associated with each contact zone. The charge-coupled device has a plurality of gate electrodes located on the insulating layer which are arranged perpendicularly to the desired direction of charge propagation through the charge-coupled device. One end of at least one centrally located electrode at least partially overlaps the first contact zone while another end at least partially overlaps the second contact zone.

Abstract: An output circuit for sequentially receiving and converting charge collected in the photoelements of an image sensor and converting such charge into an output voltage. The output circuit includes a buried-channel LDD transistor having gate, source and drain electrodes. The source electrode provides a floating diffusion. When the transistor is turned off, a potential well is provided in the floating diffusion which collects charge. An output source-follower amplifier also employing buried-channel LDD transistors is connected to the floating diffusion and produces the output voltage.

Abstract: A linear acoustic charge transport circuit including an acoustic charge transport (ACT) device and a transconductance amplifier. In one embodiment the ACT device includes a bipolar injector. The ACT device can comprise either a thick channel ACT or a heterojunction ACT.

Abstract: A charge transfer device has an output structure formed, in a semiconductor substrate of a first conductivity type, of a base region of a second conductivity type, an output region of the first conductivity type formed in the base region, a reset-drain region of a second conductivity type formed separately from the base region and held at a constant potential, and a reset gate electrode formed on the semiconductor substrate between the base and reset-drain regions via an insulator film to receive a reset pulse. The base region has a portion under the output region which is designed to allow a complete depletion throughout its thickness.

Abstract: A control device for a charge detection circuit comprising a CCD final gate electrode formed on a semiconductor substrate, an electric potential barrier forming gate electrode placed adjacent to the CCD final gate electrode, a diffusion region formed adjacent to the electric potential barrier forming gate electrode, a reset transistor connected to the diffusion region, a source follower circuit which uses as an input an electric potential in the diffusion region, a sample and hold circuit for receiving the output of the source follower circuit at a specified timing, a reference voltage source which has a value determined by the dynamic range of the source follower circuit, and an integrator which integrates a difference between the output of the sample and hold circuit and the output of the reference voltage source, and applies a value obtained by the integration to the electric potential barrier forming gate electrode.

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.

Abstract: A charge transfer device includes a signal charge transfer region including a first conductivity type first low dopant concentration semiconductor region on which transfer electrodes are disposed via an insulating film, a charge storage region including a first conductivity type second low dopant concentration semiconductor region connected to the first low dopant concentration semiconductor region, a second conductivity type semiconductor region disposed on the charge storage region, a first conductivity type high dopant concentration semiconductor region disposed at the surface of and spaced from the first conductivity type second low dopant concentration semiconductor region at a region opposite the first conductivity type first low dopant concentration semiconductor region, and a detector for detecting the quantity of signal charges stored in the charge storage region from the resistance value between two points in a portion of said second conductivity type semiconductor region.

Abstract: A solid state image sensing device comprises an image sensor for outputting optical images as signal charges, a charge transfer section for transferring signal charges, a first reading section for non-destructively reading transferred signal charges as a plurality of first output signal components, a detecting section for detecting the difference between the first output signal components, a second reading section for adding the signal charges corresponding to the first output signal components which correspond to the difference signal and reading the added signal charges as a second output signal component, an adding section for inserting at least one signal component corresponding to the second output signal component to one or more first output signal components which are canceled due to charge-transfer for addition of signal charges and generating an output signal including a third output signal component, and a level lowering section for lowering the signal levels of the second and third output signal co

Abstract: A charge coupled device for sampling an analog signal voltage. If charge is inputted to a charge coupled device by the so-called phase-referred input method, a minority charge carrier source region (10) in a semiconductor body (1) is clocked in phase with a charge transfer gate (6) so that a metering potential well formed under a metering electrode (4) is alternately filled via a d.c. gate (5) with carriers to a predetermined level and then surplus carriers are drained back via the d.c. gate and the remainder exit via the transfer gate. This mechanism tends to degrade at high frequencies and, in order to improve the high frequency performance, a very short further gate (20) is provided between the d.c. gate and the metering well. This further gate is clocked in antiphase to the source region (10) and the transfer gate (6) so that it creates a rising potential barrier when the surplus carriers are being drained back, thereby isolating the metering well from the source (10) and the d.c.

Abstract: A solid-state imaging device utilizing a charge skimming transfer system includes a sampling circuit for each of a plurality of pixels for detecting a quantity of signal charge light-electricity converted by the respective pixels and outputs a voltage level in accordance therewith, and a charge input section for performing skimming transfer of the signal charge light-electricity converted by the respective pixels using the output voltage of said sampling circuit as a skimming voltage thereof.

Abstract: A floating gate junction filed-effect transistor image sensor element (10) is formed in a semiconductor layer (14). a drain region (20) of a first conductivity type of the elements (14) is formed adjacent a gate region (26). A potential barrier (98) is formed in the gate region (26) fo rcollecting carriers (102) of the second conductivity type, the barrier (98) also acting as a probing current well. A capacitor (28, 32, 48) is coupled to the gate region (26) and is operable to deliver a pulse to gate region (26) for sweeping out the carriers (102) to the substrate (12). The difference in gate bias voltage caused by the absence of the collected carriers (102) is sensed at a sense node (116) coupled to a source region (30).

Abstract: An input bias circuit employs a gate input type CCD register and an inversion-type amplifier. An output node of the inversion-type amplifier is connected to the input gate electrode of the CCD register, and an input signal to be biased is supplied to the input gate electrode. An output node of the inversion-type amplifier is connected to the floating diffusion region of the CCD register, and a signal charge is picked up from the floating diffusion region. A comparator performs comparison among the low level of the injection pulse supplied to the input diffusion region (which serves as an input diode), the potential level of the input signal supplied to the input gate electrode of the CCD register, and the level of the low-level generated by a low-level signal generating means. On the basis of this comparison, the potential level of the input signal of the CCD register is controlled such that it is higher than the low level of the injection pulse.

Abstract: A charge-coupled device includes a semiconductor body (3) having a semiconductor layer (3) of a first conductivity type adjoining a surface and means for depleting the semiconductor layer throughout its thickness while avoiding breakdown. A sequence (row) of transport electrodes are provided on the surface above the semiconductor layer and are separated by a blocking (isolating) layer from the semiconductor layer and are connected to a clock voltage source to form in the semiconductor layer mutually separated potential wells for storing and transporting information-carrying charge packets. An input stage (I) has a supply zone for supplying majority charge carriers and an input electrode. The input electrode is located between the supply zone and the transport electrodes and is separated by the isolating layer from the semiconductor surface.

Abstract: A solid-state imaging device includes on a semiconductor substrate of a first conductivity type, a well of the opposite conductivity type and, in addition, a plurality of light-sensitive elements formed in the well. A reverse bias voltage applied to the semiconductor substrate with respect to the well causes charge stored in the light-sensitive elements less than or equal to a potential barrier voltage to leak out into the semiconductor substrate. On the substrate a detection circuit detects the resistance of the semiconductor substrate and a setting circuit sets the reverse bias voltage in such a manner as to keep the potential barrier voltage constant, based on the resistance detected by the detection circuit.

Abstract: A charge-coupled device having a charge source and a floating gate input capable of sampling a voltage and converting it to a proportional charge packet, including precharging the floating gate with a quantity of charge proportional to the sampled voltage, and isolating the floating gate such that the proportional charge substantially remains on the floating gate, and a method for doing same.

Abstract: A device having at least two channels for holding electron packets receives serial data in a first channel. A blocking potential is applied to a set of electrodes to store a set of charge packets with the device. Packets are transferred to the other channel, manipulated and released to travel to an output port. Manipulation operations include arithmetic operations, logic operations, multiplexing and demultiplexing.

Abstract: A charge transfer device is fabricated on a semiconductor substrate of a first conductivity type and comprises a well formed in a surface portion of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type, a charge transfer region of the first conductivity type formed in a surface portion of the well, a floating diffusion region of the first conductivity type formed in the surface portion of the well and contiguous to the charge transfer region, an insulating film covering the surface portion of the well, and a plurality of gate electrodes provided on the insulating film and applied with driving clocks in such a manner as to produce conductive channels in the charge transfer region for transferring electric charges toward the floating diffusion region, in which the channels in the vicinity of the floating diffusion region are gradually decreased in width toward the floating diffusion region, and in which impurity atoms of the well beneath the charge transfer r

Abstract: A charge transfer device and its driving method are disclosed such that transfer pulses each having an ampitude substantially equal to that of transfer pulses applied to transfer electrodes at transfer stages before a plurality of successively-arranged transfer stages including a final transfer stage and DC offset levels so decreased gradually as to gradually make shallow the depth of potential wells formed under the transfer electrode toward the final transfer stage are applied to transfer electrode at successively-arranged plural transfer stages including the final stage.

Abstract: A horizontal transfer shift register is formed on a semiconductor substrate for use in a solid state image sensor of the charge transfer device type. The horizontal transfer shift register is coupled to receive electric charge signals in parallel and operates to serially transfer the received electric charge signals to an signal output circuit. The horizontal transfer shift register comprises a plurality of horizontal transfer electrodes formed on the substrate, a control electrode formed on the substrate adjacent to a horizontal transfer electrode adjacent to the signal output circuit, and a drain diffusion region formed in the substrate adjacent to the control electrode.

Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.

Abstract: A front-illuminated CCD of relative high quantum efficiency (QE) and high charge transfer efficiency (CTE) utilizes an open-phase region for receiving photons and two-phase gate regions (.phi..sub.1 and .phi..sub.2) for transferring electrons collected in one pixel to the next. The open-phase region is implanted with additional n-type elements (phosphorus) in order to increase the potential of the CCD channel in the open-phase region for collection of electrons and additionally implanted with concentrated and very shallow p-type elements (boron) to pin the surface of the n-channel in the open-phase region to OV, while gate region .phi..sub.1 and .phi..sub.2 are biased to -3.5V and driven to +10V by a two-phase transfer clock. The open pinned-phase (OPP) region thus permits two-phase transfer clocking and optimum reception of photons during the integration periods between transfer clock pulses.

Abstract: There is provided a one-dimensional MIM array having MIM structures arranged on an insulative substrate in a lateral direction and each used as a unit for storing a signal charge, for sequentially storing and transferring the signal charges between the adjacent MIM structures. With the above element structure, the signal charge is transferred in each of the MIM structures in a thickness direction (depth direction) thereof and stored in a capacitor. The signal charge stored in the capacitor is sequentially transferred in a lateral direction or to the next MIM structure. In order to drive the above charge transfer device, transfer pulses applied to a plurality of MIM structures constituting a one-dimensional MIM array are controlled to sequentially transfer and store the signal charges into the MIM structures starting from the MIM structure which is provided on the output terminal side of the one-dimensional MIM array.

Abstract: A bipolar injector structure, similar to a common-base amplifier circuit, is described for use as a unidirectional injector of charge for a charge-transfer device input circuit. This injector structure acts to reduce the input impedance of such devices. A plurality of bipolar injector structures may be implemented on a single ACT device channel, and electrically connected in parallel, to effect a further reduction of input impedance and a further increase in device dynamic range. By employing an input contact structure which allows charge to be injected at more than one point along the length of the channel, without perturbing charge which was injected at some earlier time, a means for forming a transversal filter function can be realized at the input contact structure in addition to that which is achieved at the output contact structure, thus permitting improved ACT device selectivity when operated as a filter.

Abstract: Disclosed is a reading register of the type formed, firstly, by a shift register of the charge-coupled device type working according to a mode other than a two-phase mode and, secondly, an output circuit. It is notably an object of the invention improve the dynamic range, in amplitude, of the output signal delivered by the output circuit for supply voltages. The reading register has a substrate, bearing a shift register and an output circuit, separated from each other by an output gate. The shift register includes a sequence of transfer stages, each having at least three electrodes receiving transfer pulses of different phases, this sequence of stages being separated from the output gate by a last transfer stage or output transfer stage having at least three successive electrodes. According to one characteristic of the invention, the last two electrodes of the transfer stage are connected to each other and receive one and the same voltage pulse.

Abstract: In interline transfer type image sensing devices, photogenerated charge is transferred from a collection node into a charge coupled shift register. The framing rate of these detectors is typically limited by the maximum readout rate of the shift register. A CCD image sensing device with multiple shift register outputs for higher framing rate, utilizes alternating shift register orientations and multiplexing of multiple shift registers to a each output in order to match the pitches of the detector columns and output bondpads. This configuration allows detectors of different size to be made more easily. This detector additionally uses a combination of low-lag photodiodes, low transfer inefficiency true two-phase charge coupled shift registers, and low noise charge sensing amplifiers to provide non-interlaced readout of the image with minimum signal loss and noise while operating at high frame rates.

Abstract: A charge-coupled device (CCD) is formed by first defining relatively deep trenches having relatively small lateral dimensions in the surface of a silicon bulk region. A relatively thin silicon dioxide layer is formed over the silicon surface and inside each trench to cover the internal surfaces thereof. Finally, respective conducting electrode layers are formed over each trench covering the silicon dioxide layer within the trench. Such a CCD structure provides improved packing density and versatility of function over a conventional surface electrode CCD structures. When used in an image-sensing device, the trench-defined CCD structure provides improved quantum efficiency, owing to the deeper potential wells which may be formed in such structures for capturing photogenerated charge carriers.

Abstract: A non-destructive charge domain multiplier and process thereof wherein the unique characteristics of the charge coupled device permits sensing the size of the charge packet as it moves past an electrode and creating a new charge packet proportional to the product of the original packet and an externally applied value. The device non-destructively senses the size of the charge packet and multiplies it with another value using a multiple metering gate variation of the "Fill and Spill" technique. The present invention therefore constitutes a unique CCD configuration which creates as an output, a charge packet proportional to the product of the charge in an input packet and an externally applied value. Thus, the present invention enables the performance of non-linear operations by CCD integrated circuits.

Abstract: A charge-coupled imager includes in a substrate of a semiconductor material a plurality of spaced photodetectors arranged in a line. The photodetectors are each of a type that can be completely depleted. A suitable photodetector is a pinned photodiode. A separate accumulation region is contiguous with one side of each of the photodetectors. A potential is applied to each accumulation region which forms an accumulation well therein which is lower than that in its respective photodiode so that charge carriers generated in the photodiode will continuously flow into the accumulation region. An anti-blooming drain is provided adjacent each accumulation region with the potential barrier between the anti-blooming drain and the accumulation region being below the potential well in the photodiode so that when the accumulation region fills with charge carriers to the level of the potential barrier any additional charge carriers will overflow into the anti-blooming drain.

Abstract: An imaging area has a substrate with a mosaic of photo diodes arranged in rows and columns on a solid state substrate. Vertical shift registers are positioned between the columns to transfer photo charges out of the photo diodes and to associated electronic circuits. Depletion layers are interposed in said substrate to separate it into areas. Pulses are applied to the depletion layers driving the transfer periods in order to prevent charge overflow, and therefore a smearing of the image.

Abstract: A solid-state image sensor comprises photoelectric converting devices (22) formed on a p type semiconductor substrate (1), transfer gates (26) for reading signal charges therefrom, scanning lines (21) for selecting the transfer gates (26), and transfer electrodes (11) of the first layer and transfer electrodes (12) of the second layer alternately disposed for transferring in the vertical direction the read signal charges. All the electrodes of the transfer gates (26) are formed integrally with the transfer electrodes (12) of the second layer, with the result that all the electrodes of the transfer gates (26) are common to the transfer electrodes of the same layer (the second layer). Although the potential wall (340) is formed in the transfer channel (3) beneath the transfer electrode (12) connected to the transfer gate (26), the same is insulated from adjacent the transfer electrode (11) on the charge transfer direction side.

Abstract: In a charge transfer device, the threshold voltage of a drive MOS transistor in an output circuit is set to be largest among those of MOS transistors of the same conductivity type which are formed on a substrate. Even under a large reset pulse, the MOS transistor is operable in a saturation region, because its threshold voltage is set to be large.

Abstract: A charge coupled device employs peak hold circuits for detecting electric charges transferred through reference registers for facilitating automatic iput bias control. The peak hold circuits are respectively connected to a pair of reference registers which are so designed that one of the reference registers has a given maximum rating and the other reference register is adapted to transfer electric charge having a given fraction of the maximum charge rating of the aforementioned one of registers. The peak hold circuits provide peak values of the outputs of the reference registers to a comparator which feedback controls the input bias of the one of the register. This controlled bias is also applied to an input bias for a signal register which is designed for transferring input electric charge.

Abstract: An output circuit for CCD imager devices or CCD delay devices is disclosed in which a depletion type second MIS transistor is connected to the drain side of a first MIS transistor constituting a source follower adapted for converting transferred signal signals into an electrical voltage, and an output voltage is supplied to the gate of the second MIS transistor. This depletion type second MIS transistor causes the drain potential of the first MIS transistor to be changed in phase with the input electrical charges to reduce the gate-to-drain capacitance of the first MIS transistor to improve the charge-to-voltage conversion gain.

Abstract: In a charge transfer device including spaced apart channels on a semiconductor substrate, first electrodes are disposed in gaps between the channels, second electrodes are disposed opposite alternate channels overlapping the adjacent first electrodes, and a third continuous electrode overlies the alternating channels and first and second electrodes in the charge transfer direction. A first clock phase is obtained by connecting alternate first electrodes with the adjacent second electrode in the direction of charge transfer, and a second clock phase is obtained by connecting the remaining first electrodes with the third electrode. The portion of the first electrode overlapped by the second electrode in the second clock phase is larger than that in the first clock phase for stable driving by first and second clock signals out of phase by 180.degree. and generated by a driver including a resonance circuit.

Abstract: In a charge-coupled SPS memory device, in which the transport takes place according to the "pushing" principle, it may occur that during the SP transport charge is injected into the substrate and diffuses via the substrate into the memory mat. In order to avoid this undesired injection of charge, the input is provided with means by which it is ensured that the storage site under the input gate is entirely empty during the SP transport.

Abstract: A solid state imaging array for generating a plurality of electrical imaging signals includes photodiodes for producing electrical charges in response to incident light, a signal processing circuit including a charge skimming electrode associated with each sensor for receiving and storing electrical charges from the associated sensor and for transferring a skimmed portion of the stored electrical charge to a respective charge coupled device. The skimmed portion of the electrical charge is determined by the magnitude of a skimming voltage applied to the respective skimming electrode. The array includes a second charge coupled device for applying different magnitude skimming voltages to each of the skimming electrodes in order to compensate for variations in the sensitivities of the photodiodes. The individual compensation is achieved for all of the photodiodes through only two external terminals.

Abstract: A method of driving a charge detection circuit of floating diffusion amplifier type including, a second conductivity type diffusion region produced on a first conductivity type semiconductor substrate or layer, a voltage barrier gate electrode adjacent the diffusion region, a CCD final gate electrode adjacent the voltage barrier production gate electrode, an MOS transistor for resetting the diffusion region incorporating the diffusion region as a source electrode, a source follower circuit for receiving the voltage of the diffusion region as an input signal. When the signal charges are transferred to the voltage well below the CCD final gate electrode, only the charges exceeding a voltage barrier below the voltage barrier gate electrode are output to the diffusion region.

Abstract: In a charge transfer device, a voltage generating cirucit generates a voltage amounting to a potential lower by ".alpha." (.alpha.: a predetermined potential) than a potential formed under a reset gate electrode when stored charges of a floating diffusion region are discharged into a drain region. A voltage step-up circuit steps up a predetermined voltage and supplies the stepped-up voltage as a reset voltage to the drain region. A comparison/control circuit generates an error voltage amounting to a difference between the output voltage of the voltage generating circuit and the stepped-up voltage, and controls the voltage step-up operation by the step-up circuit according to the error voltage. With the structure of the device, the stepped-up voltage from the voltage step-up circuit, which is supplied as a reset voltage to the drain region, is controlled according to the process parameter variations.

Abstract: There is disclosed a charge transfer device including a semiconductor substrate, a charge transfer section formed on the semiconductor substrate for transferring charges, at least two regions formed in the semiconductor substrate via a PN-junction, one of said regions receiving the charges transferred through the charge transfer section and connected to an output terminal and at least one gate electrode formed on the semiconductor substrate between the regions via an insulator film to form a MOS transistor switch which is switched for controlling the sensitivity of the output stage and the dynamic range of the output signal.

Abstract: A charge coupled device includes a plurality of first CCD shift-registers transferring charge signals in parallel and a second CCD shift-register receiving the charge signals from the first CCD shift-registers for a parallel-serial coversion, the second CCD shift-register being connected to the first CCD shift-registers through barrier regions covered with electrodes in the second CCD shift-register.

Abstract: The invention relates to a semiconductor device including a charge transfer device having an output stage (8). The output stage (8) has a read-out zone (9), a feedback capacitor (11) and an amplifier (10). An inverting input (15) of the amplifier (10) is connected to the read-out zone (9) and an output (16) of the amplifier (10) is fed back via the feedback capacitor (11) to the inverting input (15). According to the invention, the capacitor (11) is a capacitor of the MOS type and means are provided by which during operation of the charge transfer device the surface potential of a surface region (13) in the capacitor (11) is solely determined by the potential of the read-out zone (9). Consequently, the capacitance of the feedback capacitor (11) is dependent upon the potential across it, as a result of which there is a linear relation between the charge supplied to the read-out zone (9) and the voltage variation across the capacitor (11 ).

Abstract: A solid state image sensor includes a plurality of charge storage elements arranged in a matrix form on a semiconductor substrate, vertical CCDs arranged in a plurality of columns along the arrangement of the charge storage elements on the semiconductor substrate, for reading out signal charges stored in the charge storage elements, and a plurality of horizontal CCDs arranged in parallel on the substrate and extending in a direction perpendicular to the vertical CCDs, for individually transferring signal charges of each row supplied from the vertical CCDs in a horizontal direction. A channel through which the signal charge passes at the time of transfer of the signal charge between the horizontal CCDs is made wider on the signal charge output port side than on the signal charge input port side.

Abstract: A floating diffusion region and a drain region are formed separately from each other in a substrate. A reset electrode is arranged above an area located between the drain region and the floating diffusion region. A voltage step-up circuit having a reference voltage generator receiving a power source voltage for generating a reference voltage and a step-up circuit receiving a clock pulse for applying a voltage level of the clock pulse to the reference voltage applies a voltage to the drain region. The gate of a conversion E type MOS transistor for converting and outputting the charge stored in the floating diffusion region to a signal having a voltage level proportional to the charge amount is connected to the floating diffusion region. The reference voltage generator has D type MOS transistor and E type MOS transistor connected in cascade for producing the reference voltage of the value corresponding to the variation from a process center of the manufacturing process of this charge transfer device.

Abstract: A transistor (14) having a plurality of sub-transistors (26a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providing a path between one end of the gate and ground (32). The voltage drop across the elongated gate (24) sequentially reduces the gate voltage present at each of the sub-transistors (29a-f), thereby reducing the amount of current which the sub-transistors (29a-f) can conduct. The voltage controlling circuit (45) gradually reduces the current through the elongated gate (24), thereby increasing the amount of current through the sub-transistors (29a-f). The time interval over which the conductive device induces a current through the elongated gate (24) can be adjusted by positioning the connection to the gate of a transistor (62) along the elongated gate (24).

Abstract: A charge-coupled device including a semiconductor substrate of given conductivity type, a buried channel formed on the substrate of different conductivity type than the substrate, an electrically floating diffusion formed in the substrate of different conductivity type than the substrate, and a plurality of electrodes insulating from the buried channel. The electrodes are responsive to applied voltages for supplying a signal charge through the buried channel to the floating diffusion. The charged-coupled device also includes a transistor responsive to a pulse voltage signal for periodically resetting the floating diffusion to a predetermined potential. The transistor comprises an enhancement type surface channel field effect transistor.