Abstract: A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.

Abstract: A charge transfer circuit, such as a charge coupled device or other bucket brigade device, which incorporates an amplifier to assist with charge transfer.

Abstract: A charge multiplication amplifier device comprises a series arrangement of a first separation barrier facility, a temporary storage well for charge carriers, a second charge transfer barrier facility, an impact ionization facility that is operative through electric field strength effective on mobile charge carriers, and a charge collection well for receiving charge carriers so multiplied. Advantageously, the device comprises a charge collection and transfer facility (32) that is geometrically disposed next to the impact ionization facility (31) whereas impact ionization facility is controlled at a substantially static electric potential (DC1, DC2) for controlling the electric field strength. Advantageously, another embodiment of this device comprises charge collection and transfer facilities (41, 42) implemented as two (or more) independently clocked signals ?1, ?2 that require nearly two times less swing to achieve same effect.

Abstract: A method for reducing dark current within a charge coupled device includes the steps of providing three or more phases of gates separated by an insulating layer from a buried channel of the first conductivity type in a well or substrate of the second conductivity type, and a clock driver for causing the transfer of charge through the charge coupled device; providing a barrier for separating charge packets when in accumulation state; applying, at a first time period, voltages to all phases of gates sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers; after the first time period, applying, at each gate phase n having a capacitance Cn to the layer of the second conductivity type, a voltage change on the gate phase n given by &Dgr;Vn such that the sum of products of the capacitances and voltage changes is substantially zero ∑ n ⁢   ⁢

Abstract: In a connection part of vertical transfer registers with respect to a horizontal transfer register, transfer electrodes to which clocks &phgr;V1, &phgr;V2A, &phgr;V3A, &phgr;V2B, &phgr;V3B, and &phgr;V1A are applied are arranged in the cited order. In a horizontal transfer register 6, transfer is conducted by 3-phase clocks &phgr;H1A, ØH1B, and &phgr;H2. By activating clocks, signal charges of a channel denoted by A-A′ and channels equivalent thereto are first transferred to undersides of electrodes of &phgr;H1A of the horizontal transfer register. The signal charges are transferred in the rightward direction to underside of electrodes of &phgr;H1B. Subsequently, signal charges of a channel denoted by B-B′ and channels equivalent thereto are transferred to undersides of electrodes of &phgr;H1B of the horizontal transfer register, and mixed with the signal charges previously transferred.

Abstract: A CCD shift register includes a continuous buried channel over a length of the shift register, a plurality of conductor segments, a plurality of narrow bus segments, and a plurality of wide busses. Each conductor segment includes a plurality of sets of conductors, and each set of conductors includes plurality of conductors, each conductor in a set corresponding to a respective clock signal of a plurality of clock signals. Each conductor of each set extends across the buried channel. A first narrow bus segment of the plurality of narrow bus segments includes a plurality of narrow busses that are disposed parallel to and offset from the buried channel, each narrow bus corresponding to a respective clock signal of the plurality of clock signals, and each narrow bus is coupled to a respective conductor of each set of a first conductor segment.

Abstract: A two-dimensional image sensor comprises a matrix array of photodiodes and multiple vertical shift registers horizontally divided into an imaging part and a memory part. During a vertical blanking period, the imaging part receives charge packets from the photodiodes and shifts the charge packets via the memory part to a matrix array of storage cells. During a subsequent horizontal blanking period, the charge packets are restored from the storage cells to the memory part and shifted downwards by the distance of a row so that the charge packets of bottom row are shifted our into a horizontal register. Remaining charge packets are then withdrawn from the memory part to the storage cells and stored therein during a subsequent horizontal scan period. During this horizontal scan period, the memory part is maintained at such a voltage that no dark currents substantially exist and the charge packets in the horizontal register are sequentially delivered to external circuitry.

Abstract: A charge coupled device having a CCIR/EIA mode conversion function includes: a plurality of VCCD regions formed in the direction of row, the VCCD regions having a predetermined interval from one another; a plurality of HCCD regions formed at the end of the VCCD regions in the direction of column; a plurality of photodetectors regularly arranged between the VCCD regions, the photodetectors generating signal charges according to an image signal; a plurality of vertical gate electrodes formed on the VCCD regions and the photodetectors in the direction of column, the vertical gate electrodes transmitting the signal charges of the photodetectors to the HCCD regions through the VCCD regions according to applied vertical clock signals; vertical clock signal generator for supplying a predetermined number of vertical clock signals; and a selecting portion for receiving vertical clock signals from the vertical clock signal generator, the selecting portion supplying the vertical clock signals to part of the vertical gat

Abstract: A charge-coupled device comprises a substrate, a charge transfer layer on the substrate, an insulating layer on the charge transfer layer, and a sequence of electrodes divided into recurrent groups of first, second, third and fourth electrodes each, the electrodes being arranged in a single-layered structure on the insulating layer. First, second, third and fourth conductors are connected respectively to the first, second, third and fourth electrodes of each electrode group. The insulating layer permanently holds electrons in positions respectively corresponding to the second and fourth electrodes of each group. First, second, third and fourth breakdown diodes are connected respectively to the first, second, third and fourth conductors, where the first and third breakdown diodes have a first breakdown voltage and the second and fourth diodes have a second breakdown voltage higher than the first breakdown voltage.

Abstract: A charge transfer device is disclosed in which the number of transfer clocks can be decreased, and also, power consumption, the heating amount and parasitic emissions are also reduced. Three groups of electrodes are repeatedly disposed in an alternating sequence above an N-type channel (transfer channel). Among the three groups of electrodes, a predetermined DC bias voltage supplied from a DC power supply is applied to one group of electrodes. Between the remaining two groups of electrodes, a single-phase transfer clock H.phi. supplied from the exterior of the device is directly applied to one group of electrodes, while a transfer clock H.phi.' produced by delaying the transfer clock H.phi. by a predetermined delay time in a delay circuit is applied to the other group of electrodes. Also disclosed is a solid-state imaging apparatus using the above-described charge transfer device.

Abstract: The present invention is directed to methods and apparatus for accurately detecting light energy of a signal of interest (e.g., a laser pulse) even when the signal-to-noise ratio is relatively low. The present invention is further directed to accurate detection of a signal of interest even when either or both the signal of interest and background illumination vary across plural pixels of an imaging an array. For example, a signal of interest can be accurately detected even in the presence of pixel response non-uniformity and fixed pattern noise, or when the incident signal of interest is not confined laterally to a single pixel.

Abstract: Circuit blocks to which reference clock signals with different frequencies are input can be fabricated on the same substrate. A supply path of a supply voltage applied to a source region of a first PMOSFET and a first N-type well region, and a supply path of a supply voltage applied to a source region of a second PMOSFET and a second N-type well region, are isolated from each other by the first and second N-type well regions, respectively. A supply path of a supply voltage applied to a source region of a first NMOSFET and a first P-type well region, and a supply path of a supply voltage applied to a source region of a second NMOSFET and a second P-type well region, are isolated from each other by the first and second P-type well regions, respectively. The respective isolation of the supply voltage supplied path ensures that substrate potential fluctuations caused by the different frequencies do not result in a beat (a wave form distortion) being present on outputs of the circuit blocks.

Abstract: The charge coupled device cell has a semiconductor layer 20 of a first conductivity type, a buried channel 22 of a second conductivity type on the semiconductor layer 20, a first virtual gate 24 in the buried channel 22, the first virtual gate is switched between at least two potential levels, and a first bipolar gate 42 in the buried channel 22 adjacent the first virtual gate 24.

Abstract: A magnetic field sensor, having a charge-coupled device formed in a semiconductor region is disclosed. The magnetic field sensor has first and second contact zones, made of a heavily doped semiconductor material of a first conductivity type, located on an outer surface of the semiconductor region which is made of a semiconductor material of a second conductivity type. The magnetic field sensor also has an insulating layer, located on the outer surface of the semiconductor region, which has passages for sensor connections associated with each contact zone. The charge-coupled device has a plurality of gate electrodes located on the insulating layer which are arranged perpendicularly to the desired direction of charge propagation through the charge-coupled device. One end of at least one centrally located electrode at least partially overlaps the first contact zone while another end at least partially overlaps the second contact zone.

Abstract: A charge-coupled device includes a semiconductor body (3) having a semiconductor layer (3) of a first conductivity type adjoining a surface and means for depleting the semiconductor layer throughout its thickness while avoiding breakdown. A sequence (row) of transport electrodes are provided on the surface above the semiconductor layer and are separated by a blocking (isolating) layer from the semiconductor layer and are connected to a clock voltage source to form in the semiconductor layer mutually separated potential wells for storing and transporting information-carrying charge packets. An input stage (I) has a supply zone for supplying majority charge carriers and an input electrode. The input electrode is located between the supply zone and the transport electrodes and is separated by the isolating layer from the semiconductor surface.

Abstract: A solid-state imaging device includes on a semiconductor substrate of a first conductivity type, a well of the opposite conductivity type and, in addition, a plurality of light-sensitive elements formed in the well. A reverse bias voltage applied to the semiconductor substrate with respect to the well causes charge stored in the light-sensitive elements less than or equal to a potential barrier voltage to leak out into the semiconductor substrate. On the substrate a detection circuit detects the resistance of the semiconductor substrate and a setting circuit sets the reverse bias voltage in such a manner as to keep the potential barrier voltage constant, based on the resistance detected by the detection circuit.

Abstract: A front-illuminated CCD of relative high quantum efficiency (QE) and high charge transfer efficiency (CTE) utilizes an open-phase region for receiving photons and two-phase gate regions (.phi..sub.1 and .phi..sub.2) for transferring electrons collected in one pixel to the next. The open-phase region is implanted with additional n-type elements (phosphorus) in order to increase the potential of the CCD channel in the open-phase region for collection of electrons and additionally implanted with concentrated and very shallow p-type elements (boron) to pin the surface of the n-channel in the open-phase region to OV, while gate region .phi..sub.1 and .phi..sub.2 are biased to -3.5V and driven to +10V by a two-phase transfer clock. The open pinned-phase (OPP) region thus permits two-phase transfer clocking and optimum reception of photons during the integration periods between transfer clock pulses.

Abstract: There is provided a one-dimensional MIM array having MIM structures arranged on an insulative substrate in a lateral direction and each used as a unit for storing a signal charge, for sequentially storing and transferring the signal charges between the adjacent MIM structures. With the above element structure, the signal charge is transferred in each of the MIM structures in a thickness direction (depth direction) thereof and stored in a capacitor. The signal charge stored in the capacitor is sequentially transferred in a lateral direction or to the next MIM structure. In order to drive the above charge transfer device, transfer pulses applied to a plurality of MIM structures constituting a one-dimensional MIM array are controlled to sequentially transfer and store the signal charges into the MIM structures starting from the MIM structure which is provided on the output terminal side of the one-dimensional MIM array.

Abstract: A charge transfer device comprises a plurality of charge transfer sections arranged in parallel. Each of the charge transfer sections has a first and second region in which respective storage regions are provided with shift each other to form meander charge transfer channels. Channel stop regions for isolating the storage regions are extended between the charge transfer section so that the second storage region of the second region of one charge transfer section corresponds to the first storage region of the first region of another charge transfer section. As a result, signal charges are transferred efficiently between the charge transfer sections.

Abstract: A charge-coupled imager includes in a substrate of a semiconductor material a plurality of spaced photodetectors arranged in a line. The photodetectors are each of a type that can be completely depleted. A suitable photodetector is a pinned photodiode. A separate accumulation region is contiguous with one side of each of the photodetectors. A potential is applied to each accumulation region which forms an accumulation well therein which is lower than that in its respective photodiode so that charge carriers generated in the photodiode will continuously flow into the accumulation region. An anti-blooming drain is provided adjacent each accumulation region with the potential barrier between the anti-blooming drain and the accumulation region being below the potential well in the photodiode so that when the accumulation region fills with charge carriers to the level of the potential barrier any additional charge carriers will overflow into the anti-blooming drain.

Abstract: A solid-state image sensor comprises photoelectric converting devices (22) formed on a p type semiconductor substrate (1), transfer gates (26) for reading signal charges therefrom, scanning lines (21) for selecting the transfer gates (26), and transfer electrodes (11) of the first layer and transfer electrodes (12) of the second layer alternately disposed for transferring in the vertical direction the read signal charges. All the electrodes of the transfer gates (26) are formed integrally with the transfer electrodes (12) of the second layer, with the result that all the electrodes of the transfer gates (26) are common to the transfer electrodes of the same layer (the second layer). Although the potential wall (340) is formed in the transfer channel (3) beneath the transfer electrode (12) connected to the transfer gate (26), the same is insulated from adjacent the transfer electrode (11) on the charge transfer direction side.

Abstract: In a charge transfer device including spaced apart channels on a semiconductor substrate, first electrodes are disposed in gaps between the channels, second electrodes are disposed opposite alternate channels overlapping the adjacent first electrodes, and a third continuous electrode overlies the alternating channels and first and second electrodes in the charge transfer direction. A first clock phase is obtained by connecting alternate first electrodes with the adjacent second electrode in the direction of charge transfer, and a second clock phase is obtained by connecting the remaining first electrodes with the third electrode. The portion of the first electrode overlapped by the second electrode in the second clock phase is larger than that in the first clock phase for stable driving by first and second clock signals out of phase by 180.degree. and generated by a driver including a resonance circuit.

Abstract: A high speed charge-coupled sampler and rate reduction circuit is disclosed. The present invention allows measurement of high frequency input signals while reducing actual data rates for a series of accurately interleaved sampler data streams. The charge-coupled sampler includes a source means for providing a steady supply of charge and a sampling gate means adjacent to the source means for dividing the charge stream into discrete charge packets separated uniformly in time. An input gate means, adjacent to the sampling gate means, modulates the discrete charge packets, such that size of each charge packet is directly proportional to the instantaneous voltage applied to the input gate means. A plurality of sequential charge output means in turn surround and are adjacent to the input signal gate means. Each sequential charge output means comprises a transfer gate and a storage gate for transferring and storing the charge packet modulated by the input gate means.

Abstract: A first charge storage electrode (21) has a first row (21b) of teeth interdigitated with a second row (22b) of teeth of a second charge storage electrode (22). The second storage electrode (22) has a third row (22c) of teeth interdigitated with a fourth row (23b) of teeth of a third charge storage electrode (23). The first and third rows (21b and 22c) overlie one group (11b) of a series of parallel conduction channels while the second and fourth rows (22b and 23b) overlie another group (11a) of the parallel channels. A first charge transfer electrode (24) is provided to transfer charge packets into sites beneath the first storage electrode.

Abstract: A charge coupled device includes a plurality of first CCD shift-registers transferring charge signals in parallel and a second CCD shift-register receiving the charge signals from the first CCD shift-registers for a parallel-serial coversion, the second CCD shift-register being connected to the first CCD shift-registers through barrier regions covered with electrodes in the second CCD shift-register.

Abstract: The invention provides novel implementations of a latch cell in CMOS gate array technology to produce latch dissymmetry and permit a single ended data input. The dissymmetry is produced by increasing the output impedance of the second stage of the latch cell, which can be done, either in a DC or in an AC mode, or even in a mixed version of both modes.

Abstract: A serial-parallel-serial, charged-coupled device includes an array of horizontal rows and columns of closely spaced charge storage cells. Each storage cell is formed by an electrode covering an insulation layer above a semiconductor substrate. The semiconductor substrate of each storage cell includes a channel region for conducting carriers laterally through the storage cell. The channel region of each storage cell included both in a first row of the array and in any column of the array has a tilted potential gradient providing an electric field facilitating charge carrier drift within the channel region in two lateral directions, toward a neighboring storage cell of the first row and also toward a neighboring storage cell of its column.

Abstract: A photoelectric conversion apparatus in which a plurality of photoelectric conversion elements are arranged in an array, and the outputs of the photoelectric conversion elements are read. The apparatus includes a plurality of switching elements connected equivalently in parallel with the respective photoelectric conversion elements. The photoelectric conversion elements of a particular row or column are connected in series.

Abstract: The invention relates to a charge transfer device (CTD) having two or four phases, for which the speed of transferring the stored charges is increased by means of self-induction members connected to each of the clock areas of each memory element so that the capacitive impedance presented initially to the clock signal generator by the CTD becomes a substantially resistive impedance. Such a charge transfer device having an increased transfer speed is used in digital oscilloscopy or in systems for handling pictures.

Abstract: A charge-coupled device has a semiconductor body defining a charge transfer channel. Charge storage and charge transfer electrodes are provided for, respectively, defining charge wells within the charge transfer channel and transferring charge between charge wells. Two clock lines provide clock signals to the charge storage and transfer electrodes for controlling movement of charge between charge wells and to an output connection of the charge transfer channel. Signal processing means in the form of a sense amplifier are provided for processing an output from the charge transfer channel and a conductive path connects the output connection and the signal processing means. The conductive path crosses at least one of the clock lines and a conductive shielding layer extends between and is electrically isolated from the said at least one clock line and the conductive path.

Abstract: A charge transfer memory and its fabrication method are disclosed. The memory has charge transfer shift registers, with four phases and two level of electrodes, and a reading register with two phases and three levels of electrodes. At one end of each shift register, there is a final electrode contiguous with a reading storage electrode of the reading register, which is itself contiguous to a reading transfer electrode. These electrodes are made in a layer, with a second type of doping, of a semiconductor substrate with a first type of doping. Zones with a third type of doping are made facing the transfer electrodes of the reading register. According to the invention, facing the final electrode of each shift register, a zone with a fourth type of doping is made. This zone with a fourth type of doping prevents charges flowing in the reading register from returning to a shift register.

Abstract: A charge-coupled device comprising two clock electrodes (4,5) on the two opposite sides of the charge transport channel (3) and which extend the entire length of the channel. Charge storage regions (6-9) are located zigzagwise on both sides of the channel, as a result of which during charge transport the charge is transferred from one side to the other. Due to the separation of the electrodes the parasitic capacitance between them is low, achieving low power dissipation. The electrodes are located in grooves at the sides of the channel, leaving the surface of the channel unobstructed. The device can therefore serve as an image sensor of high sensitivity.

Abstract: A sampled data circuit having: two or more serially connected sampled data stages (2) each comprising switching means (6) and storage means (10); and clock means (4) for applying to the switching means of consecutive stages clock signals of respectively first and second phases alternating between first and second levels,characterized in thatthe clock signals also have a third level intermediate the first and second levels which is occupied simultaneously by the first and second phase clock signals.

Abstract: Disclosed are a charge-coupled device with lowering of output potential as well as a method for the fabrication of this device. In a known way, the device comprises, upstream on a semiconducting substrate with a first type of doping (P), a semiconducting layer with a second type of doping (N) and an insulating layer covering the former layer. Pairs of electrodes are formed on the insulating layer. Each pair has a transfer electrode and a storage electrode. Zones with a third type of doping N.sup.+) are made in the layer of a second type (N). A layer with a third type of doping (N.sup.-) is made downstream, in the layer with a second type of doping, and, downstream, there is formed at least one other pair of additional transfer and storage electrodes. A zone with a fourth type of doping (N.sup.--) is made beneath the additional transfer electrode in the layer with a third type of doping (N.sup.-).

Abstract: A charge transfer device (CTD) eliminating the background level of a detected signal provided with an input circuit comprising an injection source (12) and an electrode (16) controlling a storage potential well, which can be subdivided into an evacuation well (18) and an output well (19) separated by the separation potential produced by a separation electrode (27). This CTD is characterized in that its input circuit comprises a floating electrode (25) connected to the separation electrode (27) in order that the separation potential controls the background level and an insulation electrode (28) insulating the reference well (29) from the output well (19), during the measuring operations, the respective dopings under the floating electrode and under the separation electrode being obtained in order that the potential wells situated under each of these respective electrodes have different depths.

Abstract: A CCD is fabricated from an intermediate product comprising a body of semiconductor material having a channel region of a first conductivity type bounded by a substrate region of a second, opposite conductivity type and a surface of the body, and first and second gates overlying the surface and spaced from each other. The method comprises introducing a dopant into the channel region by way of the surface of the body. The first and second gates are opaque with respect to the dopant. The dopant is such that it forms a zone within the channel region, beneath the space between the first and second gates, and the zone is of the first conductivity type and is of a higher doping concentration than other portions of the channel region. A third gate is formed over the surface of the body of semiconductor material, the third gate being at least partially disposed across the space between the first and second gates.

Abstract: A solid state imager has a substrate with a plurality of light receiving areas, with vertical registers to transfer charges accumulated in the light receiving areas either through the vertical registers to a horizontal register section and an output terminal, or to a drain region. The transfer is accomplished by use of externally supplied driving pulses. By use of a high-speed normal-transfer operation, charges which are trapped by potential barriers and/or potential dips, and which would normally appear as noise in the form of black spots or bright spots, can be eliminated prior to the read out if the charge signals via the vertical registers and the horizontal register, whereby the output signal is produced free of such noise.

Abstract: The invention pertains to a charge transfer shift register provided with a device for voltage sensing using a floating-potential diode. Towards that end of the register which is located on the floating-potential diode side, the width of the charge transfer channel diminishes gradually and symmetrically with respect to the longitudinal axis of the register, and the electrodes have a shape which is all the more similar to that of a ring sector as they are close to the floating-potential diode. Thus, the path followed by the charges which leave it up to the floating electrode are made substantially uniform for each of these electrodes, whether the charges leave the electrode near the edges of the channel or near the longitudinal axis of the register.

Abstract: A charge transfer device comprising, photoelectric converting elements arranged along rows and columns, first charge transfer paths to horizontally transfer the charges obtained by those elements, a second charge transfer path to vertically transfer the charges transferred through the first charge transfer paths, and third charge transfer paths to couple the respective charge output parts of the first charge transfer paths and the charge input parts of the second charge transfer path corresponding to the output parts. Each third charge transfer path is connected to the first and second charge transfer paths so as to form almost an obtuse angle to those first and second paths, respectively.

Abstract: A various CCD delay element in which extra delay stages are provided. The extra stages are either held at a given potential to pass all signals therethrough and thus to not contribute to the gain or are connected to the clock signals to thereby increase the delay.

Abstract: A high-speed CCD clock driver circuit is obtained by coupling a plurality of driver circuits in parallel, with each driver circuit including a short circuit protection circuit consisting of the parallel connection of a resistor and a diode. In a further embodiment, a plurality of pre-driver circuits are connected in parallel to provide drive to the parallel-connected driver circuits.

Abstract: The invention relates to a charge-coupled device, in which the channel is provided with two or more separation regions for obtaining a desired charge subdivision, for example, for a transversal filter. Due to asymmetry in the potential distribution between the outer subchannels and the central subchannels, an inaccuracy occurs in the charge distribution, which according to the invention is eliminated for the major part by locally providing the separation channels bounding the outer subchannels with an interruption.

Abstract: In order to clear at a high speed unwanted charge in a solid image sensing element of a charge transfer type, a potential barrier for allowing passage of excessive charge in the direction of the transfer of a CCD shift register, is provided. Also, in order to clear the charge of the CCD shift register via the barrier, an overflow drain is provided. Thus, the clearing action is effected at a high speed, and also, a blooming can be eliminated.

Abstract: A CCD imager of small geometry which has increased well capacity. An additional p-type implant 112 selectively located creates a p-type region 112 below the channel region 13 of the virtual well regions 34, which increases the capacitance in the virtual well regions 34.

Abstract: An apparatus having a charge coupled device which is used as a solid state type image pickup apparatus and prior to inversion of the level of drive pulses supplied to two electrode groups from among a plurality of electrode groups of a CCD, each electrode group is disconnected once electrically from each drive pulse generating circuit, in which period two electrode groups whose level of drive pulse are inverted are electrically short-circuited, whereby all the charges in capacitors formed between the electrodes and a substrate are not discharged but about half of the charges can be reused for charging another capacitor which is formed between the electrodes and the substrate and is to be charged next, thus enabling a saving of power consumption, a reduction of heat dissipation losses, and enabling the miniaturization of the image pickup apparatus using a charge coupled device.

Abstract: A three dimensional optical image receiver having sensor stages with a programmable gain capability. Operation of the receiver occurs entirely in the charge domain upon the charge initially generated by the optical signal.

Abstract: A charge transfer device in which a number of transfer electrodes, comprised of alternating main electrodes and auxiliary electrodes, are formed on but insulated from a channel region in a semiconductor substrate for transferring charges. The transfer electrodes are formed such that the sides of each of the electrodes which are transverse to the channel direction are concave in the direction of charge transfer. These concave sides produce an additional accelerating electric field which supplements the conventional fringing fields.

Abstract: In this transverse charge transfer filter having N MOS capacitors arranged on the same semiconductor substrate and provided with electrodes, the electrode of every other MOS capacitor has its ends covered by the ends of the electrodes of two adjacent MOS capacitors, the N MOS capacitors being arranged in n rows and the charge transfer direction in two adjacent rows being opposite, which makes it possible to compensate for the effects of the displacements of the masks used for manufacturing the transverse charge transfer filters.

Abstract: A solid image-sensing device, in which CCDs or the like are used, has a light-receiving part comprising a plurality of photosensitive cells disposed linearly and functioning to generate charges corresponding to light information projected incidently thereon, first and second charge-transfer paths on opposite sides of this light-receiving part, and a third charge-transfer path for deriving charges from the first and second charge-transfer paths, signals being read out alternately from the first and second charge-transfer paths at the time of high-speed readout, signals from the first and second charge-transfer paths being collected and read out through the third charge-transfer path during low-speed readout.

Abstract: An analog transversal filter includes a charge transfer delay line, including a plurality of cells for storing electrical charge, and a multiphase clock to transfer electrical charge from cell to cell through the delay line. A plurality of injection electrodes are connected to predetermined ones of the cells to sample an electrical signal, weight the signal sample a predetermined amount, and inject a charge packet representing the weighted signal sample into the cell. An output electrode collects and sums the charge packets transferred through the delay line. In another embodiment, the filter includes a plurality of charge transfer delay lines, with a plurality of cells for storing electrical charge in each delay line.