Abstract: A photogate electrode PG has first and second sides opposed to each other. First and second semiconductor regions FD1, FD2 are arranged as spatially separated from each other on the side where the first side of the photogate electrode PG exists and along the first side. Third and fourth semiconductor regions FD3, FD4 are arranged as spatially separated from each other on the side where the second side of the photogate electrode PG exists and along the second side. First gate electrodes TX1 are provided between the photogate electrode PG and the first and third semiconductor regions FD1, FD3. Second gate electrodes TX2 are provided between the photogate electrode PG and the second and fourth semiconductor regions FD2, FD4. The first to fourth semiconductor regions FD1-FD4 are formed so as to overlap with respective p-type well regions W1-W4 and so as to be surrounded by the respective well regions W1-W4.

Abstract: A CCD color image sensor which prevents unnecessary charge from overflowing in a photoelectric conversion element. An image input apparatus having the CCD color image sensor comprises transferring unit which transfers effective charge accumulated in the photoelectric conversion element provided for each of the colors (R, G and B), extracted as an output signal, to a shift register by opening a shift gate; and discarding unit which discards unnecessary charge accumulated in the photoelectric conversion element by opening the shift gate at different timing from one color to another immediately before the photoelectric conversion element starts accumulating effective charge again. The discarding unit discards unnecessary charge immediately before effective charge accumulates, and discards unnecessary charge by opening the shift gate before unnecessary charge overflows in the photoelectric conversion element.

Abstract: In a case where a thinning operation is implemented at the point when signal charges are read out from each of pixels to thin out pixel information by lines (row), the thinning may be performed only in the vertical direction, but not in the horizontal direction. In an all-pixel-read-out type CCD image pickup element, a discharge controlling section is provided in each of VH transfer stage sections transferring signal charges from vertical CCDs to a horizontal CCD, and where a thinning mode is selected, among those signal charges transferred from a plurality of the vertical CCDs, those of a given set of columns are stopped and discharged at the respective discharge controlling sections, and those of the rest of columns are transferred to the horizontal CCD, and at the same time, those of a given set of lines (rows) are stopped and discharged for all columns, thereby performing the thinning operation over the pixel information in both the vertical and horizontal directions at the VH transfer stage.

Abstract: A charge multiplication amplifier device comprises a series arrangement of a first separation barrier facility, a temporary storage well for charge carriers, a second charge transfer barrier facility, an impact ionization facility that is operative through electric field strength effective on mobile charge carriers, and a charge collection well for receiving charge carriers so multiplied. Advantageously, the device comprises a charge collection and transfer facility (32) that is geometrically disposed next to the impact ionization facility (31) whereas impact ionization facility is controlled at a substantially static electric potential (DC1, DC2) for controlling the electric field strength. Advantageously, another embodiment of this device comprises charge collection and transfer facilities (41, 42) implemented as two (or more) independently clocked signals ?1, ?2 that require nearly two times less swing to achieve same effect.

Abstract: In a case where a thinning operation is implemented at the point when signal charges are read out from each of pixels to thin out pixel information by lines (row), the thinning may be performed only in the vertical direction, but not in the horizontal direction. In an all-pixel-read-out type CCD image pickup element, a discharge controlling section is provided in each of VH transfer stage sections transferring signal charges from vertical CCDs to a horizontal CCD, and where a thinning mode is selected, among those signal charges transferred from a plurality of the vertical CCDs, those of a given set of columns are stopped and discharged at the respective discharge controlling sections, and those of the rest of columns are transferred to the horizontal CCD, and at the same time, those of a given set of lines (rows) are stopped and discharged for all columns, thereby performing the thinning operation over the pixel information in both the vertical and horizontal directions at the VH transfer stage.

Abstract: A circuit for adding or subtracting an amount of charge from a charge sample, such as in a Charge Coupled Device (CCD), by portioning and pipelining the processing stages, to avoid introducing a memory effect. The operation, such as subtraction, is split into multiple stages, with each stage responsible for removing only a portion of the total amount of charge that is desired to be removed. The subtraction pipeline stages operate together to remove the total desired charge amount. In one embodiment each successive subtraction stage removes a corresponding lesser amount of charge. As a result, greater accuracy in the amount of charge removed is achieved as well operation at higher frequencies than previous charge subtraction approaches.

Abstract: In a case where a thinning operation is implemented at the point when signal charges are read out from each of pixels to thin out pixel information by lines (row), the thinning may be performed only in the vertical direction, but not in the horizontal direction. In an all-pixel-read-out type CCD image pickup element, a discharge controlling section is provided in each of VH transfer stage sections transferring signal charges from vertical CCDs to a horizontal CCD, and where a thinning mode is selected, among those signal charges transferred from a plurality of the vertical CCDs, those of a given set of columns are stopped and discharged at the respective discharge controlling sections, and those of the rest of columns are transferred to the horizontal CCD, and at the same time, those of a given set of lines (rows) are stopped and discharged for all columns, thereby performing the thinning operation over the pixel information in both the vertical and horizontal directions at the VH transfer stage.

Abstract: A charge transfer device is disclosed wherein three pixel rows are arranged adjacently to each other. First to third pixel rows are arranged adjacently to each other, and the charge transfer device includes a first charge transfer element for reading out and transferring signal charges generated in the first pixel row and a second charge transfer element for reading out and transferring signal charges generated in the second and third pixel rows. Second readout electrodes for reading out signal charges generated in the second pixel row into the second charge transfer element are provided with one electrode placed between adjacent pixels of the third pixel row.

Abstract: A method for reducing dark current within a charge coupled device includes the steps of providing three or more phases of gates separated by an insulating layer from a buried channel of the first conductivity type in a well or substrate of the second conductivity type, and a clock driver for causing the transfer of charge through the charge coupled device; providing a barrier for separating charge packets when in accumulation state; applying, at a first time period, voltages to all phases of gates sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers; after the first time period, applying, at each gate phase n having a capacitance Cn to the layer of the second conductivity type, a voltage change on the gate phase n given by &Dgr;Vn such that the sum of products of the capacitances and voltage changes is substantially zero ∑ n ⁢   ⁢

Abstract: A solid state image pickup device having: a mode selector for selecting one of first and second modes; a plurality of photoelectric converters for converting received light into electric charges; transfer paths each having a plurality of packets for receiving the electric charges from the plurality of photoelectric converters and transferring the electric charges in each packet; a controller for reading the electric charges from each of the plurality of photoelectric converters and supplying the read electric charges to the transfer paths; and a driver for driving the transfer means in the selected first or second mode at the number of drive phases different from the number of drive phases of the non-selected mode.

Abstract: The present invention provides a clock control method for preventing the charge couple device from saturation. The charge couple device comprises a shift register, a last stage register and a pixel processing circuit. The clock control method for preventing the charge couple device from saturation is able to reduce the charge voltage sent to the last stage register from the shift register by controlling the signal transmission clock of the last stage register and the operating period of the reset clock of the pixel processing circuit, so as to prevent the saturation situation of the charge couple device from occurring. Moreover, better image quality is obtained by the proper clock control.

Abstract: A CCD shift register includes a continuous buried channel over a length of the shift register, a plurality of conductor segments, a plurality of narrow bus segments, and a plurality of wide busses. Each conductor segment includes a plurality of sets of conductors, and each set of conductors includes plurality of conductors, each conductor in a set corresponding to a respective clock signal of a plurality of clock signals. Each conductor of each set extends across the buried channel. A first narrow bus segment of the plurality of narrow bus segments includes a plurality of narrow busses that are disposed parallel to and offset from the buried channel, each narrow bus corresponding to a respective clock signal of the plurality of clock signals, and each narrow bus is coupled to a respective conductor of each set of a first conductor segment.

Abstract: A charge transfer device comprising charge transfer means for transferring charges, a floating diffusion layer for accumulating the charges transferred from said charge transfer means, a floating gate electrode formed on said floating diffusion layer via an insulating layer, charge detection means connected to the floating gate electrode for outputting a voltage corresponding to an amount of charges accumulated in the floating diffusion layer, first precharge means connected to the floating gate electrode, the first precharge means starting precharging of the floating gate electrode responsive to transition of a first pulse voltage from a first state to a second state, the first precharge means terminating precharging of the floating gate electrode responsive to transition of the first pulse voltage from the second state to the first state, second precharge means connected to the floating diffusion layer, the second precharge means starting precharging of the floating diffusion layer responsive to transition

Abstract: A charge transfer device is disclosed in which the number of transfer clocks can be decreased, and also, power consumption, the heating amount and parasitic emissions are also reduced. Three groups of electrodes are repeatedly disposed in an alternating sequence above an N-type channel (transfer channel). Among the three groups of electrodes, a predetermined DC bias voltage supplied from a DC power supply is applied to one group of electrodes. Between the remaining two groups of electrodes, a single-phase transfer clock H.phi. supplied from the exterior of the device is directly applied to one group of electrodes, while a transfer clock H.phi.' produced by delaying the transfer clock H.phi. by a predetermined delay time in a delay circuit is applied to the other group of electrodes. Also disclosed is a solid-state imaging apparatus using the above-described charge transfer device.

Abstract: Channel coupled feedback- technology for implementing many analog and digital signal processing functions in a single-polysilicon digital IC fabrication process is described. Field effect transistors are constructed having a common channel and the substrate regions of the field effect transistors in the channel are electronically connected. Thus, a fixed amount of charge can freely move within the channel in response to the application of the signal to be processed. By sensing the charge transferred within the channel when the input signal is applied, many signal processing functions are possible. Fixed-gain amplifiers, offset compensated amplifiers, integrators, differentiators, analog-to-digital converters, digital-to-analog converters, switchable gain amplifiers, automatic gain control systems, and linear transform computation circuits are constructed entirely with field effect transistors, eliminating the need for passive components for most signal processing functions.

Abstract: In order to stabilize the reference level of an output signal from a solid-state image pick-up device, the solid-state image pick-up device includes an output circuit 12 for obtaining a picture signal Y1(t) from information charges outputted from a horizontal shift register 11, an impedance conversion circuit 13 for reducing the output impedance of the picture signal Y1(t) and a clamp circuit 14 for fixing the reference level in the picture signal Y1(t), all of which are integrated on the same semiconductor substrate.

Abstract: Signal processing involves accruing signal charge at photosensors, accumulating samples of the content of several adjacent photosensors in individual potential wells of a CCD according to a predetermined pattern, shifting them into individual stages of a first group of registers, and shifting the contents of the first group of registers into a second register to create a linear filtering operation. Accumulating the samples averages the content of adjacent pixels.

Abstract: The present invention is directed to methods and apparatus for accurately detecting light energy of a signal of interest (e.g., a laser pulse) even when the signal-to-noise ratio is relatively low. The present invention is further directed to accurate detection of a signal of interest even when either or both the signal of interest and background illumination vary across plural pixels of an imaging an array. For example, a signal of interest can be accurately detected even in the presence of pixel response non-uniformity and fixed pattern noise, or when the incident signal of interest is not confined laterally to a single pixel.

Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon wit

Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon wit

Abstract: A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.

Abstract: It is known to reduce the leakage current or dark current in charge-coupled devices with buried channels such as, for example, charge-coupled imaging devices by bringing the surface to the inverted state. In such a device, however, it is not possible to empty the channel completely locally in usual manner in that the charge is drained off through the substrate by means of a voltage pulse applied to the gates (charge reset). To be able to carry out charge reset nevertheless, the voltage pulse is applied between the substrate and the intermediate zone interposed between the substrate and the CCD channel. Since this voltage pulse is active over the entire range of the device, the device also prevents charge from being removed in locations where this is not desired when the pulse is applied.

Abstract: A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.

Abstract: A device and method for controlling the gain of a charge based signal is described. The described device and method may be used for both offset correction and for gain control. First and second charge holding gates are provided for receiving a charge packet representing a signal. A control gate partitions off at least a portion of the charge on the secondary charge holding gate. The charge not so partitioned off is then transferred onto the output line as the adjusted charge packet representing the adjusted signal, where the gain is now the ratio of areas of first charge holding gate to the sum of areas of both first and second charge holding gates. The offset of a signal can also be corrected by segregating the portion of charge representing the offset of an input signal onto the second charge holding gate.

Abstract: A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR operation, the best matching in case a perfect one does not exist. The chip disclosed herein has a fully parallel architecture in which an input word is compared to all stored words at one time. A preferred embodiment of the invention uses a four phase CCD, wherein each stored word occupies one row of the CCD and each such bit of each such word occupies two cells. Where perfect matches exist, only one comparison clock cycle is needed to compare the input word with all stored words and where there is no perfect match, the best match will be detected on a subsequent comparison pulse. Charge packets represent binary words generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines.

Abstract: A solid-state imaging device which can generate finite difference data of images at different times. There are provided with photoelectrical converting sections each of which includes photodiodes disposed in a matrix array and receives incident light to generate signal charges. A signal charge difference generating section generates a signal charge difference at different times from the signal charges generated in the photoelectrical converting section. A signal charge difference transfer section transfers the signal charge difference generated as an output of the device.

Abstract: There is provided a solid state imaging device having high-sensitivity, low-noise characteristics by reducing electrostatic capacity relating to interconnection. The solid state imaging device includes a photoelectric conversion section, a transfer section, a floating diffusion layer for receiving signal charges from the transfer section, and an output transistor having a gate electrode connected to the floating diffusion layer via an interconnection. A source and a drain of the output transistor are provided commonly within a flat p-type well of relatively thin concentration in which the photoelectric conversion section, the transfer section, and the floating diffusion layer are also provided.

Abstract: A charge coupled device according to the present invention, having an output terminal, for detecting an electric charge and for outputting a detection signal corresponding to the electric charge from the output terminal, comprises a semiconductor substrate having a main surface, further having a first, second and third regions in the main surface, both the first and second regions defining the third region therebetween, a charge supply formed in the vicinity of the first region, for supplying the electric charge to the first region, a first impurity formed in the first region, for transferring the electric charge to the third region, a floating gate electrode overlying the third region, coupled to the output terminal, for detecting the electric charge and outputting the detection signal corresponding to the electric charge from the output terminal in a first condition, for transferring the electric charge to the second region in a second condition, a transfer electrode overlying the second region, applied a c

Abstract: In CCD's, the major part of the dark current is caused by surface states. This dark current is disturbing, especially in image sensors, because the sensitivity of the camera is limited thereby. When according to the invention the integrating gates are varied periodically, the subjacent surface parts of the - buried - channel being brought periodically into inversion and into depletion, while maintaining the charge-containing capacity, a considerable reduction of the dark current can be obtained. In image sensors, voltage variation preferably occurs during the fly-back time.

Abstract: A charge transfer device includes a first input stage converting a first input signal into first signal charge, a first shift register transferring the first signal charge with a first delay amount, a second input stage converting a second input signal into second signal charge and having a first switch for selectively inputting the second signal charge to a second shift register, a third input stage converting a third input signal into third signal charge and having a second switch for selectively inputting the third signal charge to a third shift register, and an adding section for selectively adding one of the second and third signal charge to the first signal charge. The second shift register transfers the second signal charge with a second delay amount and the third shift register transfers the third signal charge with a third delay amount.

Abstract: A charge transfer device in which a charge transfer section, an output gate, a floating diffused region, a reset gate electrode, a reset drain region, a barrier gate electrode and an absorption drain region are provided in semiconductor substrate. The reset drain region for resetting or draining charges in the floating diffused region is connected via a capacitor to a constant potential terminal. The absorption drain region is provided with a voltage booster for raising the amplitude of the transfer pulse to a level higher than the power source voltage. The output voltage of the voltage booster is supplied to the absorption drain region. The channel potential beneath the barrier gate electrode is set lower than that beneath the reset gate electrode.

Abstract: The invention provides a signal processing device including sampling means (31, 41, 32) for sampling an input signal in the form of charge carrier packages and a shift register (4) having an input region (41) to which a signal sample is offered during operation, and provided with transport means (2) for transporting the signal sample to an output region (42) of the shift register. The device according to the invention is capable of adapting itself to the frequency with which the input signal is sampled in such a way that the storage of the increase in signal samples which accompanies an increase in the sampling frequency does not require additional space. For this purpose, according to the invention, the shift register comprises a transport channel (4) in which an electron-hole liquid can exist. The sampling means (31, 41, 32) are capable of sampling the input signal in the form of electron-hole droplets (71 . . .

Abstract: In an output circuit for a charge transfer device, a floating diffusion region is connected to a source side gate electrode of a double-gate read-out field effect transistor having its drain side gate electrode connected to the drain of the read-out transistor itself. Thus, the capacitance between the gate of the read-out transistor connected to the floating diffusion region and the drain of the read-out transistor can be made small, so that the total capacitance of the floating diffusion region is correspondingly reduced, with the result that a high detection sensitivity can be realized.

Abstract: A bucket brigade analog delay line with voltage limiting feedback includes an input stage for receiving an input signal and a series of delay stages coupled to the input stage for propagating the input signal through the line. Each delay stage contains a storage capacitor for holding either a signal charge or a reference charge, a transfer device for transferring charge from one stage to another at regular clock intervals, and a tap circuit for allowing external sampling of the propagated input signal. Each delay stage also includes a negative feedback amplifier for maintaining the drain terminal of the transfer device at a constant potential during charge transfer, thereby eliminating errors caused by finite output impedance of the transfer device. The negative feedback amplifier also prevents overvoltage conditions which could result in failure of the charge transfer devices.

Abstract: In a solid state image sensor, such as a CCD image sensor having lateral antiblooming protection, the level of which is controlled by an overflow gate voltage forming a barrier, the storage of electrons in the photodiode junction region of the sensor is eliminated by removing the barrier and allowing the charge to flow from the sensor's photodiode junctions into the overflow region. The charge flow is then detected as a function of the instantaneous light impinging on the photodiodes. The physical connections of the overflow gates are selected to form zones. Since the charge flow now represent the instantaneous light intensity, higher frequency components are detected than that limited by the sensor sampling rate. An amplifier is connected to sense the charge flow from each zone. With the range of light intensity being large the amplifier is provided with a logarithmic feed back element. This element provides compression of a signal representing the sensed charge flow.

Abstract: A solid imaging device that minimizes the degradation in charge transfer efficiency attributable to narrow channel effect by enlarging the apparent width of the horizontal output gate outlet. Miniaturization of the floating diffusion (FD) region is not hampered despite the apparent widening of the horizontal output gate outlet. The inventive imaging device utilizes a floating diffusion amplifier as the charge detector that detects a charge signal transferred from a horizontal CCD. In this device structure, ions are implanted into the substrate surface side of the region adjacent to the FD region in the horizontal output gate in such a manner that the channel potential of the adjacent region will become appropriately deeper than that of the forward-half region next to the adjacent region.

Abstract: A solid state image sensing device comprising first and second horizontal shift registers of two-phase drive system, a smear drain region disposed in an opposing relation to a first storage section of the second horizontal shift register to which the first phase drive pulse of the second horizontal shift register is applied and a channel stop region disposed in an opposing relation to a second storage section of the second horizontal shift register to which the second phase drive pulse is applied, wherein a smear component is drained to the smear drain region, and a hole component is drained to the channel stop region for thereby reducing a dark current of the second horizontal shift register to about that of the first horizontal shift register. Therefore, a dark current in the horizontal shift register of the solid state image sensing device can be reduced.

Abstract: An exploiting or readout circuit for a linear or matrix type photodetector array is of the multiplex type, such as a charge-coupled device (CCD). The exploiting circuit has a number of input stages corresponding to the number of photodetectors or similar photosites, and the gains of the input stages are established as a function of the fields of view of their associated photodetectors. In one embodiment the input stages each comprise a storage device formed of a first and a second storage electrode separated by a dividing electrode, the storage electrodes having respective surface areas selected in a relation that varies as a function of solid angle field of view of the respective photodetector. In another embodiment the input stage can include an OpAmp with a negative feedback capacitor whose value is selected as a function of the viewing solid angle of the respective photodetector.

Abstract: An image sensing device that outputs a signal logarithmically proportional to the intensity of the incident light. The image sensing device makes use of a sub-threshold current flowing between the drain and source of a MOS transistor when the gate voltage is below the threshold voltage (above which the MOS transistor is nominally conductive and below which nominally non-conductive). Since the logarithmic conversion is done in the photosensing section of a solid-state image sensing device, the output from the device is already compressed and is easily handled by a small capacity CCD. Some output systems for the image sensing device of the present invention are also described.

Abstract: A wide dynamic range photodetector comprising a photosensitive region for generating signal electrons in response to being illuminated, a collection region for storing the signal electrons generated within the photosensitive region, a shift register for receiving and outputing the signal electrons from the collection region, and a transfer gate intermediate the photosensitive region and the collection region for alternately facilitating transfer of the signal electrons from the photosensitive region for storage in the collection region, and isolating the photosensitive region from the collection region while the signal electrons are being output via the shift register.

Abstract: A charge coupled device includes a second conductivity type first horizontal channel in a first conductivity type semiconductor substrate, a second conductivity type second horizontal channel in the substrate at a predetermined distance from the first horizontal channel, and a second conductivity type transfer channel connecting the first horizontal channel with the second horizontal channel to enable transfer of charges from the first horizontal channel to the second horizontal channel. The pinning potential of the transfer channel is larger in absolute value than the pinning potential of the first and second horizontal channels, and the gate voltage pinning the transfer channel is smaller in absolute value than the gate voltage pinning the first and second horizontal channels.

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Abstract: A charge-coupled device includes a semiconductor body (3) having a semiconductor layer (3) of a first conductivity type adjoining a surface and means for depleting the semiconductor layer throughout its thickness while avoiding breakdown. A sequence (row) of transport electrodes are provided on the surface above the semiconductor layer and are separated by a blocking (isolating) layer from the semiconductor layer and are connected to a clock voltage source to form in the semiconductor layer mutually separated potential wells for storing and transporting information-carrying charge packets. An input stage (I) has a supply zone for supplying majority charge carriers and an input electrode. The input electrode is located between the supply zone and the transport electrodes and is separated by the isolating layer from the semiconductor surface.

Abstract: A solid-state imaging device includes on a semiconductor substrate of a first conductivity type, a well of the opposite conductivity type and, in addition, a plurality of light-sensitive elements formed in the well. A reverse bias voltage applied to the semiconductor substrate with respect to the well causes charge stored in the light-sensitive elements less than or equal to a potential barrier voltage to leak out into the semiconductor substrate. On the substrate a detection circuit detects the resistance of the semiconductor substrate and a setting circuit sets the reverse bias voltage in such a manner as to keep the potential barrier voltage constant, based on the resistance detected by the detection circuit.

Abstract: A charge transfer device and its driving method are disclosed such that transfer pulses each having an ampitude substantially equal to that of transfer pulses applied to transfer electrodes at transfer stages before a plurality of successively-arranged transfer stages including a final transfer stage and DC offset levels so decreased gradually as to gradually make shallow the depth of potential wells formed under the transfer electrode toward the final transfer stage are applied to transfer electrode at successively-arranged plural transfer stages including the final stage.

Abstract: A horizontal transfer shift register is formed on a semiconductor substrate for use in a solid state image sensor of the charge transfer device type. The horizontal transfer shift register is coupled to receive electric charge signals in parallel and operates to serially transfer the received electric charge signals to an signal output circuit. The horizontal transfer shift register comprises a plurality of horizontal transfer electrodes formed on the substrate, a control electrode formed on the substrate adjacent to a horizontal transfer electrode adjacent to the signal output circuit, and a drain diffusion region formed in the substrate adjacent to the control electrode.

Abstract: A front-illuminated CCD of relative high quantum efficiency (QE) and high charge transfer efficiency (CTE) utilizes an open-phase region for receiving photons and two-phase gate regions (.phi..sub.1 and .phi..sub.2) for transferring electrons collected in one pixel to the next. The open-phase region is implanted with additional n-type elements (phosphorus) in order to increase the potential of the CCD channel in the open-phase region for collection of electrons and additionally implanted with concentrated and very shallow p-type elements (boron) to pin the surface of the n-channel in the open-phase region to OV, while gate region .phi..sub.1 and .phi..sub.2 are biased to -3.5V and driven to +10V by a two-phase transfer clock. The open pinned-phase (OPP) region thus permits two-phase transfer clocking and optimum reception of photons during the integration periods between transfer clock pulses.

Abstract: Disclosed is a reading register of the type formed, firstly, by a shift register of the charge-coupled device type working according to a mode other than a two-phase mode and, secondly, an output circuit. It is notably an object of the invention improve the dynamic range, in amplitude, of the output signal delivered by the output circuit for supply voltages. The reading register has a substrate, bearing a shift register and an output circuit, separated from each other by an output gate. The shift register includes a sequence of transfer stages, each having at least three electrodes receiving transfer pulses of different phases, this sequence of stages being separated from the output gate by a last transfer stage or output transfer stage having at least three successive electrodes. According to one characteristic of the invention, the last two electrodes of the transfer stage are connected to each other and receive one and the same voltage pulse.

Abstract: A charge-coupled imager includes in a substrate of a semiconductor material a plurality of spaced photodetectors arranged in a line. The photodetectors are each of a type that can be completely depleted. A suitable photodetector is a pinned photodiode. A separate accumulation region is contiguous with one side of each of the photodetectors. A potential is applied to each accumulation region which forms an accumulation well therein which is lower than that in its respective photodiode so that charge carriers generated in the photodiode will continuously flow into the accumulation region. An anti-blooming drain is provided adjacent each accumulation region with the potential barrier between the anti-blooming drain and the accumulation region being below the potential well in the photodiode so that when the accumulation region fills with charge carriers to the level of the potential barrier any additional charge carriers will overflow into the anti-blooming drain.

Abstract: A solid-state image sensor comprises photoelectric converting devices (22) formed on a p type semiconductor substrate (1), transfer gates (26) for reading signal charges therefrom, scanning lines (21) for selecting the transfer gates (26), and transfer electrodes (11) of the first layer and transfer electrodes (12) of the second layer alternately disposed for transferring in the vertical direction the read signal charges. All the electrodes of the transfer gates (26) are formed integrally with the transfer electrodes (12) of the second layer, with the result that all the electrodes of the transfer gates (26) are common to the transfer electrodes of the same layer (the second layer). Although the potential wall (340) is formed in the transfer channel (3) beneath the transfer electrode (12) connected to the transfer gate (26), the same is insulated from adjacent the transfer electrode (11) on the charge transfer direction side.