Abstract: In a first light emission control device, a clock signal is generated, and after a first driving sequence starts to be performed in which the respective states of light-emitting elements in a first light-emitting element array are sequentially switched synchronously with the clock signal, at a particular time point a characteristic of the clock signal is changed from a first characteristic to a second characteristic. After the change, in a second light emission control device, a second driving sequence is performed in which the respective states of light-emitting elements in a second light-emitting element array are sequentially switched synchronously with the clock signal.

Abstract: A gate driving circuit according to an embodiment and a display panel including the same are disclosed. The gate driving circuit according to the embodiment includes: a controller configured to charge and discharge a first control node that pulls up an output voltage and a second control node that pulls down the output voltage; an output unit including a pull-up transistor configured to apply a gate high voltage to an output node in response to a charging voltage of the first control node, and a pull-down transistor configured to apply a gate low voltage to the output node in response to a charging voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; and a compensation unit configured to change the charging voltage of the second control node in response to an output of the sensing unit.

Abstract: A shift register and a method of driving the same, a gate driving circuit, and a display panel are disclosed. The shift register includes a display control circuit coupled to a pull-up node, a first power supply and a first control terminal respectively; a cascade output circuit coupled to a second clock terminal, the pull-up node and a cascade output terminal; a sensing control circuit coupled to the pull-up node, the cascade output terminal, a second control terminal and a third control terminal respectively; and a signal output circuit coupled to the pull-up node, a first clock terminal and a signal output terminal.

Abstract: Provided is a display driving circuit, which includes a pull-up control unit and a pull-up unit electrically connected to the pull-up control unit via a first node. The pull-up unit includes a capacitor and a first transistor. A first end of the capacitor is electrically connected to a clock signal input end and a second end of the capacitor is electrically connected to the first node. The gate of the first transistor is electrically connected to the first node, the source of the first transistor is electrically connected to the clock signal input end, the drain of the first transistor is electrically connected to a signal output end.

Abstract: The present disclosure relates to an array substrate gate driving unit and an apparatus thereof, a driving method and a display apparatus. The array substrate gate driving unit includes: an input circuit, connected with an input signal terminal and a pull-up node PU; a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU; a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD; an output circuit, connected with a clock signal terminal CLK, a second voltage signal terminal and a control circuit; a reset circuit, connected with a reset signal terminal Reset, the first voltage signal terminal and the pull-up node PU; and the control circuit, connected with the pull-up node PU and the output circuit.

Abstract: A scan driver that includes a plurality of stages of scan driving circuits is provided.

Abstract: Embodiments of the present disclosure provide a shift register and a driving method thereof and a gate driving circuit. The shift register comprises an inputting circuit, a first outputting circuit, and a second outputting circuit. The first outputting circuit may comprise a first pulling-up sub-circuit, a first outputting sub-circuit, a first pulling-down sub-circuit, and a switching sub-circuit. A controlling terminal of switching sub-circuit is coupled to a controlling terminal of the first pulling-up sub-circuit. An inputting terminal of the switching sub-circuit is coupled to the outputting terminal of a first outputting sub-circuit. The second outputting circuit may comprise a second pulling-up sub-circuit, a second outputting sub-circuit, and a second pulling-down sub-circuit. An inputting terminal of the second pulling-up sub-circuit is coupled to an outputting terminal of the switching sub-circuit.

Abstract: A display device includes a plurality of scan lines, a plurality of data lines, a plurality of pixel units, a plurality of gate driving circuits, and a plurality of connection lines. The scan lines extend in a first direction. The data lines extend in a second direction. The gate driving circuits extend in the first direction, and each of the gate driving circuits crosses through at least two of the pixel units. At least two gate driving circuits are included between two adjacent rows of the pixel units. The connection lines extend in the second direction and are electrically connected to the gate driving circuits. At least part of the connection lines overlap the data lines. The connection lines include a plurality of output lines and a plurality of signal lines. The output lines are electrically connected to the scan lines.

Abstract: The present disclosure relates to a shift register unit circuit, a method for driving the same, a gate drive circuit and a display panel. The shift register unit circuit includes a first switch circuit configured to transmit an input signal to a first node; a second switch circuit configured to transmit a first voltage to a signal output; a third switch circuit configured to transmit a second clock signal to a second node; fourth switch circuit configured to transmit the second voltage signal to a third node; a fifth switch circuit configured to transmit a second voltage signal to the signal output; a sixth switch circuit configured to transmit the second voltage signal to a fourth node; a first capacitor connected between the second clock signal and the third node; and a second capacitor connected between the first node and the second node.

Abstract: A shift register includes a first switch and a second switch coupled to a first node, a pull-down circuit selectively connecting the first node to a voltage end according to a potential of a second node, a control circuit, and an input stage circuit which may receive a previous-stage shift register output signal, a next-stage shift register output signal, and at least one scanning order logic signal. The first switch receives clock signals. A first output end of the input stage circuit outputs the previous-stage shift register output signal or the next-stage shift register output signal to a control end of the second switch based on the scanning order logic signal. The previous-stage shift register output signal or the next-stage shift register output signal triggers a second output end of the input stage circuit to output the scanning order logic signal to an input end of the control circuit.

Abstract: A shift register unit, a gate driving circuit and a display device are provided. The shift register unit includes an input sub-circuit, a first output sub-circuit, a second output sub-circuit, an output resetting sub-circuit, a node resetting sub-circuit and a capacitor sub-circuit. A control end of the output resetting sub-circuit is connected to a second reference voltage signal end, so as to provide a second reference voltage signal from the second reference voltage signal end with a rising edge within a relatively short time period.

Abstract: The present disclosure provides a gate driving circuit, a gate driving method and a display method. The gate driving circuit includes a pull-up node control circuitry, a pull-down node control circuitry, a display storage circuitry, a compensation storage circuitry and a compensation storage control circuitry. The compensation storage control circuitry is connected to an input terminal, a pull-down control voltage terminal, a pull-up node, a pull-down node, and a second terminal of the compensation storage circuitry, and configured to enable the pull-down control voltage terminal to be electrically connected to the second terminal of the compensation storage circuitry under the control of the input terminal so as to charge the compensation storage circuitry, and enable the second terminal of the compensation storage circuitry to be electrically connected to the pull-up node.

Abstract: A reset circuit for compensating a level reduction at a first node during a first stage without affecting levels during a second stage includes a reset portion, a reset control portion, and at least three input terminals. The reset portion is coupled to the first and second input terminals, and a second node, and is configured to be turned on if the second node is at a first level, to electrically couple the second and first input terminals. The reset control portion is coupled to the first, second, and third input terminals, and the second node, and is configured to electrically couple the second input terminal with the second node if the first input terminal is at the first level, and to electrically couple the second node with the third input terminal if the second input terminal is at a second level.

Abstract: The present disclosure proposes a scanning driver for driving scan lines row by row. The scanning driver includes cascaded scanning circuits. Each scanning circuit includes a pull-up control module, a driving module, a pull-down module, a pull-down holding module, and a constant low voltage supply. The pull-up control module includes a first transistor, a second transistor, and a third transistor.

Abstract: The invention disclosure a GOA circuit and a liquid crystal display. The GOA circuit including an electrical potential pull-down controlling circuit and a plurality of GOA sub circuits in cascade connection, the electrical potential pull-down controlling circuit comprising a first voltage limited transistor, a second filter transistor and a third transistor. The first voltage limited transistor, and the second filter transistor a reconnected in series and between the output terminal of the initial scanning signal, STV signal and the control terminal of the third transistor, the control terminal of the first voltage limited transistor and the first terminal of the third transistor is connected to the first power terminal and the second terminal of the third transistor is connected to the GOA sub circuit. By this design, the damage from the large static electricity to the GOA sub circuit can be avoided.

Abstract: A shift register and driving method thereof, and a gate driving circuit. The shift register of the present disclosure comprises: an input unit for controlling whether the signal of a first input end is inputted to a charging unit; a charging unit for charging a pull-up node; a pull-up unit for maintaining a high level of the pull-up node; a high level output unit for controlling whether the high level is outputted to the output end according to the level of the pull-up node; a pull-down unit for pulling down the level of the pull-up node and outputting the low level to the output end; a low level output unit for outputting the low level to the output end. The gate driving circuit of the present disclosure is formed by cascading a plurality of the above shift registers.

Abstract: The present disclosure relates to the technical field of communication. There is provided a shift register unit and a gate driving circuit for decreasing noise interferences, enhancing stability of the shift register unit, and at the same reducing the size of the shift register unit.

Abstract: The present invention provides a GOA circuit of LTPS semiconductor TFT, employed for forward scan transmission, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors and comprises a transmission part (100), a transmission control part (200), an information storage part (300), a data erase part (400), an output control part (500) and an output buffer part (600).

Abstract: The present invention provides a GOA circuit of LTPS semiconductor TFT, employed for backward scan transmission, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors and the Nth GOA unit comprises a transmission part (100), a transmission control part (200), an information storage part (300), a data erase part (400), an output control part (500) and an output buffer part (600).

Abstract: There is provided a shift register unit and driving method thereof, a gate driving circuit and display device. By setting the voltage stabilizing capacitor (C) connected to the pull-up node (P), the shift register unit utilizes the voltage stabilizing capacitor (C2) to stabilize the potential at the pull-up node (P), so as to make the signal output from the shift register unit more stable; and at the same time, uses a very small quantity of transistors and capacitors to compose the shift register unit, so that the wiring area of the gate driving circuit is greatly reduced to provide a technical support for the design of a liquid crystal display device with a narrower frame. In the meantime, since the structure of the gate driving circuit is simplified, the manufacturing process of the gate driving circuit is simplified and the cost for manufacturing is reduced.

Abstract: An output thin film transistor threshold voltage offset compensation circuit, a GOA circuit, and a display. The circuit includes: a first capacitor, comprising a first electrode and a second electrode, the first electrode being connected to the gate of an output thin film transistor and receiving a charge signal, the second electrode being connected to the drain of the output thin film transistor, the first capacitor being used for, under the action of the charge signal, making the first electrode and the second electrode have a same voltage, so that a voltage difference between the drain and the source of the output thin film transistor is equal to a threshold voltage thereof; a first switch unit, connected to the drain and the source of the output thin film transistor, and opening under the action of a first clock signal, so that a voltage difference between the gate and the source of the output thin film transistor is equal to the threshold voltage thereof.

Abstract: To provide a pulse signal output circuit and a shift register which have lower power consumption, are not easily changed over time, and have a longer lifetime. A pulse signal output circuit includes a first input signal generation circuit; a second input signal generation circuit; an output circuit which includes a first transistor and a second transistor and outputs a pulse signal in response to a signal output from the first and second input signal generation circuits; a monitor circuit which obtains the threshold voltages of the first and second transistors; and a power supply output circuit which generates a power supply potential raised by a potential higher than or equal to a potential which is equal to or substantially equal to the threshold voltage and supplies the power supply potential to the first and second input signal generation circuits. A shift register includes the pulse signal output circuit.

Abstract: A stage circuit includes first and second supply units. The first supply unit outputs a scan signal to a first output terminal. The second supply unit outputs an emission control signal to a second output terminal. The second supply unit includes a first transistor and a second transistor. The first transistor is between a first power source and the second output terminal, and has a gate electrode coupled to a first node. The second transistor is between the second output terminal and a second power source, and has a gate electrode coupled to a second node. Third and fourth transistors are coupled in series between the first power source and first node. A gate electrode of the third transistor is coupled to the third input terminal, and a gate electrode of the fourth transistor is coupled to the sixth input terminal.

Abstract: A shift register of a gate driving circuit includes a pull-up unit for pulling up a first output signal and a first gate signal to a high voltage level according to a driving voltage and a high-frequency clock signal, a start-up unit for transmitting a second gate signal, an energy-store unit for providing the driving voltage to the pull-up unit according to the second gate signal, a first discharging unit for pulling down the driving voltage to a first voltage level according to a first control signal, a first leakage-preventing unit for turning off the first discharging unit when the first gate signal reaches the high voltage level, a first pull-down unit for respectively pulling down the first output and first gate signals to the first and a second voltage levels according to the first control signal, and a first control unit for generating the first control signal.

Abstract: A shift register unit comprises a pull-up control module (1), a pull-up module (2), a pull-down control module (3) and a pull-down module (4), the pull-up control module (1) is connected to a first clock signal terminal (CLK1), a first voltage signal terminal (V1), a second voltage signal terminal (V2) and a pull-up control node (Aj), the pull-up module (2) is connected to the pull-up control node (A), the first voltage signal terminal (V1) and a signal output terminal (OUTPUT) of present stage, the pull-down control module (3) is connected to a second clock signal terminal (CLK2), a signal input terminal (INPUT) and a pull-down control node (B), and the pull-down module (4) is connected to the pull-down control node (B), the first clock signal terminal (CLK1) and the signal output terminal (OUTPUT) of present stage. There also disclose a gate driving circuit and a display device.

Abstract: Embodiments of the present invention provides a shift register unit, driving method thereof, a shift register and a display device. A switch-off module is provided to disconnect electrical connections between a pull-up node and a precharge module and between the pull-up node and a pull-down module at a pull-up stage. As a result, it is able to prevent excessive electric leakage of a GOA circuit, thereby to improve the reliability and power consumption of the GOA circuit with an Oxide TFT.

Abstract: A shift register unit, a shift register and a display apparatus, insulate a start charging capacitor from the gate of the driving transistor, and adopt a dual pulling-down structure for the gate of the driving transistor and the output terminal simultaneously thereby the transistor can be turned off normally and a leakage is prevented.

Abstract: A shift register unit, a display panel including the shift register unit and a display device including the display panel are provided. The shift register unit includes a driving module, an output module, a first transistor, and a second transistor. By connecting a second electrode of the first transistor in the shift register unit with an output terminal of the shift register unit, even if a channel width of the second transistor is considerably smaller than a theoretical design value, abnormal output of the shift register unit can be avoided.

Abstract: The present disclosure provides a shift register for delaying and outputting a received startup voltage and meanwhile outputting a voltage inverse to the delayed startup voltage.

Abstract: A flip-flop of the present invention includes: an input terminal; an output terminal; a first control signal terminal and a second control signal terminal; a first output section including a bootstrap capacitor, the first output section being connected to the first control signal terminal and the output terminal; a second output section connected to a first output section source and the output terminal; a first input section connected to the input terminal, the first input section charging the bootstrap capacitor; a discharge section discharging the bootstrap capacitor; a second input section connected to the input terminal, the second input section being also connected to the second output section; a reset section controlling the discharge section and the second output section, the reset section being connected to the second control signal terminal; a first initialization section controlling the first output section; a second initialization section controlling the first input section; and a third initializat

Abstract: A signal processing circuit of the present invention includes: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, a third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal. The first node becomes active in a case where the first input terminal becomes active. The second node becomes active in a case where the second input terminal becomes active. The output terminal is connected to the first power supply via the resistor. With the configuration, it is possible to have an improvement in operational stability of the signal processing circuit.

Abstract: A pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit are provided. A clock signal is supplied to one of transistors connected to a first output terminal. A power supply potential is applied to one of transistors connected to a second output terminal. Thus, power consumed by discharge and charge of the transistor included in the second output terminal can be reduced. Further, since a potential is supplied from a power source to the second output terminal, sufficient charge capability can be obtained.

Abstract: A buffer circuit driving method for driving a buffer circuit including: an output terminal; a first transistor connected to a signal source of a clock signal that is of at least a first voltage or a second voltage lower than the first voltage, for supplying the first voltage to the output terminal; and a second transistor connected to a voltage source that supplies a third voltage lower than the first voltage, for supplying the third voltage to the output terminal, includes: causing the first transistor to switch to a conducting state in a period where the clock signal is of the first voltage; and causing the first transistor and the second transistor to switch to the conducting state in a period where the clock signal is of the second voltage, following the period where the clock signal is of the first voltage.

Abstract: A shift register circuit and a shading waveform generating method are disclosed. The shift register circuit includes plural stages of shift registers. Each stage of the shift register includes an output transistor, an input unit and a gate-shading circuit. The output transistor is configured for generating an output signal of the stage of the shift register. The input unit is configured for controlling a voltage level on a gate terminal of the output transistor. The gate-shading circuit includes a first switch, a second switch and a third switch. The first switch is configured for outputting a control signal. The second switch is configured for pulling down the voltage level on the gate terminal of the output transistor according to the control signal. The third switch is configured for pulling down a level on an output terminal of the output transistor according to the control signal.

Abstract: A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

Abstract: A shift register includes a previous signal receiving unit, a next signal receiving unit, a control unit and a voltage stabilizing switch. The shift register controls an outputting signal by continuously stabilized voltage generated from cooperating operation of the units and switch.

Abstract: A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit.

Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: An LCD device is configured to drive a plurality of shift register units using two clock signals having different driving abilities. Each shift register unit may thus generate a stronger signal for triggering a next-stage shift register unit, thereby improving cold-start. When the LCD device has been activated over a predetermined period of time, the driving ability of the clock signal having higher driving ability is gradually lowered, thereby reducing power consumption.

Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit and a pull-up unit. The pull-up unit is utilized for pulling up a gate signal according to a system clock and a driving control voltage. The input unit is employed for outputting the driving control voltage according to a control signal and an input signal. The input unit includes a switch device having a first transistor and a second transistor. The first transistor has a first end for receiving the input signal, a gate end for receiving the control signal, and a second end. The second transistor has a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the driving control voltage.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit.

Abstract: The present invention provides a shift register unit, a shift register circuit, an array substrate and a display device, and relates to the area of display manufacturing. The time of the bias working on the de-noising transistor can be reduced without affecting the circuit stability, so that the operational lifespan of the device can be extended. A shift register comprises: a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a de-noising control model. The present invention is used for manufacturing displays.

Abstract: A display substrate includes a base substrate including a display area and a peripheral area, a pixel disposed on the display area, wherein the pixel includes; a pixel transistor connected to a gate line and a data line which cross each other, and a pixel electrode connected to the pixel transistor and the pixel electrode, and a gate driving circuit disposed on the peripheral area, wherein the gate driving circuit outputs a gate signal to the gate line and comprises a plurality of stages, an n-th stage of the gate driving circuit including a plurality of circuit transistors and a boosting capacitor including a first capacitor and a second capacitor, the plurality of circuit transistors and the first capacitor being disposed on a first area and the second capacitor being disposed on a second area of the peripheral area positioned between the first area and the display area.

Abstract: A gate drive circuit includes a plurality of stages connected one after another to each other. Each of the stages includes a charging section, a driving section, a discharging section, a holding section and a holding control section. The driving section pulls up a high level of a first clock signal to output a gate signal. The discharging section discharges a voltage potential of a first node to a first off-voltage. The holding section holds a voltage potential of the first node to the first off-voltage. The holding control section receives the first clock signal and a second clock signal. The holding control section holds a voltage potential of the holding section to a second off-voltage through a second node in accordance with the second clock signal to prevent floating of the holding section.

Abstract: An object is to suppress the stress applied to a transistor as well as suppressing generation of defective operation. In a pulse output circuit having a function of outputting a pulse signal and including a transistor that controls whether to set the pulse signal to high level, in a period during which the pulse signal output from the pulse output circuit is at low level, the potential of a gate of a transistor is not set to a constant value but intermittently set to a value higher than the potential VSS. Accordingly, the stress to the transistor can be suppressed.

Abstract: A gate driver is provided. The gate driver includes a plurality of cascade-connected stages. The k-th stage of the stages includes a switching unit for connecting a first node to a second node, a driving unit for generating an output signal in accordance with a voltage of the first node, and an input unit for inputting an output signal of a (k?1)-th stage of the stages and an output signal of a (k+1)-th stage of the stages to the second node.

Abstract: There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB.

Abstract: An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.